if_athioctl.h revision 237522
1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: head/sys/dev/ath/if_athioctl.h 237522 2012-06-24 07:01:49Z adrian $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Ioctl-related defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHIOCTL_H 36116743Ssam#define _DEV_ATH_ATHIOCTL_H 37116743Ssam 38227327Sadrianstruct ath_tx_aggr_stats { 39227327Sadrian u_int32_t aggr_pkts[64]; 40227327Sadrian u_int32_t aggr_single_pkt; 41227327Sadrian u_int32_t aggr_nonbaw_pkt; 42227327Sadrian u_int32_t aggr_aggr_pkt; 43227327Sadrian u_int32_t aggr_baw_closed_single_pkt; 44227327Sadrian u_int32_t aggr_low_hwq_single_pkt; 45227327Sadrian u_int32_t aggr_sched_nopkt; 46233989Sadrian u_int32_t aggr_rts_aggr_limited; 47227327Sadrian}; 48227327Sadrian 49234090Sadrianstruct ath_intr_stats { 50234090Sadrian u_int32_t sync_intr[32]; 51234090Sadrian}; 52234090Sadrian 53116743Ssamstruct ath_stats { 54116743Ssam u_int32_t ast_watchdog; /* device reset by watchdog */ 55116743Ssam u_int32_t ast_hardware; /* fatal hardware error interrupts */ 56116743Ssam u_int32_t ast_bmiss; /* beacon miss interrupts */ 57155492Ssam u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */ 58138570Ssam u_int32_t ast_bstuck; /* beacon stuck interrupts */ 59116743Ssam u_int32_t ast_rxorn; /* rx overrun interrupts */ 60116743Ssam u_int32_t ast_rxeol; /* rx eol interrupts */ 61116743Ssam u_int32_t ast_txurn; /* tx underrun interrupts */ 62138570Ssam u_int32_t ast_mib; /* mib interrupts */ 63116743Ssam u_int32_t ast_intrcoal; /* interrupts coalesced */ 64138570Ssam u_int32_t ast_tx_packets; /* packet sent on the interface */ 65116743Ssam u_int32_t ast_tx_mgmt; /* management frames transmitted */ 66116743Ssam u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ 67116743Ssam u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ 68116743Ssam u_int32_t ast_tx_encap; /* tx encapsulation failed */ 69116743Ssam u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ 70116743Ssam u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */ 71116743Ssam u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */ 72116743Ssam u_int32_t ast_tx_linear; /* tx linearized to cluster */ 73116743Ssam u_int32_t ast_tx_nodata; /* tx discarded empty frame */ 74116743Ssam u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ 75116743Ssam u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ 76116743Ssam u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 77116743Ssam u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ 78116743Ssam u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ 79116743Ssam u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ 80116743Ssam u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ 81116743Ssam u_int32_t ast_tx_noack; /* tx frames with no ack marked */ 82116743Ssam u_int32_t ast_tx_rts; /* tx frames with rts enabled */ 83116743Ssam u_int32_t ast_tx_cts; /* tx frames with cts enabled */ 84116743Ssam u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ 85127779Ssam u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ 86127779Ssam u_int32_t ast_tx_protect; /* tx frames with protection */ 87170530Ssam u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */ 88170530Ssam u_int32_t ast_tx_ctsext; /* tx frames with cts extension */ 89116743Ssam u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */ 90116743Ssam u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ 91116743Ssam u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ 92116743Ssam u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 93116743Ssam u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 94116743Ssam u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ 95138570Ssam u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */ 96116743Ssam u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ 97218689Sadrian u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */ 98119147Ssam u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ 99127779Ssam u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ 100138570Ssam u_int32_t ast_rx_packets; /* packet recv on the interface */ 101138570Ssam u_int32_t ast_rx_mgt; /* management frames received */ 102119147Ssam u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ 103138570Ssam int8_t ast_tx_rssi; /* tx rssi of last ack */ 104138570Ssam int8_t ast_rx_rssi; /* rx rssi from histogram */ 105161187Ssam u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */ 106138570Ssam u_int32_t ast_be_xmit; /* beacons transmitted */ 107116743Ssam u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */ 108116743Ssam u_int32_t ast_per_cal; /* periodic calibration calls */ 109116743Ssam u_int32_t ast_per_calfail;/* periodic calibration failed */ 110116743Ssam u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 111116743Ssam u_int32_t ast_rate_calls; /* rate control checks */ 112116743Ssam u_int32_t ast_rate_raise; /* rate control raised xmit rate */ 113116743Ssam u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ 114138570Ssam u_int32_t ast_ant_defswitch;/* rx/default antenna switches */ 115138570Ssam u_int32_t ast_ant_txswitch;/* tx antenna switches */ 116138570Ssam u_int32_t ast_ant_rx[8]; /* rx frames with antenna */ 117138570Ssam u_int32_t ast_ant_tx[8]; /* tx frames with antenna */ 118159894Ssam u_int32_t ast_cabq_xmit; /* cabq frames transmitted */ 119159894Ssam u_int32_t ast_cabq_busy; /* cabq found busy */ 120160992Ssam u_int32_t ast_tx_raw; /* tx frames through raw api */ 121170530Ssam u_int32_t ast_ff_txok; /* fast frames tx'd successfully */ 122170530Ssam u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */ 123170530Ssam u_int32_t ast_ff_rx; /* fast frames rx'd */ 124170530Ssam u_int32_t ast_ff_flush; /* fast frames flushed from staging q */ 125170530Ssam u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */ 126170530Ssam int8_t ast_rx_noise; /* rx noise floor */ 127186904Ssam u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */ 128186904Ssam u_int32_t ast_tdma_update;/* TDMA slot timing updates */ 129186904Ssam u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */ 130186904Ssam u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */ 131186904Ssam u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/ 132186904Ssam u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/ 133188195Ssam u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */ 134188195Ssam u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */ 135188555Ssam u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */ 136211299Sadrian u_int32_t ast_be_missed; /* missed beacons */ 137217684Sadrian u_int32_t ast_ani_cal; /* ANI calibrations performed */ 138218378Sadrian u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */ 139221965Sadrian u_int32_t ast_rx_halfgi; /* RX half-GI */ 140221965Sadrian u_int32_t ast_rx_2040; /* RX 40mhz frame */ 141221965Sadrian u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */ 142221965Sadrian u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */ 143221965Sadrian u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */ 144218689Sadrian u_int32_t ast_rx_hi_rx_chain; 145218924Sadrian u_int32_t ast_tx_htprotect; /* HT tx frames with protection */ 146221965Sadrian u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */ 147220772Sadrian u_int32_t ast_tx_timeout; /* Global TX timeout */ 148220782Sadrian u_int32_t ast_tx_cst; /* Carrier sense timeout */ 149221965Sadrian u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */ 150221965Sadrian u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */ 151221965Sadrian u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */ 152226798Sadrian u_int32_t ast_tx_swretries; /* software TX retries */ 153226798Sadrian u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */ 154226798Sadrian u_int32_t ast_tx_data_underrun; 155226798Sadrian u_int32_t ast_tx_delim_underrun; 156227868Sadrian u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */ 157226798Sadrian u_int32_t ast_tx_getnobuf; 158226798Sadrian u_int32_t ast_tx_getbusybuf; 159226798Sadrian u_int32_t ast_tx_intr; 160226798Sadrian u_int32_t ast_rx_intr; 161227868Sadrian u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */ 162227868Sadrian u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */ 163232764Sadrian u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */ 164232764Sadrian u_int32_t ast_pad[1]; 165116743Ssam}; 166116743Ssam 167116743Ssam#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) 168188557Ssam#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq) 169236833Sadrian#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq) 170116743Ssam 171123044Ssamstruct ath_diag { 172138570Ssam char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ 173138570Ssam u_int16_t ad_id; 174138570Ssam#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ 175138570Ssam#define ATH_DIAG_IN 0x4000 /* copy in parameters */ 176138570Ssam#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ 177138570Ssam#define ATH_DIAG_ID 0x0fff 178138570Ssam u_int16_t ad_in_size; /* pack to fit, yech */ 179138570Ssam caddr_t ad_in_data; 180138570Ssam caddr_t ad_out_data; 181138570Ssam u_int ad_out_size; 182123044Ssam 183123044Ssam}; 184123044Ssam#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) 185224245Sadrian#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag) 186123044Ssam 187119783Ssam/* 188119783Ssam * Radio capture format. 189119783Ssam */ 190237522Sadrian#define ATH_RX_RADIOTAP_PRESENT_BASE ( \ 191154140Ssam (1 << IEEE80211_RADIOTAP_TSFT) | \ 192119783Ssam (1 << IEEE80211_RADIOTAP_FLAGS) | \ 193119783Ssam (1 << IEEE80211_RADIOTAP_RATE) | \ 194123928Ssam (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 195154140Ssam (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 196154140Ssam (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ 197170530Ssam (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 198119783Ssam 0) 199119783Ssam 200237522Sadrian#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 201237522Sadrian#define ATH_RX_RADIOTAP_PRESENT \ 202237522Sadrian (ATH_RX_RADIOTAP_PRESENT_BASE | \ 203237522Sadrian (1 << IEEE80211_RADIOTAP_VENDOREXT) | \ 204237522Sadrian (1 << IEEE80211_RADIOTAP_EXT) | \ 205237522Sadrian 0) 206237522Sadrian#else 207237522Sadrian#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE 208237522Sadrian#endif /* ATH_ENABLE_RADIOTAP_PRESENT */ 209237522Sadrian 210237522Sadrian#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 211237522Sadrian/* 212237522Sadrian * This is higher than the vendor bitmap used inside 213237522Sadrian * the Atheros reference codebase. 214237522Sadrian */ 215237522Sadrian 216237522Sadrian/* Bit 8 */ 217237522Sadrian#define ATH_RADIOTAP_VENDOR_HEADER 8 218237522Sadrian 219237522Sadrian/* 220237522Sadrian * Using four chains makes all the fields in the 221237522Sadrian * per-chain info header be 4-byte aligned. 222237522Sadrian */ 223237522Sadrian#define ATH_RADIOTAP_MAX_CHAINS 4 224237522Sadrian 225237522Sadrian/* 226237522Sadrian * The vendor radiotap header data needs to be: 227237522Sadrian * 228237522Sadrian * + Aligned to a 4 byte address 229237522Sadrian * + .. so all internal fields are 4 bytes aligned; 230237522Sadrian * + .. and no 64 bit fields are allowed. 231237522Sadrian * 232237522Sadrian * So padding is required to ensure this is the case. 233237522Sadrian * 234237522Sadrian * Note that because of the lack of alignment with the 235237522Sadrian * vendor header (6 bytes), the first field must be 236237522Sadrian * two bytes so it can be accessed by alignment-strict 237237522Sadrian * platform (eg MIPS.) 238237522Sadrian */ 239237522Sadrianstruct ath_radiotap_vendor_hdr { /* 30 bytes */ 240237522Sadrian uint8_t vh_version; /* 1 */ 241237522Sadrian uint8_t vh_rx_chainmask; /* 1 */ 242237522Sadrian 243237522Sadrian /* At this point it should be 4 byte aligned */ 244237522Sadrian uint32_t evm[ATH_RADIOTAP_MAX_CHAINS]; /* 4 * 4 = 16 */ 245237522Sadrian 246237522Sadrian uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */ 247237522Sadrian uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */ 248237522Sadrian 249237522Sadrian uint8_t vh_phyerr_code; /* Phy error code, or 0xff */ 250237522Sadrian uint8_t vh_rs_status; /* RX status */ 251237522Sadrian uint8_t vh_rssi; /* Raw RSSI */ 252237522Sadrian uint8_t vh_pad1[1]; /* Pad to 4 byte boundary */ 253237522Sadrian} __packed; 254237522Sadrian#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 255237522Sadrian 256119783Ssamstruct ath_rx_radiotap_header { 257119783Ssam struct ieee80211_radiotap_header wr_ihdr; 258237522Sadrian 259237522Sadrian#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 260237522Sadrian /* Vendor extension header bitmap */ 261237522Sadrian uint32_t wr_ext_bitmap; /* 4 */ 262237522Sadrian 263237522Sadrian /* 264237522Sadrian * This padding is needed because: 265237522Sadrian * + the radiotap header is 8 bytes; 266237522Sadrian * + the extension bitmap is 4 bytes; 267237522Sadrian * + the tsf is 8 bytes, so it must start on an 8 byte 268237522Sadrian * boundary. 269237522Sadrian */ 270237522Sadrian uint32_t wr_pad1; 271237522Sadrian#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 272237522Sadrian 273237522Sadrian /* Normal radiotap fields */ 274154140Ssam u_int64_t wr_tsf; 275154140Ssam u_int8_t wr_flags; 276119783Ssam u_int8_t wr_rate; 277170530Ssam int8_t wr_antsignal; 278170530Ssam int8_t wr_antnoise; 279170530Ssam u_int8_t wr_antenna; 280170530Ssam u_int8_t wr_pad[3]; 281170530Ssam u_int32_t wr_chan_flags; 282119783Ssam u_int16_t wr_chan_freq; 283170530Ssam u_int8_t wr_chan_ieee; 284170530Ssam int8_t wr_chan_maxpow; 285237522Sadrian 286237522Sadrian#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 287237522Sadrian /* 288237522Sadrian * Vendor header section, as required by the 289237522Sadrian * presence of the vendor extension bit and bitmap 290237522Sadrian * entry. 291237522Sadrian * 292237522Sadrian * XXX This must be aligned to a 4 byte address? 293237522Sadrian * XXX or 8 byte address? 294237522Sadrian */ 295237522Sadrian struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */ 296237522Sadrian 297237522Sadrian /* 298237522Sadrian * Because of the lack of alignment enforced by the above 299237522Sadrian * header, this vendor section won't be aligned in any 300237522Sadrian * useful way. So, this will include a two-byte version 301237522Sadrian * value which will force the structure to be 4-byte aligned. 302237522Sadrian */ 303237522Sadrian struct ath_radiotap_vendor_hdr wr_v; 304237522Sadrian#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 305170530Ssam} __packed; 306119783Ssam 307119783Ssam#define ATH_TX_RADIOTAP_PRESENT ( \ 308154140Ssam (1 << IEEE80211_RADIOTAP_TSFT) | \ 309119783Ssam (1 << IEEE80211_RADIOTAP_FLAGS) | \ 310119783Ssam (1 << IEEE80211_RADIOTAP_RATE) | \ 311123928Ssam (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ 312123928Ssam (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 313170530Ssam (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 314119783Ssam 0) 315119783Ssam 316119783Ssamstruct ath_tx_radiotap_header { 317119783Ssam struct ieee80211_radiotap_header wt_ihdr; 318154140Ssam u_int64_t wt_tsf; 319154140Ssam u_int8_t wt_flags; 320119783Ssam u_int8_t wt_rate; 321123928Ssam u_int8_t wt_txpower; 322123928Ssam u_int8_t wt_antenna; 323170530Ssam u_int32_t wt_chan_flags; 324170530Ssam u_int16_t wt_chan_freq; 325170530Ssam u_int8_t wt_chan_ieee; 326170530Ssam int8_t wt_chan_maxpow; 327170530Ssam} __packed; 328119783Ssam 329224245Sadrian/* 330224245Sadrian * DFS ioctl commands 331224245Sadrian */ 332224245Sadrian 333224245Sadrian#define DFS_SET_THRESH 2 334224245Sadrian#define DFS_GET_THRESH 3 335224245Sadrian#define DFS_RADARDETECTS 6 336224245Sadrian 337224245Sadrian/* 338224245Sadrian * DFS ioctl parameter types 339224245Sadrian */ 340224245Sadrian#define DFS_PARAM_FIRPWR 1 341224245Sadrian#define DFS_PARAM_RRSSI 2 342224245Sadrian#define DFS_PARAM_HEIGHT 3 343224245Sadrian#define DFS_PARAM_PRSSI 4 344224245Sadrian#define DFS_PARAM_INBAND 5 345224245Sadrian#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */ 346224245Sadrian#define DFS_PARAM_RELSTEP_EN 7 347224245Sadrian#define DFS_PARAM_RELSTEP 8 348224245Sadrian#define DFS_PARAM_RELPWR_EN 9 349224245Sadrian#define DFS_PARAM_RELPWR 10 350224245Sadrian#define DFS_PARAM_MAXLEN 11 351224245Sadrian#define DFS_PARAM_USEFIR128 12 352224245Sadrian#define DFS_PARAM_BLOCKRADAR 13 353224245Sadrian#define DFS_PARAM_MAXRSSI_EN 14 354224245Sadrian 355224245Sadrian/* FreeBSD-specific start at 32 */ 356224245Sadrian#define DFS_PARAM_ENABLE 32 357224245Sadrian#define DFS_PARAM_EN_EXTCH 33 358224245Sadrian 359116743Ssam#endif /* _DEV_ATH_ATHIOCTL_H */ 360