1116743Ssam/*- 2186904Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3116743Ssam * All rights reserved. 4116743Ssam * 5116743Ssam * Redistribution and use in source and binary forms, with or without 6116743Ssam * modification, are permitted provided that the following conditions 7116743Ssam * are met: 8116743Ssam * 1. Redistributions of source code must retain the above copyright 9116743Ssam * notice, this list of conditions and the following disclaimer, 10116743Ssam * without modification. 11116743Ssam * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12116743Ssam * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13116743Ssam * redistribution must be conditioned upon including a substantially 14116743Ssam * similar Disclaimer requirement for further binary redistribution. 15116743Ssam * 16116743Ssam * NO WARRANTY 17116743Ssam * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18116743Ssam * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19116743Ssam * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20116743Ssam * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21116743Ssam * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22116743Ssam * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23116743Ssam * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24116743Ssam * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25116743Ssam * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26116743Ssam * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27116743Ssam * THE POSSIBILITY OF SUCH DAMAGES. 28116743Ssam * 29116743Ssam * $FreeBSD: releng/11.0/sys/dev/ath/if_athioctl.h 298760 2016-04-29 01:51:27Z adrian $ 30116743Ssam */ 31116743Ssam 32116743Ssam/* 33116743Ssam * Ioctl-related defintions for the Atheros Wireless LAN controller driver. 34116743Ssam */ 35116743Ssam#ifndef _DEV_ATH_ATHIOCTL_H 36116743Ssam#define _DEV_ATH_ATHIOCTL_H 37116743Ssam 38227327Sadrianstruct ath_tx_aggr_stats { 39227327Sadrian u_int32_t aggr_pkts[64]; 40227327Sadrian u_int32_t aggr_single_pkt; 41227327Sadrian u_int32_t aggr_nonbaw_pkt; 42227327Sadrian u_int32_t aggr_aggr_pkt; 43227327Sadrian u_int32_t aggr_baw_closed_single_pkt; 44227327Sadrian u_int32_t aggr_low_hwq_single_pkt; 45227327Sadrian u_int32_t aggr_sched_nopkt; 46233989Sadrian u_int32_t aggr_rts_aggr_limited; 47227327Sadrian}; 48227327Sadrian 49234090Sadrianstruct ath_intr_stats { 50234090Sadrian u_int32_t sync_intr[32]; 51234090Sadrian}; 52234090Sadrian 53116743Ssamstruct ath_stats { 54116743Ssam u_int32_t ast_watchdog; /* device reset by watchdog */ 55116743Ssam u_int32_t ast_hardware; /* fatal hardware error interrupts */ 56116743Ssam u_int32_t ast_bmiss; /* beacon miss interrupts */ 57155492Ssam u_int32_t ast_bmiss_phantom;/* beacon miss interrupts */ 58138570Ssam u_int32_t ast_bstuck; /* beacon stuck interrupts */ 59116743Ssam u_int32_t ast_rxorn; /* rx overrun interrupts */ 60116743Ssam u_int32_t ast_rxeol; /* rx eol interrupts */ 61116743Ssam u_int32_t ast_txurn; /* tx underrun interrupts */ 62138570Ssam u_int32_t ast_mib; /* mib interrupts */ 63116743Ssam u_int32_t ast_intrcoal; /* interrupts coalesced */ 64138570Ssam u_int32_t ast_tx_packets; /* packet sent on the interface */ 65116743Ssam u_int32_t ast_tx_mgmt; /* management frames transmitted */ 66116743Ssam u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ 67116743Ssam u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ 68116743Ssam u_int32_t ast_tx_encap; /* tx encapsulation failed */ 69116743Ssam u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ 70116743Ssam u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */ 71116743Ssam u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */ 72116743Ssam u_int32_t ast_tx_linear; /* tx linearized to cluster */ 73116743Ssam u_int32_t ast_tx_nodata; /* tx discarded empty frame */ 74116743Ssam u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ 75116743Ssam u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ 76116743Ssam u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 77116743Ssam u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ 78116743Ssam u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ 79116743Ssam u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ 80116743Ssam u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ 81116743Ssam u_int32_t ast_tx_noack; /* tx frames with no ack marked */ 82116743Ssam u_int32_t ast_tx_rts; /* tx frames with rts enabled */ 83116743Ssam u_int32_t ast_tx_cts; /* tx frames with cts enabled */ 84116743Ssam u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ 85127779Ssam u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ 86127779Ssam u_int32_t ast_tx_protect; /* tx frames with protection */ 87170530Ssam u_int32_t ast_tx_ctsburst;/* tx frames with cts and bursting */ 88170530Ssam u_int32_t ast_tx_ctsext; /* tx frames with cts extension */ 89116743Ssam u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */ 90116743Ssam u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ 91116743Ssam u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ 92116743Ssam u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 93116743Ssam u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 94116743Ssam u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ 95138570Ssam u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */ 96116743Ssam u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ 97218689Sadrian u_int32_t ast_rx_phy[64]; /* rx PHY error per-code counts */ 98119147Ssam u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ 99127779Ssam u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ 100138570Ssam u_int32_t ast_rx_packets; /* packet recv on the interface */ 101138570Ssam u_int32_t ast_rx_mgt; /* management frames received */ 102119147Ssam u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ 103138570Ssam int8_t ast_tx_rssi; /* tx rssi of last ack */ 104138570Ssam int8_t ast_rx_rssi; /* rx rssi from histogram */ 105161187Ssam u_int8_t ast_tx_rate; /* IEEE rate of last unicast tx */ 106138570Ssam u_int32_t ast_be_xmit; /* beacons transmitted */ 107116743Ssam u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */ 108116743Ssam u_int32_t ast_per_cal; /* periodic calibration calls */ 109116743Ssam u_int32_t ast_per_calfail;/* periodic calibration failed */ 110116743Ssam u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 111116743Ssam u_int32_t ast_rate_calls; /* rate control checks */ 112116743Ssam u_int32_t ast_rate_raise; /* rate control raised xmit rate */ 113116743Ssam u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ 114138570Ssam u_int32_t ast_ant_defswitch;/* rx/default antenna switches */ 115138570Ssam u_int32_t ast_ant_txswitch;/* tx antenna switches */ 116138570Ssam u_int32_t ast_ant_rx[8]; /* rx frames with antenna */ 117138570Ssam u_int32_t ast_ant_tx[8]; /* tx frames with antenna */ 118159894Ssam u_int32_t ast_cabq_xmit; /* cabq frames transmitted */ 119159894Ssam u_int32_t ast_cabq_busy; /* cabq found busy */ 120160992Ssam u_int32_t ast_tx_raw; /* tx frames through raw api */ 121170530Ssam u_int32_t ast_ff_txok; /* fast frames tx'd successfully */ 122170530Ssam u_int32_t ast_ff_txerr; /* fast frames tx'd w/ error */ 123170530Ssam u_int32_t ast_ff_rx; /* fast frames rx'd */ 124170530Ssam u_int32_t ast_ff_flush; /* fast frames flushed from staging q */ 125170530Ssam u_int32_t ast_tx_qfull; /* tx dropped 'cuz of queue limit */ 126170530Ssam int8_t ast_rx_noise; /* rx noise floor */ 127186904Ssam u_int32_t ast_tx_nobuf; /* tx dropped 'cuz no ath buffer */ 128186904Ssam u_int32_t ast_tdma_update;/* TDMA slot timing updates */ 129186904Ssam u_int32_t ast_tdma_timers;/* TDMA slot update set beacon timers */ 130186904Ssam u_int32_t ast_tdma_tsf; /* TDMA slot update set TSF */ 131186904Ssam u_int16_t ast_tdma_tsfadjp;/* TDMA slot adjust+ (usec, smoothed)*/ 132186904Ssam u_int16_t ast_tdma_tsfadjm;/* TDMA slot adjust- (usec, smoothed)*/ 133188195Ssam u_int32_t ast_tdma_ack; /* TDMA tx failed 'cuz ACK required */ 134188195Ssam u_int32_t ast_tx_raw_fail;/* raw tx failed 'cuz h/w down */ 135188555Ssam u_int32_t ast_tx_nofrag; /* tx dropped 'cuz no ath frag buffer */ 136211299Sadrian u_int32_t ast_be_missed; /* missed beacons */ 137217684Sadrian u_int32_t ast_ani_cal; /* ANI calibrations performed */ 138218378Sadrian u_int32_t ast_rx_agg; /* number of aggregate frames RX'ed */ 139221965Sadrian u_int32_t ast_rx_halfgi; /* RX half-GI */ 140221965Sadrian u_int32_t ast_rx_2040; /* RX 40mhz frame */ 141221965Sadrian u_int32_t ast_rx_pre_crc_err; /* RX pre-delimiter CRC error */ 142221965Sadrian u_int32_t ast_rx_post_crc_err; /* RX post-delimiter CRC error */ 143221965Sadrian u_int32_t ast_rx_decrypt_busy_err; /* RX decrypt engine busy error */ 144218689Sadrian u_int32_t ast_rx_hi_rx_chain; 145218924Sadrian u_int32_t ast_tx_htprotect; /* HT tx frames with protection */ 146221965Sadrian u_int32_t ast_rx_hitqueueend; /* RX hit descr queue end */ 147220772Sadrian u_int32_t ast_tx_timeout; /* Global TX timeout */ 148220782Sadrian u_int32_t ast_tx_cst; /* Carrier sense timeout */ 149221965Sadrian u_int32_t ast_tx_xtxop; /* tx exceeded TXOP */ 150221965Sadrian u_int32_t ast_tx_timerexpired; /* tx exceeded TX_TIMER */ 151221965Sadrian u_int32_t ast_tx_desccfgerr; /* tx desc cfg error */ 152226798Sadrian u_int32_t ast_tx_swretries; /* software TX retries */ 153226798Sadrian u_int32_t ast_tx_swretrymax; /* software TX retry max limit reach */ 154226798Sadrian u_int32_t ast_tx_data_underrun; 155226798Sadrian u_int32_t ast_tx_delim_underrun; 156227868Sadrian u_int32_t ast_tx_aggr_failall; /* aggregate TX failed in its entirety */ 157226798Sadrian u_int32_t ast_tx_getnobuf; 158226798Sadrian u_int32_t ast_tx_getbusybuf; 159226798Sadrian u_int32_t ast_tx_intr; 160226798Sadrian u_int32_t ast_rx_intr; 161227868Sadrian u_int32_t ast_tx_aggr_ok; /* aggregate TX ok */ 162227868Sadrian u_int32_t ast_tx_aggr_fail; /* aggregate TX failed */ 163232764Sadrian u_int32_t ast_tx_mcastq_overflow; /* multicast queue overflow */ 164238507Sadrian u_int32_t ast_rx_keymiss; 165240639Sadrian u_int32_t ast_tx_swfiltered; 166250665Sadrian u_int32_t ast_tx_node_psq_overflow; 167250346Sadrian u_int32_t ast_rx_stbc; /* RX STBC frame */ 168250326Sadrian u_int32_t ast_tx_nodeq_overflow; /* node sw queue overflow */ 169298760Sadrian u_int32_t ast_tx_ldpc; /* TX LDPC frame */ 170298760Sadrian u_int32_t ast_tx_stbc; /* TX STBC frame */ 171298760Sadrian u_int32_t ast_pad[10]; 172116743Ssam}; 173116743Ssam 174116743Ssam#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) 175188557Ssam#define SIOCZATHSTATS _IOWR('i', 139, struct ifreq) 176236833Sadrian#define SIOCGATHAGSTATS _IOWR('i', 141, struct ifreq) 177116743Ssam 178123044Ssamstruct ath_diag { 179138570Ssam char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ 180138570Ssam u_int16_t ad_id; 181138570Ssam#define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ 182138570Ssam#define ATH_DIAG_IN 0x4000 /* copy in parameters */ 183138570Ssam#define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ 184138570Ssam#define ATH_DIAG_ID 0x0fff 185138570Ssam u_int16_t ad_in_size; /* pack to fit, yech */ 186138570Ssam caddr_t ad_in_data; 187138570Ssam caddr_t ad_out_data; 188138570Ssam u_int ad_out_size; 189123044Ssam 190123044Ssam}; 191123044Ssam#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) 192224245Sadrian#define SIOCGATHPHYERR _IOWR('i', 140, struct ath_diag) 193123044Ssam 194238632Sadrian 195119783Ssam/* 196238632Sadrian * The rate control ioctl has to support multiple potential rate 197238632Sadrian * control classes. For now, instead of trying to support an 198238632Sadrian * abstraction for this in the API, let's just use a TLV 199238632Sadrian * representation for the payload and let userspace sort it out. 200238632Sadrian */ 201238632Sadrianstruct ath_rateioctl_tlv { 202238632Sadrian uint16_t tlv_id; 203238632Sadrian uint16_t tlv_len; /* length excluding TLV header */ 204238632Sadrian}; 205238632Sadrian 206238632Sadrian/* 207238632Sadrian * This is purely the six byte MAC address. 208238632Sadrian */ 209238632Sadrian#define ATH_RATE_TLV_MACADDR 0xaab0 210238632Sadrian 211238632Sadrian/* 212238638Sadrian * The rate control modules may decide to push a mapping table 213238638Sadrian * of rix -> net80211 ratecode as part of the update. 214238638Sadrian */ 215238638Sadrian#define ATH_RATE_TLV_RATETABLE_NENTRIES 64 216238638Sadrianstruct ath_rateioctl_rt { 217238638Sadrian uint16_t nentries; 218238638Sadrian uint16_t pad[1]; 219238638Sadrian uint8_t ratecode[ATH_RATE_TLV_RATETABLE_NENTRIES]; 220238638Sadrian}; 221238638Sadrian#define ATH_RATE_TLV_RATETABLE 0xaab1 222238638Sadrian 223238638Sadrian/* 224238632Sadrian * This is the sample node statistics structure. 225238632Sadrian * More in ath_rate/sample/sample.h. 226238632Sadrian */ 227238632Sadrian#define ATH_RATE_TLV_SAMPLENODE 0xaab2 228238632Sadrian 229238632Sadrianstruct ath_rateioctl { 230238632Sadrian char if_name[IFNAMSIZ]; /* if name */ 231238632Sadrian union { 232238632Sadrian uint8_t macaddr[IEEE80211_ADDR_LEN]; 233238632Sadrian uint64_t pad; 234238632Sadrian } is_u; 235238632Sadrian uint32_t len; 236238632Sadrian caddr_t buf; 237238632Sadrian}; 238238632Sadrian#define SIOCGATHNODERATESTATS _IOWR('i', 149, struct ath_rateioctl) 239238929Sadrian#define SIOCGATHRATESTATS _IOWR('i', 150, struct ath_rateioctl) 240238632Sadrian 241238632Sadrian/* 242119783Ssam * Radio capture format. 243119783Ssam */ 244237522Sadrian#define ATH_RX_RADIOTAP_PRESENT_BASE ( \ 245154140Ssam (1 << IEEE80211_RADIOTAP_TSFT) | \ 246119783Ssam (1 << IEEE80211_RADIOTAP_FLAGS) | \ 247119783Ssam (1 << IEEE80211_RADIOTAP_RATE) | \ 248123928Ssam (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 249154140Ssam (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 250154140Ssam (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ 251170530Ssam (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 252119783Ssam 0) 253119783Ssam 254237522Sadrian#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 255237522Sadrian#define ATH_RX_RADIOTAP_PRESENT \ 256237522Sadrian (ATH_RX_RADIOTAP_PRESENT_BASE | \ 257237522Sadrian (1 << IEEE80211_RADIOTAP_VENDOREXT) | \ 258237522Sadrian (1 << IEEE80211_RADIOTAP_EXT) | \ 259237522Sadrian 0) 260237522Sadrian#else 261237522Sadrian#define ATH_RX_RADIOTAP_PRESENT ATH_RX_RADIOTAP_PRESENT_BASE 262237522Sadrian#endif /* ATH_ENABLE_RADIOTAP_PRESENT */ 263237522Sadrian 264237522Sadrian#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 265237522Sadrian/* 266237522Sadrian * This is higher than the vendor bitmap used inside 267237522Sadrian * the Atheros reference codebase. 268237522Sadrian */ 269237522Sadrian 270237522Sadrian/* Bit 8 */ 271237522Sadrian#define ATH_RADIOTAP_VENDOR_HEADER 8 272237522Sadrian 273237522Sadrian/* 274237522Sadrian * Using four chains makes all the fields in the 275237522Sadrian * per-chain info header be 4-byte aligned. 276237522Sadrian */ 277237522Sadrian#define ATH_RADIOTAP_MAX_CHAINS 4 278237522Sadrian 279237522Sadrian/* 280248143Sadrian * AR9380 and later chips are 3x3, which requires 281248143Sadrian * 5 EVM DWORDs in HT40 mode. 282248143Sadrian */ 283248143Sadrian#define ATH_RADIOTAP_MAX_EVM 5 284248143Sadrian 285248143Sadrian/* 286237522Sadrian * The vendor radiotap header data needs to be: 287237522Sadrian * 288237522Sadrian * + Aligned to a 4 byte address 289237522Sadrian * + .. so all internal fields are 4 bytes aligned; 290237522Sadrian * + .. and no 64 bit fields are allowed. 291237522Sadrian * 292237522Sadrian * So padding is required to ensure this is the case. 293237522Sadrian * 294237522Sadrian * Note that because of the lack of alignment with the 295237522Sadrian * vendor header (6 bytes), the first field must be 296237522Sadrian * two bytes so it can be accessed by alignment-strict 297237522Sadrian * platform (eg MIPS.) 298237522Sadrian */ 299237522Sadrianstruct ath_radiotap_vendor_hdr { /* 30 bytes */ 300237522Sadrian uint8_t vh_version; /* 1 */ 301237522Sadrian uint8_t vh_rx_chainmask; /* 1 */ 302237522Sadrian 303237522Sadrian /* At this point it should be 4 byte aligned */ 304248143Sadrian uint32_t evm[ATH_RADIOTAP_MAX_EVM]; /* 5 * 4 = 20 */ 305237522Sadrian 306237522Sadrian uint8_t rssi_ctl[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */ 307237522Sadrian uint8_t rssi_ext[ATH_RADIOTAP_MAX_CHAINS]; /* 4 */ 308237522Sadrian 309237522Sadrian uint8_t vh_phyerr_code; /* Phy error code, or 0xff */ 310237522Sadrian uint8_t vh_rs_status; /* RX status */ 311237522Sadrian uint8_t vh_rssi; /* Raw RSSI */ 312248146Sadrian uint8_t vh_flags; /* General flags */ 313248146Sadrian#define ATH_VENDOR_PKT_RX 0x01 314248146Sadrian#define ATH_VENDOR_PKT_TX 0x02 315248146Sadrian#define ATH_VENDOR_PKT_RXPHYERR 0x04 316248146Sadrian#define ATH_VENDOR_PKT_ISAGGR 0x08 317248146Sadrian#define ATH_VENDOR_PKT_MOREAGGR 0x10 318248146Sadrian 319248146Sadrian uint8_t vh_rx_hwrate; /* hardware RX ratecode */ 320248146Sadrian uint8_t vh_rs_flags; /* RX HAL flags */ 321248146Sadrian uint8_t vh_pad[2]; /* pad to DWORD boundary */ 322237522Sadrian} __packed; 323237522Sadrian#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 324237522Sadrian 325119783Ssamstruct ath_rx_radiotap_header { 326119783Ssam struct ieee80211_radiotap_header wr_ihdr; 327237522Sadrian 328237522Sadrian#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 329237522Sadrian /* Vendor extension header bitmap */ 330237522Sadrian uint32_t wr_ext_bitmap; /* 4 */ 331237522Sadrian 332237522Sadrian /* 333237522Sadrian * This padding is needed because: 334237522Sadrian * + the radiotap header is 8 bytes; 335237522Sadrian * + the extension bitmap is 4 bytes; 336237522Sadrian * + the tsf is 8 bytes, so it must start on an 8 byte 337237522Sadrian * boundary. 338237522Sadrian */ 339237522Sadrian uint32_t wr_pad1; 340237522Sadrian#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 341237522Sadrian 342237522Sadrian /* Normal radiotap fields */ 343154140Ssam u_int64_t wr_tsf; 344154140Ssam u_int8_t wr_flags; 345119783Ssam u_int8_t wr_rate; 346170530Ssam int8_t wr_antsignal; 347170530Ssam int8_t wr_antnoise; 348170530Ssam u_int8_t wr_antenna; 349170530Ssam u_int8_t wr_pad[3]; 350170530Ssam u_int32_t wr_chan_flags; 351119783Ssam u_int16_t wr_chan_freq; 352170530Ssam u_int8_t wr_chan_ieee; 353170530Ssam int8_t wr_chan_maxpow; 354237522Sadrian 355237522Sadrian#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 356237522Sadrian /* 357237522Sadrian * Vendor header section, as required by the 358237522Sadrian * presence of the vendor extension bit and bitmap 359237522Sadrian * entry. 360237522Sadrian * 361237522Sadrian * XXX This must be aligned to a 4 byte address? 362237522Sadrian * XXX or 8 byte address? 363237522Sadrian */ 364237522Sadrian struct ieee80211_radiotap_vendor_header wr_vh; /* 6 bytes */ 365237522Sadrian 366237522Sadrian /* 367237522Sadrian * Because of the lack of alignment enforced by the above 368237522Sadrian * header, this vendor section won't be aligned in any 369237522Sadrian * useful way. So, this will include a two-byte version 370237522Sadrian * value which will force the structure to be 4-byte aligned. 371237522Sadrian */ 372237522Sadrian struct ath_radiotap_vendor_hdr wr_v; 373237522Sadrian#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 374170530Ssam} __packed; 375119783Ssam 376119783Ssam#define ATH_TX_RADIOTAP_PRESENT ( \ 377154140Ssam (1 << IEEE80211_RADIOTAP_TSFT) | \ 378119783Ssam (1 << IEEE80211_RADIOTAP_FLAGS) | \ 379119783Ssam (1 << IEEE80211_RADIOTAP_RATE) | \ 380123928Ssam (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ 381123928Ssam (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 382170530Ssam (1 << IEEE80211_RADIOTAP_XCHANNEL) | \ 383119783Ssam 0) 384119783Ssam 385119783Ssamstruct ath_tx_radiotap_header { 386119783Ssam struct ieee80211_radiotap_header wt_ihdr; 387154140Ssam u_int64_t wt_tsf; 388154140Ssam u_int8_t wt_flags; 389119783Ssam u_int8_t wt_rate; 390123928Ssam u_int8_t wt_txpower; 391123928Ssam u_int8_t wt_antenna; 392170530Ssam u_int32_t wt_chan_flags; 393170530Ssam u_int16_t wt_chan_freq; 394170530Ssam u_int8_t wt_chan_ieee; 395170530Ssam int8_t wt_chan_maxpow; 396170530Ssam} __packed; 397119783Ssam 398224245Sadrian/* 399224245Sadrian * DFS ioctl commands 400224245Sadrian */ 401224245Sadrian 402224245Sadrian#define DFS_SET_THRESH 2 403224245Sadrian#define DFS_GET_THRESH 3 404224245Sadrian#define DFS_RADARDETECTS 6 405224245Sadrian 406224245Sadrian/* 407224245Sadrian * DFS ioctl parameter types 408224245Sadrian */ 409224245Sadrian#define DFS_PARAM_FIRPWR 1 410224245Sadrian#define DFS_PARAM_RRSSI 2 411224245Sadrian#define DFS_PARAM_HEIGHT 3 412224245Sadrian#define DFS_PARAM_PRSSI 4 413224245Sadrian#define DFS_PARAM_INBAND 5 414224245Sadrian#define DFS_PARAM_NOL 6 /* XXX not used in FreeBSD */ 415224245Sadrian#define DFS_PARAM_RELSTEP_EN 7 416224245Sadrian#define DFS_PARAM_RELSTEP 8 417224245Sadrian#define DFS_PARAM_RELPWR_EN 9 418224245Sadrian#define DFS_PARAM_RELPWR 10 419224245Sadrian#define DFS_PARAM_MAXLEN 11 420224245Sadrian#define DFS_PARAM_USEFIR128 12 421224245Sadrian#define DFS_PARAM_BLOCKRADAR 13 422224245Sadrian#define DFS_PARAM_MAXRSSI_EN 14 423224245Sadrian 424224245Sadrian/* FreeBSD-specific start at 32 */ 425224245Sadrian#define DFS_PARAM_ENABLE 32 426224245Sadrian#define DFS_PARAM_EN_EXTCH 33 427224245Sadrian 428244951Sadrian/* 429244951Sadrian * Spectral ioctl parameter types 430244951Sadrian */ 431244951Sadrian#define SPECTRAL_PARAM_FFT_PERIOD 1 432244951Sadrian#define SPECTRAL_PARAM_SS_PERIOD 2 433244951Sadrian#define SPECTRAL_PARAM_SS_COUNT 3 434244951Sadrian#define SPECTRAL_PARAM_SS_SHORT_RPT 4 435244951Sadrian#define SPECTRAL_PARAM_ENABLED 5 436244951Sadrian#define SPECTRAL_PARAM_ACTIVE 6 437244951Sadrian 438244951Sadrian/* 439244951Sadrian * Spectral control parameters 440244951Sadrian */ 441244951Sadrian#define SIOCGATHSPECTRAL _IOWR('i', 151, struct ath_diag) 442244951Sadrian 443244951Sadrian#define SPECTRAL_CONTROL_ENABLE 2 444244951Sadrian#define SPECTRAL_CONTROL_DISABLE 3 445244951Sadrian#define SPECTRAL_CONTROL_START 4 446244951Sadrian#define SPECTRAL_CONTROL_STOP 5 447244951Sadrian#define SPECTRAL_CONTROL_GET_PARAMS 6 448244951Sadrian#define SPECTRAL_CONTROL_SET_PARAMS 7 449245185Sadrian#define SPECTRAL_CONTROL_ENABLE_AT_RESET 8 450245185Sadrian#define SPECTRAL_CONTROL_DISABLE_AT_RESET 9 451244951Sadrian 452116743Ssam#endif /* _DEV_ATH_ATHIOCTL_H */ 453