ar5212_attach.c revision 222644
1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187831Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 222644 2011-06-03 07:27:53Z adrian $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25185377Ssam#include "ar5212/ar5212.h" 26185377Ssam#include "ar5212/ar5212reg.h" 27185377Ssam#include "ar5212/ar5212phy.h" 28185377Ssam 29185377Ssam#define AH_5212_COMMON 30185377Ssam#include "ar5212/ar5212.ini" 31185377Ssam 32188979Ssamstatic void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 33188979Ssamstatic void ar5212DisablePCIE(struct ath_hal *ah); 34188979Ssam 35185377Ssamstatic const struct ath_hal_private ar5212hal = {{ 36185377Ssam .ah_magic = AR5212_MAGIC, 37185377Ssam 38185377Ssam .ah_getRateTable = ar5212GetRateTable, 39185377Ssam .ah_detach = ar5212Detach, 40185377Ssam 41185377Ssam /* Reset Functions */ 42185377Ssam .ah_reset = ar5212Reset, 43185377Ssam .ah_phyDisable = ar5212PhyDisable, 44185377Ssam .ah_disable = ar5212Disable, 45188979Ssam .ah_configPCIE = ar5212ConfigPCIE, 46188979Ssam .ah_disablePCIE = ar5212DisablePCIE, 47185377Ssam .ah_setPCUConfig = ar5212SetPCUConfig, 48185377Ssam .ah_perCalibration = ar5212PerCalibration, 49185380Ssam .ah_perCalibrationN = ar5212PerCalibrationN, 50185380Ssam .ah_resetCalValid = ar5212ResetCalValid, 51185377Ssam .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 52185377Ssam .ah_getChanNoise = ath_hal_getChanNoise, 53185377Ssam 54185377Ssam /* Transmit functions */ 55185377Ssam .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 56185377Ssam .ah_setupTxQueue = ar5212SetupTxQueue, 57185377Ssam .ah_setTxQueueProps = ar5212SetTxQueueProps, 58185377Ssam .ah_getTxQueueProps = ar5212GetTxQueueProps, 59185377Ssam .ah_releaseTxQueue = ar5212ReleaseTxQueue, 60185377Ssam .ah_resetTxQueue = ar5212ResetTxQueue, 61185377Ssam .ah_getTxDP = ar5212GetTxDP, 62185377Ssam .ah_setTxDP = ar5212SetTxDP, 63185377Ssam .ah_numTxPending = ar5212NumTxPending, 64185377Ssam .ah_startTxDma = ar5212StartTxDma, 65185377Ssam .ah_stopTxDma = ar5212StopTxDma, 66185377Ssam .ah_setupTxDesc = ar5212SetupTxDesc, 67185377Ssam .ah_setupXTxDesc = ar5212SetupXTxDesc, 68185377Ssam .ah_fillTxDesc = ar5212FillTxDesc, 69185377Ssam .ah_procTxDesc = ar5212ProcTxDesc, 70185377Ssam .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 71185377Ssam .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 72217621Sadrian .ah_getTxCompletionRates = ar5212GetTxCompletionRates, 73185377Ssam 74185377Ssam /* RX Functions */ 75185377Ssam .ah_getRxDP = ar5212GetRxDP, 76185377Ssam .ah_setRxDP = ar5212SetRxDP, 77185377Ssam .ah_enableReceive = ar5212EnableReceive, 78185377Ssam .ah_stopDmaReceive = ar5212StopDmaReceive, 79185377Ssam .ah_startPcuReceive = ar5212StartPcuReceive, 80185377Ssam .ah_stopPcuReceive = ar5212StopPcuReceive, 81185377Ssam .ah_setMulticastFilter = ar5212SetMulticastFilter, 82185377Ssam .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 83185377Ssam .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 84185377Ssam .ah_getRxFilter = ar5212GetRxFilter, 85185377Ssam .ah_setRxFilter = ar5212SetRxFilter, 86185377Ssam .ah_setupRxDesc = ar5212SetupRxDesc, 87185377Ssam .ah_procRxDesc = ar5212ProcRxDesc, 88217684Sadrian .ah_rxMonitor = ar5212RxMonitor, 89217684Sadrian .ah_aniPoll = ar5212AniPoll, 90185377Ssam .ah_procMibEvent = ar5212ProcessMibIntr, 91185377Ssam 92185377Ssam /* Misc Functions */ 93185377Ssam .ah_getCapability = ar5212GetCapability, 94185377Ssam .ah_setCapability = ar5212SetCapability, 95185377Ssam .ah_getDiagState = ar5212GetDiagState, 96185377Ssam .ah_getMacAddress = ar5212GetMacAddress, 97185377Ssam .ah_setMacAddress = ar5212SetMacAddress, 98185377Ssam .ah_getBssIdMask = ar5212GetBssIdMask, 99185377Ssam .ah_setBssIdMask = ar5212SetBssIdMask, 100185380Ssam .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 101185377Ssam .ah_setLedState = ar5212SetLedState, 102185377Ssam .ah_writeAssocid = ar5212WriteAssocid, 103185377Ssam .ah_gpioCfgInput = ar5212GpioCfgInput, 104185377Ssam .ah_gpioCfgOutput = ar5212GpioCfgOutput, 105185377Ssam .ah_gpioGet = ar5212GpioGet, 106185377Ssam .ah_gpioSet = ar5212GpioSet, 107185377Ssam .ah_gpioSetIntr = ar5212GpioSetIntr, 108185377Ssam .ah_getTsf32 = ar5212GetTsf32, 109185377Ssam .ah_getTsf64 = ar5212GetTsf64, 110185377Ssam .ah_resetTsf = ar5212ResetTsf, 111185377Ssam .ah_detectCardPresent = ar5212DetectCardPresent, 112185377Ssam .ah_updateMibCounters = ar5212UpdateMibCounters, 113185377Ssam .ah_getRfGain = ar5212GetRfgain, 114185377Ssam .ah_getDefAntenna = ar5212GetDefAntenna, 115185377Ssam .ah_setDefAntenna = ar5212SetDefAntenna, 116185377Ssam .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 117185377Ssam .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 118185377Ssam .ah_setSifsTime = ar5212SetSifsTime, 119185377Ssam .ah_getSifsTime = ar5212GetSifsTime, 120185377Ssam .ah_setSlotTime = ar5212SetSlotTime, 121185377Ssam .ah_getSlotTime = ar5212GetSlotTime, 122185377Ssam .ah_setAckTimeout = ar5212SetAckTimeout, 123185377Ssam .ah_getAckTimeout = ar5212GetAckTimeout, 124185377Ssam .ah_setAckCTSRate = ar5212SetAckCTSRate, 125185377Ssam .ah_getAckCTSRate = ar5212GetAckCTSRate, 126185377Ssam .ah_setCTSTimeout = ar5212SetCTSTimeout, 127185377Ssam .ah_getCTSTimeout = ar5212GetCTSTimeout, 128185377Ssam .ah_setDecompMask = ar5212SetDecompMask, 129185377Ssam .ah_setCoverageClass = ar5212SetCoverageClass, 130222644Sadrian .ah_setQuiet = ar5212SetQuiet, 131185377Ssam 132222584Sadrian /* DFS Functions */ 133222584Sadrian .ah_enableDfs = ar5212EnableDfs, 134222584Sadrian .ah_getDfsThresh = ar5212GetDfsThresh, 135222584Sadrian 136185377Ssam /* Key Cache Functions */ 137185377Ssam .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 138185377Ssam .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 139185377Ssam .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 140185377Ssam .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 141185377Ssam .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 142185377Ssam 143185377Ssam /* Power Management Functions */ 144185377Ssam .ah_setPowerMode = ar5212SetPowerMode, 145185377Ssam .ah_getPowerMode = ar5212GetPowerMode, 146185377Ssam 147185377Ssam /* Beacon Functions */ 148185377Ssam .ah_setBeaconTimers = ar5212SetBeaconTimers, 149185377Ssam .ah_beaconInit = ar5212BeaconInit, 150185377Ssam .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 151185377Ssam .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 152185377Ssam 153185377Ssam /* Interrupt Functions */ 154185377Ssam .ah_isInterruptPending = ar5212IsInterruptPending, 155185377Ssam .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 156185377Ssam .ah_getInterrupts = ar5212GetInterrupts, 157185377Ssam .ah_setInterrupts = ar5212SetInterrupts }, 158185377Ssam 159185377Ssam .ah_getChannelEdges = ar5212GetChannelEdges, 160185377Ssam .ah_getWirelessModes = ar5212GetWirelessModes, 161185377Ssam .ah_eepromRead = ar5212EepromRead, 162185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 163185377Ssam .ah_eepromWrite = ar5212EepromWrite, 164185377Ssam#endif 165185377Ssam .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 166185377Ssam}; 167185377Ssam 168185377Ssamuint32_t 169185377Ssamar5212GetRadioRev(struct ath_hal *ah) 170185377Ssam{ 171185377Ssam uint32_t val; 172185377Ssam int i; 173185377Ssam 174185377Ssam /* Read Radio Chip Rev Extract */ 175185377Ssam OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 176185377Ssam for (i = 0; i < 8; i++) 177185377Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 178185377Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 179185377Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 180185377Ssam return ath_hal_reverseBits(val, 8); 181185377Ssam} 182185377Ssam 183185377Ssamstatic void 184185377Ssamar5212AniSetup(struct ath_hal *ah) 185185377Ssam{ 186185377Ssam static const struct ar5212AniParams aniparams = { 187185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 188185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 189185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 190185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 191185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 192185377Ssam .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 193185377Ssam .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 194185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 195185377Ssam .firstep = { 0, 4, 8 }, 196185377Ssam .ofdmTrigHigh = 500, 197185377Ssam .ofdmTrigLow = 200, 198185377Ssam .cckTrigHigh = 200, 199185377Ssam .cckTrigLow = 100, 200185377Ssam .rssiThrHigh = 40, 201185377Ssam .rssiThrLow = 7, 202185377Ssam .period = 100, 203185377Ssam }; 204185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 205185377Ssam struct ar5212AniParams tmp; 206185377Ssam OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 207185377Ssam tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 208185377Ssam ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 209185377Ssam } else 210185377Ssam ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 211222265Sadrian 212222265Sadrian /* Set overridable ANI methods */ 213222265Sadrian AH5212(ah)->ah_aniControl = ar5212AniControl; 214185377Ssam} 215185377Ssam 216185377Ssam/* 217185377Ssam * Attach for an AR5212 part. 218185377Ssam */ 219185377Ssamvoid 220185377Ssamar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 221185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 222185377Ssam{ 223185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 224185377Ssam static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 225185377Ssam { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 226185377Ssam struct ath_hal *ah; 227185377Ssam 228185377Ssam ah = &ahp->ah_priv.h; 229185377Ssam /* set initial values */ 230185377Ssam OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 231185377Ssam ah->ah_sc = sc; 232185377Ssam ah->ah_st = st; 233185377Ssam ah->ah_sh = sh; 234185377Ssam 235185377Ssam ah->ah_devid = devid; /* NB: for alq */ 236185377Ssam AH_PRIVATE(ah)->ah_devid = devid; 237185377Ssam AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 238185377Ssam 239185377Ssam AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 240185377Ssam AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 241185377Ssam 242185380Ssam ahp->ah_antControl = HAL_ANT_VARIABLE; 243185380Ssam ahp->ah_diversity = AH_TRUE; 244185377Ssam ahp->ah_bIQCalibration = AH_FALSE; 245185377Ssam /* 246185377Ssam * Enable MIC handling. 247185377Ssam */ 248185377Ssam ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 249185377Ssam ahp->ah_rssiThr = INIT_RSSI_THR; 250185377Ssam ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 251185380Ssam ahp->ah_phyPowerOn = AH_FALSE; 252185377Ssam ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 253185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CTS) 254185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 255185377Ssam ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 256185377Ssam ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 257185377Ssam ahp->ah_slottime = (u_int) -1; 258185377Ssam ahp->ah_acktimeout = (u_int) -1; 259185377Ssam ahp->ah_ctstimeout = (u_int) -1; 260185377Ssam ahp->ah_sifstime = (u_int) -1; 261204579Srpaulo ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD, 262204579Srpaulo ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD, 263204579Srpaulo 264185377Ssam OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 265185377Ssam#undef N 266185377Ssam} 267185377Ssam 268185377Ssam/* 269185377Ssam * Validate MAC version and revision. 270185377Ssam */ 271185377Ssamstatic HAL_BOOL 272185377Ssamar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 273185377Ssam{ 274185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 275185377Ssam static const struct { 276185377Ssam uint8_t version; 277185377Ssam uint8_t revMin, revMax; 278185377Ssam } macs[] = { 279185377Ssam { AR_SREV_VERSION_VENICE, 280185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 281185377Ssam { AR_SREV_VERSION_GRIFFIN, 282185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 283185377Ssam { AR_SREV_5413, 284185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 285185377Ssam { AR_SREV_5424, 286185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 287185377Ssam { AR_SREV_2425, 288185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 289185377Ssam { AR_SREV_2417, 290185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 291185377Ssam }; 292185377Ssam int i; 293185377Ssam 294185377Ssam for (i = 0; i < N(macs); i++) 295185377Ssam if (macs[i].version == macVersion && 296185377Ssam macs[i].revMin <= macRev && macRev <= macs[i].revMax) 297185377Ssam return AH_TRUE; 298185377Ssam return AH_FALSE; 299185377Ssam#undef N 300185377Ssam} 301185377Ssam 302185377Ssam/* 303185377Ssam * Attach for an AR5212 part. 304185377Ssam */ 305185406Ssamstatic struct ath_hal * 306185377Ssamar5212Attach(uint16_t devid, HAL_SOFTC sc, 307217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 308217624Sadrian HAL_STATUS *status) 309185377Ssam{ 310185377Ssam#define AH_EEPROM_PROTECT(ah) \ 311188979Ssam (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 312185377Ssam struct ath_hal_5212 *ahp; 313185377Ssam struct ath_hal *ah; 314185406Ssam struct ath_hal_rf *rf; 315185377Ssam uint32_t val; 316185377Ssam uint16_t eeval; 317185377Ssam HAL_STATUS ecode; 318185377Ssam 319185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 320185377Ssam __func__, sc, (void*) st, (void*) sh); 321185377Ssam 322185377Ssam /* NB: memory is returned zero'd */ 323185377Ssam ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 324185377Ssam if (ahp == AH_NULL) { 325185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 326185377Ssam "%s: cannot allocate memory for state block\n", __func__); 327185377Ssam *status = HAL_ENOMEM; 328185377Ssam return AH_NULL; 329185377Ssam } 330185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 331185377Ssam ah = &ahp->ah_priv.h; 332185377Ssam 333185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 334185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 335185377Ssam __func__); 336185377Ssam ecode = HAL_EIO; 337185377Ssam goto bad; 338185377Ssam } 339185377Ssam /* Read Revisions from Chips before taking out of reset */ 340185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 341185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 342185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 343188979Ssam AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 344185377Ssam 345185377Ssam if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 346185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 347185377Ssam "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 348185377Ssam __func__, AH_PRIVATE(ah)->ah_macVersion, 349185377Ssam AH_PRIVATE(ah)->ah_macRev); 350185377Ssam ecode = HAL_ENOTSUPP; 351185377Ssam goto bad; 352185377Ssam } 353185377Ssam 354185377Ssam /* setup common ini data; rf backends handle remainder */ 355185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 356185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 357185377Ssam 358185377Ssam if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 359185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 360185377Ssam ecode = HAL_EIO; 361185377Ssam goto bad; 362185377Ssam } 363185377Ssam 364185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 365185377Ssam 366188979Ssam if (AH_PRIVATE(ah)->ah_ispcie) { 367185377Ssam /* XXX: build flag to disable this? */ 368188979Ssam ath_hal_configPCIE(ah, AH_FALSE); 369185377Ssam } 370185377Ssam 371185377Ssam if (!ar5212ChipTest(ah)) { 372185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 373185377Ssam __func__); 374185377Ssam ecode = HAL_ESELFTEST; 375185377Ssam goto bad; 376185377Ssam } 377185377Ssam 378185377Ssam /* Enable PCI core retry fix in software for Hainan and up */ 379185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 380185377Ssam OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 381185377Ssam 382185377Ssam /* 383185377Ssam * Set correct Baseband to analog shift 384185377Ssam * setting to access analog chips. 385185377Ssam */ 386185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 387185377Ssam 388185377Ssam /* Read Radio Chip Rev Extract */ 389185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 390185406Ssam 391185406Ssam rf = ath_hal_rfprobe(ah, &ecode); 392185406Ssam if (rf == AH_NULL) 393185406Ssam goto bad; 394185406Ssam 395185377Ssam /* NB: silently accept anything in release code per Atheros */ 396185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 397185377Ssam case AR_RAD5111_SREV_MAJOR: 398185377Ssam case AR_RAD5112_SREV_MAJOR: 399185377Ssam case AR_RAD2112_SREV_MAJOR: 400185377Ssam case AR_RAD2111_SREV_MAJOR: 401185377Ssam case AR_RAD2413_SREV_MAJOR: 402185377Ssam case AR_RAD5413_SREV_MAJOR: 403185377Ssam case AR_RAD5424_SREV_MAJOR: 404185377Ssam break; 405185377Ssam default: 406185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 407185377Ssam /* 408185377Ssam * When RF_Silent is used, the 409185377Ssam * analog chip is reset. So when the system boots 410185377Ssam * up with the radio switch off we cannot determine 411185377Ssam * the RF chip rev. To workaround this check the 412185377Ssam * mac+phy revs and if Hainan, set the radio rev 413185377Ssam * to Derby. 414185377Ssam */ 415185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 416185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 417185377Ssam AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 418185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 419185377Ssam break; 420185377Ssam } 421185377Ssam if (IS_2413(ah)) { /* Griffin */ 422185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 423185380Ssam AR_RAD2413_SREV_MAJOR | 0x1; 424185377Ssam break; 425185377Ssam } 426185377Ssam if (IS_5413(ah)) { /* Eagle */ 427185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 428185380Ssam AR_RAD5413_SREV_MAJOR | 0x2; 429185377Ssam break; 430185377Ssam } 431185377Ssam if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 432185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 433185380Ssam AR_RAD5424_SREV_MAJOR | 0x2; 434185377Ssam break; 435185377Ssam } 436185377Ssam } 437185377Ssam#ifdef AH_DEBUG 438185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 439185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 440185377Ssam "this driver\n", 441185377Ssam __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 442185377Ssam ecode = HAL_ENOTSUPP; 443185377Ssam goto bad; 444185377Ssam#endif 445185377Ssam } 446185380Ssam if (IS_RAD5112_REV1(ah)) { 447185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 448185377Ssam "%s: 5112 Rev 1 is not supported by this " 449185377Ssam "driver (analog5GhzRev 0x%x)\n", __func__, 450185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 451185377Ssam ecode = HAL_ENOTSUPP; 452185377Ssam goto bad; 453185377Ssam } 454185377Ssam 455185377Ssam val = OS_REG_READ(ah, AR_PCICFG); 456185377Ssam val = MS(val, AR_PCICFG_EEPROM_SIZE); 457185377Ssam if (val == 0) { 458188979Ssam if (!AH_PRIVATE(ah)->ah_ispcie) { 459185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 460185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 461185377Ssam __func__, val, val); 462185377Ssam ecode = HAL_EESIZE; 463185377Ssam goto bad; 464185377Ssam } 465185377Ssam /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 466185377Ssam } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 467185377Ssam if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 468185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 469185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 470185377Ssam __func__, val, val); 471185377Ssam ecode = HAL_EESIZE; 472185377Ssam goto bad; 473185377Ssam } 474185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 475185377Ssam "%s: EEPROM size = %d. Must be %d (16k).\n", 476185377Ssam __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 477185377Ssam ecode = HAL_EESIZE; 478185377Ssam goto bad; 479185377Ssam } 480185377Ssam ecode = ath_hal_legacyEepromAttach(ah); 481185377Ssam if (ecode != HAL_OK) { 482185377Ssam goto bad; 483185377Ssam } 484185377Ssam ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 485185377Ssam 486185377Ssam /* 487185377Ssam * If Bmode and AR5212, verify 2.4 analog exists 488185377Ssam */ 489185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 490185377Ssam (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 491185377Ssam /* 492185377Ssam * Set correct Baseband to analog shift 493185377Ssam * setting to access analog chips. 494185377Ssam */ 495185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 496185377Ssam OS_DELAY(2000); 497185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 498185377Ssam 499185377Ssam /* Set baseband for 5GHz chip */ 500185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 501185377Ssam OS_DELAY(2000); 502185377Ssam if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 503185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 504185377Ssam "%s: 2G Radio Chip Rev 0x%02X is not " 505185377Ssam "supported by this driver\n", __func__, 506185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev); 507185377Ssam ecode = HAL_ENOTSUPP; 508185377Ssam goto bad; 509185377Ssam } 510185377Ssam } 511185377Ssam 512185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 513185377Ssam if (ecode != HAL_OK) { 514185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 515185377Ssam "%s: cannot read regulatory domain from EEPROM\n", 516185377Ssam __func__); 517185377Ssam goto bad; 518185377Ssam } 519185377Ssam AH_PRIVATE(ah)->ah_currentRD = eeval; 520185377Ssam /* XXX record serial number */ 521185377Ssam 522185377Ssam /* 523185377Ssam * Got everything we need now to setup the capabilities. 524185377Ssam */ 525185377Ssam if (!ar5212FillCapabilityInfo(ah)) { 526185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 527185377Ssam "%s: failed ar5212FillCapabilityInfo\n", __func__); 528185377Ssam ecode = HAL_EEREAD; 529185377Ssam goto bad; 530185377Ssam } 531185377Ssam 532185406Ssam if (!rf->attach(ah, &ecode)) { 533185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 534185377Ssam __func__, ecode); 535185377Ssam goto bad; 536185377Ssam } 537185377Ssam /* 538185377Ssam * Set noise floor adjust method; we arrange a 539185377Ssam * direct call instead of thunking. 540185377Ssam */ 541185377Ssam AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 542185377Ssam 543185377Ssam /* Initialize gain ladder thermal calibration structure */ 544185377Ssam ar5212InitializeGainValues(ah); 545185377Ssam 546185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 547185377Ssam if (ecode != HAL_OK) { 548185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 549185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 550185377Ssam goto bad; 551185377Ssam } 552185377Ssam 553185377Ssam ar5212AniSetup(ah); 554185377Ssam /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 555185377Ssam ar5212InitNfCalHistBuffer(ah); 556185377Ssam 557185377Ssam /* XXX EAR stuff goes here */ 558185377Ssam 559185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 560185377Ssam 561185377Ssam return ah; 562185377Ssam 563185377Ssambad: 564185377Ssam if (ahp) 565185377Ssam ar5212Detach((struct ath_hal *) ahp); 566185377Ssam if (status) 567185377Ssam *status = ecode; 568185377Ssam return AH_NULL; 569185377Ssam#undef AH_EEPROM_PROTECT 570185377Ssam} 571185377Ssam 572185377Ssamvoid 573185377Ssamar5212Detach(struct ath_hal *ah) 574185377Ssam{ 575185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 576185377Ssam 577185377Ssam HALASSERT(ah != AH_NULL); 578185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 579185377Ssam 580185377Ssam ar5212AniDetach(ah); 581185377Ssam ar5212RfDetach(ah); 582185377Ssam ar5212Disable(ah); 583185377Ssam ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 584185377Ssam 585185377Ssam ath_hal_eepromDetach(ah); 586185377Ssam ath_hal_free(ah); 587185377Ssam} 588185377Ssam 589185377SsamHAL_BOOL 590185377Ssamar5212ChipTest(struct ath_hal *ah) 591185377Ssam{ 592185377Ssam uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 593185377Ssam uint32_t regHold[2]; 594185377Ssam uint32_t patternData[4] = 595185377Ssam { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 596185377Ssam int i, j; 597185377Ssam 598185377Ssam /* Test PHY & MAC registers */ 599185377Ssam for (i = 0; i < 2; i++) { 600185377Ssam uint32_t addr = regAddr[i]; 601185377Ssam uint32_t wrData, rdData; 602185377Ssam 603185377Ssam regHold[i] = OS_REG_READ(ah, addr); 604185377Ssam for (j = 0; j < 0x100; j++) { 605185377Ssam wrData = (j << 16) | j; 606185377Ssam OS_REG_WRITE(ah, addr, wrData); 607185377Ssam rdData = OS_REG_READ(ah, addr); 608185377Ssam if (rdData != wrData) { 609185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 610185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 611185377Ssam __func__, addr, wrData, rdData); 612185377Ssam return AH_FALSE; 613185377Ssam } 614185377Ssam } 615185377Ssam for (j = 0; j < 4; j++) { 616185377Ssam wrData = patternData[j]; 617185377Ssam OS_REG_WRITE(ah, addr, wrData); 618185377Ssam rdData = OS_REG_READ(ah, addr); 619185377Ssam if (wrData != rdData) { 620185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 621185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 622185377Ssam __func__, addr, wrData, rdData); 623185377Ssam return AH_FALSE; 624185377Ssam } 625185377Ssam } 626185377Ssam OS_REG_WRITE(ah, regAddr[i], regHold[i]); 627185377Ssam } 628185377Ssam OS_DELAY(100); 629185377Ssam return AH_TRUE; 630185377Ssam} 631185377Ssam 632185377Ssam/* 633185377Ssam * Store the channel edges for the requested operational mode 634185377Ssam */ 635185377SsamHAL_BOOL 636185377Ssamar5212GetChannelEdges(struct ath_hal *ah, 637185377Ssam uint16_t flags, uint16_t *low, uint16_t *high) 638185377Ssam{ 639187831Ssam if (flags & IEEE80211_CHAN_5GHZ) { 640185377Ssam *low = 4915; 641185377Ssam *high = 6100; 642185377Ssam return AH_TRUE; 643185377Ssam } 644187831Ssam if ((flags & IEEE80211_CHAN_2GHZ) && 645185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 646185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 647185377Ssam *low = 2312; 648185377Ssam *high = 2732; 649185377Ssam return AH_TRUE; 650185377Ssam } 651185377Ssam return AH_FALSE; 652185377Ssam} 653185377Ssam 654185377Ssam/* 655188979Ssam * Disable PLL when in L0s as well as receiver clock when in L1. 656188979Ssam * This power saving option must be enabled through the Serdes. 657188979Ssam * 658188979Ssam * Programming the Serdes must go through the same 288 bit serial shift 659188979Ssam * register as the other analog registers. Hence the 9 writes. 660188979Ssam * 661188979Ssam * XXX Clean up the magic numbers. 662188979Ssam */ 663188979Ssamstatic void 664188979Ssamar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 665188979Ssam{ 666188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 667188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 668188979Ssam 669188979Ssam /* RX shut off when elecidle is asserted */ 670188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 671188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 672188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 673188979Ssam 674188979Ssam /* Shut off PLL and CLKREQ active in L1 */ 675188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 676188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 677188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 678188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 679188979Ssam 680188979Ssam /* Load the new settings */ 681188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 682188979Ssam} 683188979Ssam 684188979Ssamstatic void 685188979Ssamar5212DisablePCIE(struct ath_hal *ah) 686188979Ssam{ 687188979Ssam /* NB: fill in for 9100 */ 688188979Ssam} 689188979Ssam 690188979Ssam/* 691185377Ssam * Fill all software cached or static hardware state information. 692185377Ssam * Return failure if capabilities are to come from EEPROM and 693185377Ssam * cannot be read. 694185377Ssam */ 695185377SsamHAL_BOOL 696185377Ssamar5212FillCapabilityInfo(struct ath_hal *ah) 697185377Ssam{ 698185377Ssam#define AR_KEYTABLE_SIZE 128 699185377Ssam#define IS_GRIFFIN_LITE(ah) \ 700185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 701185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 702185377Ssam#define IS_COBRA(ah) \ 703185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 704185377Ssam#define IS_2112(ah) \ 705185377Ssam ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 706185377Ssam 707185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 708185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 709185377Ssam uint16_t capField, val; 710185377Ssam 711185377Ssam /* Read the capability EEPROM location */ 712185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 713185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 714185377Ssam "%s: unable to read caps from eeprom\n", __func__); 715185377Ssam return AH_FALSE; 716185377Ssam } 717185377Ssam if (IS_2112(ah)) 718185377Ssam ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 719185377Ssam if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 720185377Ssam /* 721185377Ssam * For griffin-lite cards with unprogrammed capabilities. 722185377Ssam */ 723185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 724185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 725185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 726185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 727185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 728185377Ssam "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 729185377Ssam __func__, capField); 730185377Ssam } 731185377Ssam 732185377Ssam /* Modify reg domain on newer cards that need to work with older sw */ 733185377Ssam if (ahpriv->ah_opmode != HAL_M_HOSTAP && 734185377Ssam ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 735185377Ssam if (ahpriv->ah_currentRD == 0x64 || 736185377Ssam ahpriv->ah_currentRD == 0x65) 737185377Ssam ahpriv->ah_currentRD += 5; 738185377Ssam else if (ahpriv->ah_currentRD == 0x41) 739185377Ssam ahpriv->ah_currentRD = 0x43; 740185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 741185377Ssam __func__, ahpriv->ah_currentRD); 742185377Ssam } 743185377Ssam 744185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 745185377Ssam AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 746185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 747185377Ssam "%s: enable Bmode and disable turbo for Swan/Nala\n", 748185377Ssam __func__); 749185377Ssam ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 750185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 751185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 752185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 753185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 754185377Ssam } 755185377Ssam 756185377Ssam /* Construct wireless mode from EEPROM */ 757185377Ssam pCap->halWirelessModes = 0; 758185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 759185377Ssam pCap->halWirelessModes |= HAL_MODE_11A; 760185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 761185377Ssam pCap->halWirelessModes |= HAL_MODE_TURBO; 762185377Ssam } 763185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 764185377Ssam pCap->halWirelessModes |= HAL_MODE_11B; 765185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 766185377Ssam ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 767185377Ssam pCap->halWirelessModes |= HAL_MODE_11G; 768185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 769185377Ssam pCap->halWirelessModes |= HAL_MODE_108G; 770185377Ssam } 771185377Ssam 772185377Ssam pCap->halLow2GhzChan = 2312; 773185380Ssam /* XXX 2417 too? */ 774185380Ssam if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 775185377Ssam pCap->halHigh2GhzChan = 2500; 776185377Ssam else 777185377Ssam pCap->halHigh2GhzChan = 2732; 778185377Ssam 779185377Ssam pCap->halLow5GhzChan = 4915; 780185377Ssam pCap->halHigh5GhzChan = 6100; 781185377Ssam 782185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 783185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 784185377Ssam pCap->halCipherAesCcmSupport = 785185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 786185377Ssam ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 787185377Ssam ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 788185377Ssam (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 789185377Ssam 790185377Ssam pCap->halMicCkipSupport = AH_FALSE; 791185377Ssam pCap->halMicTkipSupport = AH_TRUE; 792185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 793185377Ssam /* 794185377Ssam * Starting with Griffin TX+RX mic keys can be combined 795185377Ssam * in one key cache slot. 796185377Ssam */ 797185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 798185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 799185377Ssam else 800185377Ssam pCap->halTkipMicTxRxKeySupport = AH_FALSE; 801185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 802185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 803185377Ssam 804185377Ssam if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 805185377Ssam pCap->halCompressSupport = 806185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 807185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 808185377Ssam pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 809185377Ssam pCap->halFastFramesSupport = 810185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 811185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 812185377Ssam pCap->halChapTuningSupport = AH_TRUE; 813185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 814185377Ssam } 815185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 816185377Ssam 817185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 818185377Ssam pCap->halVEOLSupport = AH_TRUE; 819185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 820185377Ssam pCap->halMcastKeySrchSupport = AH_TRUE; 821185377Ssam if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 822185377Ssam ahpriv->ah_macRev == 8) || 823185377Ssam ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 824185377Ssam pCap->halTsfAddSupport = AH_TRUE; 825185377Ssam 826185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 827185377Ssam pCap->halTotalQueues = val; 828185377Ssam else 829185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 830185377Ssam 831185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 832185377Ssam pCap->halKeyCacheSize = val; 833185377Ssam else 834185377Ssam pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 835185377Ssam 836185380Ssam pCap->halChanHalfRate = AH_TRUE; 837185380Ssam pCap->halChanQuarterRate = AH_TRUE; 838185377Ssam 839185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 840185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 841185377Ssam /* NB: enabled by default */ 842185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 843185377Ssam pCap->halRfSilentSupport = AH_TRUE; 844185377Ssam } 845185377Ssam 846185377Ssam /* NB: this is a guess, noone seems to know the answer */ 847185377Ssam ahpriv->ah_rxornIsFatal = 848185377Ssam (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 849185377Ssam 850195114Ssam /* enable features that first appeared in Hainan */ 851195114Ssam if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 852185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 853195114Ssam AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 854195114Ssam /* h/w phy counters */ 855195114Ssam pCap->halHwPhyCounterSupport = AH_TRUE; 856195114Ssam /* bssid match disable */ 857195114Ssam pCap->halBssidMatchSupport = AH_TRUE; 858195114Ssam } 859185377Ssam 860185377Ssam pCap->halTstampPrecision = 15; 861192396Ssam pCap->halIntrMask = HAL_INT_COMMON 862192396Ssam | HAL_INT_RX 863192396Ssam | HAL_INT_TX 864192396Ssam | HAL_INT_FATAL 865192396Ssam | HAL_INT_BNR 866192396Ssam | HAL_INT_BMISC 867192396Ssam ; 868192400Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 869192400Ssam pCap->halIntrMask &= ~HAL_INT_TBTT; 870185377Ssam 871218436Sadrian pCap->hal4kbSplitTransSupport = AH_TRUE; 872220324Sadrian pCap->halHasRxSelfLinkedTail = AH_TRUE; 873218436Sadrian 874185377Ssam return AH_TRUE; 875185377Ssam#undef IS_COBRA 876185377Ssam#undef IS_GRIFFIN_LITE 877185377Ssam#undef AR_KEYTABLE_SIZE 878185377Ssam} 879185406Ssam 880185406Ssamstatic const char* 881185406Ssamar5212Probe(uint16_t vendorid, uint16_t devid) 882185406Ssam{ 883185406Ssam if (vendorid == ATHEROS_VENDOR_ID || 884185406Ssam vendorid == ATHEROS_3COM_VENDOR_ID || 885185406Ssam vendorid == ATHEROS_3COM2_VENDOR_ID) { 886185406Ssam switch (devid) { 887185406Ssam case AR5212_FPGA: 888185406Ssam return "Atheros 5212 (FPGA)"; 889185406Ssam case AR5212_DEVID: 890185406Ssam case AR5212_DEVID_IBM: 891185406Ssam case AR5212_DEFAULT: 892185406Ssam return "Atheros 5212"; 893185406Ssam case AR5212_AR2413: 894185406Ssam return "Atheros 2413"; 895185406Ssam case AR5212_AR2417: 896185406Ssam return "Atheros 2417"; 897185406Ssam case AR5212_AR5413: 898185406Ssam return "Atheros 5413"; 899185406Ssam case AR5212_AR5424: 900185406Ssam return "Atheros 5424/2424"; 901185406Ssam } 902185406Ssam } 903185406Ssam return AH_NULL; 904185406Ssam} 905185418SsamAH_CHIP(AR5212, ar5212Probe, ar5212Attach); 906