ar5212_attach.c revision 217624
1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187831Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 217624 2011-01-20 07:56:09Z adrian $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25185377Ssam#include "ar5212/ar5212.h" 26185377Ssam#include "ar5212/ar5212reg.h" 27185377Ssam#include "ar5212/ar5212phy.h" 28185377Ssam 29185377Ssam#define AH_5212_COMMON 30185377Ssam#include "ar5212/ar5212.ini" 31185377Ssam 32188979Ssamstatic void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 33188979Ssamstatic void ar5212DisablePCIE(struct ath_hal *ah); 34188979Ssam 35185377Ssamstatic const struct ath_hal_private ar5212hal = {{ 36185377Ssam .ah_magic = AR5212_MAGIC, 37185377Ssam 38185377Ssam .ah_getRateTable = ar5212GetRateTable, 39185377Ssam .ah_detach = ar5212Detach, 40185377Ssam 41185377Ssam /* Reset Functions */ 42185377Ssam .ah_reset = ar5212Reset, 43185377Ssam .ah_phyDisable = ar5212PhyDisable, 44185377Ssam .ah_disable = ar5212Disable, 45188979Ssam .ah_configPCIE = ar5212ConfigPCIE, 46188979Ssam .ah_disablePCIE = ar5212DisablePCIE, 47185377Ssam .ah_setPCUConfig = ar5212SetPCUConfig, 48185377Ssam .ah_perCalibration = ar5212PerCalibration, 49185380Ssam .ah_perCalibrationN = ar5212PerCalibrationN, 50185380Ssam .ah_resetCalValid = ar5212ResetCalValid, 51185377Ssam .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 52185377Ssam .ah_getChanNoise = ath_hal_getChanNoise, 53185377Ssam 54185377Ssam /* Transmit functions */ 55185377Ssam .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 56185377Ssam .ah_setupTxQueue = ar5212SetupTxQueue, 57185377Ssam .ah_setTxQueueProps = ar5212SetTxQueueProps, 58185377Ssam .ah_getTxQueueProps = ar5212GetTxQueueProps, 59185377Ssam .ah_releaseTxQueue = ar5212ReleaseTxQueue, 60185377Ssam .ah_resetTxQueue = ar5212ResetTxQueue, 61185377Ssam .ah_getTxDP = ar5212GetTxDP, 62185377Ssam .ah_setTxDP = ar5212SetTxDP, 63185377Ssam .ah_numTxPending = ar5212NumTxPending, 64185377Ssam .ah_startTxDma = ar5212StartTxDma, 65185377Ssam .ah_stopTxDma = ar5212StopTxDma, 66185377Ssam .ah_setupTxDesc = ar5212SetupTxDesc, 67185377Ssam .ah_setupXTxDesc = ar5212SetupXTxDesc, 68185377Ssam .ah_fillTxDesc = ar5212FillTxDesc, 69185377Ssam .ah_procTxDesc = ar5212ProcTxDesc, 70185377Ssam .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 71185377Ssam .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 72217621Sadrian .ah_getTxCompletionRates = ar5212GetTxCompletionRates, 73185377Ssam 74185377Ssam /* RX Functions */ 75185377Ssam .ah_getRxDP = ar5212GetRxDP, 76185377Ssam .ah_setRxDP = ar5212SetRxDP, 77185377Ssam .ah_enableReceive = ar5212EnableReceive, 78185377Ssam .ah_stopDmaReceive = ar5212StopDmaReceive, 79185377Ssam .ah_startPcuReceive = ar5212StartPcuReceive, 80185377Ssam .ah_stopPcuReceive = ar5212StopPcuReceive, 81185377Ssam .ah_setMulticastFilter = ar5212SetMulticastFilter, 82185377Ssam .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 83185377Ssam .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 84185377Ssam .ah_getRxFilter = ar5212GetRxFilter, 85185377Ssam .ah_setRxFilter = ar5212SetRxFilter, 86185377Ssam .ah_setupRxDesc = ar5212SetupRxDesc, 87185377Ssam .ah_procRxDesc = ar5212ProcRxDesc, 88185377Ssam .ah_rxMonitor = ar5212AniPoll, 89185377Ssam .ah_procMibEvent = ar5212ProcessMibIntr, 90185377Ssam 91185377Ssam /* Misc Functions */ 92185377Ssam .ah_getCapability = ar5212GetCapability, 93185377Ssam .ah_setCapability = ar5212SetCapability, 94185377Ssam .ah_getDiagState = ar5212GetDiagState, 95185377Ssam .ah_getMacAddress = ar5212GetMacAddress, 96185377Ssam .ah_setMacAddress = ar5212SetMacAddress, 97185377Ssam .ah_getBssIdMask = ar5212GetBssIdMask, 98185377Ssam .ah_setBssIdMask = ar5212SetBssIdMask, 99185380Ssam .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 100185377Ssam .ah_setLedState = ar5212SetLedState, 101185377Ssam .ah_writeAssocid = ar5212WriteAssocid, 102185377Ssam .ah_gpioCfgInput = ar5212GpioCfgInput, 103185377Ssam .ah_gpioCfgOutput = ar5212GpioCfgOutput, 104185377Ssam .ah_gpioGet = ar5212GpioGet, 105185377Ssam .ah_gpioSet = ar5212GpioSet, 106185377Ssam .ah_gpioSetIntr = ar5212GpioSetIntr, 107185377Ssam .ah_getTsf32 = ar5212GetTsf32, 108185377Ssam .ah_getTsf64 = ar5212GetTsf64, 109185377Ssam .ah_resetTsf = ar5212ResetTsf, 110185377Ssam .ah_detectCardPresent = ar5212DetectCardPresent, 111185377Ssam .ah_updateMibCounters = ar5212UpdateMibCounters, 112185377Ssam .ah_getRfGain = ar5212GetRfgain, 113185377Ssam .ah_getDefAntenna = ar5212GetDefAntenna, 114185377Ssam .ah_setDefAntenna = ar5212SetDefAntenna, 115185377Ssam .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 116185377Ssam .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 117185377Ssam .ah_setSifsTime = ar5212SetSifsTime, 118185377Ssam .ah_getSifsTime = ar5212GetSifsTime, 119185377Ssam .ah_setSlotTime = ar5212SetSlotTime, 120185377Ssam .ah_getSlotTime = ar5212GetSlotTime, 121185377Ssam .ah_setAckTimeout = ar5212SetAckTimeout, 122185377Ssam .ah_getAckTimeout = ar5212GetAckTimeout, 123185377Ssam .ah_setAckCTSRate = ar5212SetAckCTSRate, 124185377Ssam .ah_getAckCTSRate = ar5212GetAckCTSRate, 125185377Ssam .ah_setCTSTimeout = ar5212SetCTSTimeout, 126185377Ssam .ah_getCTSTimeout = ar5212GetCTSTimeout, 127185377Ssam .ah_setDecompMask = ar5212SetDecompMask, 128185377Ssam .ah_setCoverageClass = ar5212SetCoverageClass, 129185377Ssam 130185377Ssam /* Key Cache Functions */ 131185377Ssam .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 132185377Ssam .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 133185377Ssam .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 134185377Ssam .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 135185377Ssam .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 136185377Ssam 137185377Ssam /* Power Management Functions */ 138185377Ssam .ah_setPowerMode = ar5212SetPowerMode, 139185377Ssam .ah_getPowerMode = ar5212GetPowerMode, 140185377Ssam 141185377Ssam /* Beacon Functions */ 142185377Ssam .ah_setBeaconTimers = ar5212SetBeaconTimers, 143185377Ssam .ah_beaconInit = ar5212BeaconInit, 144185377Ssam .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 145185377Ssam .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 146185377Ssam 147185377Ssam /* Interrupt Functions */ 148185377Ssam .ah_isInterruptPending = ar5212IsInterruptPending, 149185377Ssam .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 150185377Ssam .ah_getInterrupts = ar5212GetInterrupts, 151185377Ssam .ah_setInterrupts = ar5212SetInterrupts }, 152185377Ssam 153185377Ssam .ah_getChannelEdges = ar5212GetChannelEdges, 154185377Ssam .ah_getWirelessModes = ar5212GetWirelessModes, 155185377Ssam .ah_eepromRead = ar5212EepromRead, 156185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 157185377Ssam .ah_eepromWrite = ar5212EepromWrite, 158185377Ssam#endif 159185377Ssam .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 160185377Ssam}; 161185377Ssam 162185377Ssamuint32_t 163185377Ssamar5212GetRadioRev(struct ath_hal *ah) 164185377Ssam{ 165185377Ssam uint32_t val; 166185377Ssam int i; 167185377Ssam 168185377Ssam /* Read Radio Chip Rev Extract */ 169185377Ssam OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 170185377Ssam for (i = 0; i < 8; i++) 171185377Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 172185377Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 173185377Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 174185377Ssam return ath_hal_reverseBits(val, 8); 175185377Ssam} 176185377Ssam 177185377Ssamstatic void 178185377Ssamar5212AniSetup(struct ath_hal *ah) 179185377Ssam{ 180185377Ssam static const struct ar5212AniParams aniparams = { 181185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 182185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 183185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 184185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 185185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 186185377Ssam .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 187185377Ssam .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 188185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 189185377Ssam .firstep = { 0, 4, 8 }, 190185377Ssam .ofdmTrigHigh = 500, 191185377Ssam .ofdmTrigLow = 200, 192185377Ssam .cckTrigHigh = 200, 193185377Ssam .cckTrigLow = 100, 194185377Ssam .rssiThrHigh = 40, 195185377Ssam .rssiThrLow = 7, 196185377Ssam .period = 100, 197185377Ssam }; 198185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 199185377Ssam struct ar5212AniParams tmp; 200185377Ssam OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 201185377Ssam tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 202185377Ssam ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 203185377Ssam } else 204185377Ssam ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 205185377Ssam} 206185377Ssam 207185377Ssam/* 208185377Ssam * Attach for an AR5212 part. 209185377Ssam */ 210185377Ssamvoid 211185377Ssamar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 212185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 213185377Ssam{ 214185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 215185377Ssam static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 216185377Ssam { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 217185377Ssam struct ath_hal *ah; 218185377Ssam 219185377Ssam ah = &ahp->ah_priv.h; 220185377Ssam /* set initial values */ 221185377Ssam OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 222185377Ssam ah->ah_sc = sc; 223185377Ssam ah->ah_st = st; 224185377Ssam ah->ah_sh = sh; 225185377Ssam 226185377Ssam ah->ah_devid = devid; /* NB: for alq */ 227185377Ssam AH_PRIVATE(ah)->ah_devid = devid; 228185377Ssam AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 229185377Ssam 230185377Ssam AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 231185377Ssam AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 232185377Ssam 233185380Ssam ahp->ah_antControl = HAL_ANT_VARIABLE; 234185380Ssam ahp->ah_diversity = AH_TRUE; 235185377Ssam ahp->ah_bIQCalibration = AH_FALSE; 236185377Ssam /* 237185377Ssam * Enable MIC handling. 238185377Ssam */ 239185377Ssam ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 240185377Ssam ahp->ah_rssiThr = INIT_RSSI_THR; 241185377Ssam ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 242185380Ssam ahp->ah_phyPowerOn = AH_FALSE; 243185377Ssam ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 244185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CTS) 245185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 246185377Ssam ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 247185377Ssam ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 248185377Ssam ahp->ah_slottime = (u_int) -1; 249185377Ssam ahp->ah_acktimeout = (u_int) -1; 250185377Ssam ahp->ah_ctstimeout = (u_int) -1; 251185377Ssam ahp->ah_sifstime = (u_int) -1; 252204579Srpaulo ahp->ah_txTrigLev = INIT_TX_FIFO_THRESHOLD, 253204579Srpaulo ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD, 254204579Srpaulo 255185377Ssam OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 256185377Ssam#undef N 257185377Ssam} 258185377Ssam 259185377Ssam/* 260185377Ssam * Validate MAC version and revision. 261185377Ssam */ 262185377Ssamstatic HAL_BOOL 263185377Ssamar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 264185377Ssam{ 265185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 266185377Ssam static const struct { 267185377Ssam uint8_t version; 268185377Ssam uint8_t revMin, revMax; 269185377Ssam } macs[] = { 270185377Ssam { AR_SREV_VERSION_VENICE, 271185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 272185377Ssam { AR_SREV_VERSION_GRIFFIN, 273185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 274185377Ssam { AR_SREV_5413, 275185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 276185377Ssam { AR_SREV_5424, 277185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 278185377Ssam { AR_SREV_2425, 279185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 280185377Ssam { AR_SREV_2417, 281185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 282185377Ssam }; 283185377Ssam int i; 284185377Ssam 285185377Ssam for (i = 0; i < N(macs); i++) 286185377Ssam if (macs[i].version == macVersion && 287185377Ssam macs[i].revMin <= macRev && macRev <= macs[i].revMax) 288185377Ssam return AH_TRUE; 289185377Ssam return AH_FALSE; 290185377Ssam#undef N 291185377Ssam} 292185377Ssam 293185377Ssam/* 294185377Ssam * Attach for an AR5212 part. 295185377Ssam */ 296185406Ssamstatic struct ath_hal * 297185377Ssamar5212Attach(uint16_t devid, HAL_SOFTC sc, 298217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 299217624Sadrian HAL_STATUS *status) 300185377Ssam{ 301185377Ssam#define AH_EEPROM_PROTECT(ah) \ 302188979Ssam (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 303185377Ssam struct ath_hal_5212 *ahp; 304185377Ssam struct ath_hal *ah; 305185406Ssam struct ath_hal_rf *rf; 306185377Ssam uint32_t val; 307185377Ssam uint16_t eeval; 308185377Ssam HAL_STATUS ecode; 309185377Ssam 310185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 311185377Ssam __func__, sc, (void*) st, (void*) sh); 312185377Ssam 313185377Ssam /* NB: memory is returned zero'd */ 314185377Ssam ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 315185377Ssam if (ahp == AH_NULL) { 316185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 317185377Ssam "%s: cannot allocate memory for state block\n", __func__); 318185377Ssam *status = HAL_ENOMEM; 319185377Ssam return AH_NULL; 320185377Ssam } 321185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 322185377Ssam ah = &ahp->ah_priv.h; 323185377Ssam 324185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 325185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 326185377Ssam __func__); 327185377Ssam ecode = HAL_EIO; 328185377Ssam goto bad; 329185377Ssam } 330185377Ssam /* Read Revisions from Chips before taking out of reset */ 331185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 332185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 333185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 334188979Ssam AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 335185377Ssam 336185377Ssam if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 337185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 338185377Ssam "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 339185377Ssam __func__, AH_PRIVATE(ah)->ah_macVersion, 340185377Ssam AH_PRIVATE(ah)->ah_macRev); 341185377Ssam ecode = HAL_ENOTSUPP; 342185377Ssam goto bad; 343185377Ssam } 344185377Ssam 345185377Ssam /* setup common ini data; rf backends handle remainder */ 346185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 347185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 348185377Ssam 349185377Ssam if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 350185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 351185377Ssam ecode = HAL_EIO; 352185377Ssam goto bad; 353185377Ssam } 354185377Ssam 355185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 356185377Ssam 357188979Ssam if (AH_PRIVATE(ah)->ah_ispcie) { 358185377Ssam /* XXX: build flag to disable this? */ 359188979Ssam ath_hal_configPCIE(ah, AH_FALSE); 360185377Ssam } 361185377Ssam 362185377Ssam if (!ar5212ChipTest(ah)) { 363185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 364185377Ssam __func__); 365185377Ssam ecode = HAL_ESELFTEST; 366185377Ssam goto bad; 367185377Ssam } 368185377Ssam 369185377Ssam /* Enable PCI core retry fix in software for Hainan and up */ 370185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 371185377Ssam OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 372185377Ssam 373185377Ssam /* 374185377Ssam * Set correct Baseband to analog shift 375185377Ssam * setting to access analog chips. 376185377Ssam */ 377185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 378185377Ssam 379185377Ssam /* Read Radio Chip Rev Extract */ 380185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 381185406Ssam 382185406Ssam rf = ath_hal_rfprobe(ah, &ecode); 383185406Ssam if (rf == AH_NULL) 384185406Ssam goto bad; 385185406Ssam 386185377Ssam /* NB: silently accept anything in release code per Atheros */ 387185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 388185377Ssam case AR_RAD5111_SREV_MAJOR: 389185377Ssam case AR_RAD5112_SREV_MAJOR: 390185377Ssam case AR_RAD2112_SREV_MAJOR: 391185377Ssam case AR_RAD2111_SREV_MAJOR: 392185377Ssam case AR_RAD2413_SREV_MAJOR: 393185377Ssam case AR_RAD5413_SREV_MAJOR: 394185377Ssam case AR_RAD5424_SREV_MAJOR: 395185377Ssam break; 396185377Ssam default: 397185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 398185377Ssam /* 399185377Ssam * When RF_Silent is used, the 400185377Ssam * analog chip is reset. So when the system boots 401185377Ssam * up with the radio switch off we cannot determine 402185377Ssam * the RF chip rev. To workaround this check the 403185377Ssam * mac+phy revs and if Hainan, set the radio rev 404185377Ssam * to Derby. 405185377Ssam */ 406185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 407185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 408185377Ssam AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 409185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 410185377Ssam break; 411185377Ssam } 412185377Ssam if (IS_2413(ah)) { /* Griffin */ 413185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 414185380Ssam AR_RAD2413_SREV_MAJOR | 0x1; 415185377Ssam break; 416185377Ssam } 417185377Ssam if (IS_5413(ah)) { /* Eagle */ 418185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 419185380Ssam AR_RAD5413_SREV_MAJOR | 0x2; 420185377Ssam break; 421185377Ssam } 422185377Ssam if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 423185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 424185380Ssam AR_RAD5424_SREV_MAJOR | 0x2; 425185377Ssam break; 426185377Ssam } 427185377Ssam } 428185377Ssam#ifdef AH_DEBUG 429185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 430185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 431185377Ssam "this driver\n", 432185377Ssam __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 433185377Ssam ecode = HAL_ENOTSUPP; 434185377Ssam goto bad; 435185377Ssam#endif 436185377Ssam } 437185380Ssam if (IS_RAD5112_REV1(ah)) { 438185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 439185377Ssam "%s: 5112 Rev 1 is not supported by this " 440185377Ssam "driver (analog5GhzRev 0x%x)\n", __func__, 441185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 442185377Ssam ecode = HAL_ENOTSUPP; 443185377Ssam goto bad; 444185377Ssam } 445185377Ssam 446185377Ssam val = OS_REG_READ(ah, AR_PCICFG); 447185377Ssam val = MS(val, AR_PCICFG_EEPROM_SIZE); 448185377Ssam if (val == 0) { 449188979Ssam if (!AH_PRIVATE(ah)->ah_ispcie) { 450185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 451185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 452185377Ssam __func__, val, val); 453185377Ssam ecode = HAL_EESIZE; 454185377Ssam goto bad; 455185377Ssam } 456185377Ssam /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 457185377Ssam } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 458185377Ssam if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 459185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 460185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 461185377Ssam __func__, val, val); 462185377Ssam ecode = HAL_EESIZE; 463185377Ssam goto bad; 464185377Ssam } 465185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 466185377Ssam "%s: EEPROM size = %d. Must be %d (16k).\n", 467185377Ssam __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 468185377Ssam ecode = HAL_EESIZE; 469185377Ssam goto bad; 470185377Ssam } 471185377Ssam ecode = ath_hal_legacyEepromAttach(ah); 472185377Ssam if (ecode != HAL_OK) { 473185377Ssam goto bad; 474185377Ssam } 475185377Ssam ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 476185377Ssam 477185377Ssam /* 478185377Ssam * If Bmode and AR5212, verify 2.4 analog exists 479185377Ssam */ 480185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 481185377Ssam (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 482185377Ssam /* 483185377Ssam * Set correct Baseband to analog shift 484185377Ssam * setting to access analog chips. 485185377Ssam */ 486185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 487185377Ssam OS_DELAY(2000); 488185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 489185377Ssam 490185377Ssam /* Set baseband for 5GHz chip */ 491185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 492185377Ssam OS_DELAY(2000); 493185377Ssam if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 494185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 495185377Ssam "%s: 2G Radio Chip Rev 0x%02X is not " 496185377Ssam "supported by this driver\n", __func__, 497185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev); 498185377Ssam ecode = HAL_ENOTSUPP; 499185377Ssam goto bad; 500185377Ssam } 501185377Ssam } 502185377Ssam 503185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 504185377Ssam if (ecode != HAL_OK) { 505185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 506185377Ssam "%s: cannot read regulatory domain from EEPROM\n", 507185377Ssam __func__); 508185377Ssam goto bad; 509185377Ssam } 510185377Ssam AH_PRIVATE(ah)->ah_currentRD = eeval; 511185377Ssam /* XXX record serial number */ 512185377Ssam 513185377Ssam /* 514185377Ssam * Got everything we need now to setup the capabilities. 515185377Ssam */ 516185377Ssam if (!ar5212FillCapabilityInfo(ah)) { 517185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 518185377Ssam "%s: failed ar5212FillCapabilityInfo\n", __func__); 519185377Ssam ecode = HAL_EEREAD; 520185377Ssam goto bad; 521185377Ssam } 522185377Ssam 523185406Ssam if (!rf->attach(ah, &ecode)) { 524185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 525185377Ssam __func__, ecode); 526185377Ssam goto bad; 527185377Ssam } 528185377Ssam /* 529185377Ssam * Set noise floor adjust method; we arrange a 530185377Ssam * direct call instead of thunking. 531185377Ssam */ 532185377Ssam AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 533185377Ssam 534185377Ssam /* Initialize gain ladder thermal calibration structure */ 535185377Ssam ar5212InitializeGainValues(ah); 536185377Ssam 537185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 538185377Ssam if (ecode != HAL_OK) { 539185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 540185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 541185377Ssam goto bad; 542185377Ssam } 543185377Ssam 544185377Ssam ar5212AniSetup(ah); 545185377Ssam /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 546185377Ssam ar5212InitNfCalHistBuffer(ah); 547185377Ssam 548185377Ssam /* XXX EAR stuff goes here */ 549185377Ssam 550185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 551185377Ssam 552185377Ssam return ah; 553185377Ssam 554185377Ssambad: 555185377Ssam if (ahp) 556185377Ssam ar5212Detach((struct ath_hal *) ahp); 557185377Ssam if (status) 558185377Ssam *status = ecode; 559185377Ssam return AH_NULL; 560185377Ssam#undef AH_EEPROM_PROTECT 561185377Ssam} 562185377Ssam 563185377Ssamvoid 564185377Ssamar5212Detach(struct ath_hal *ah) 565185377Ssam{ 566185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 567185377Ssam 568185377Ssam HALASSERT(ah != AH_NULL); 569185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 570185377Ssam 571185377Ssam ar5212AniDetach(ah); 572185377Ssam ar5212RfDetach(ah); 573185377Ssam ar5212Disable(ah); 574185377Ssam ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 575185377Ssam 576185377Ssam ath_hal_eepromDetach(ah); 577185377Ssam ath_hal_free(ah); 578185377Ssam} 579185377Ssam 580185377SsamHAL_BOOL 581185377Ssamar5212ChipTest(struct ath_hal *ah) 582185377Ssam{ 583185377Ssam uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 584185377Ssam uint32_t regHold[2]; 585185377Ssam uint32_t patternData[4] = 586185377Ssam { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 587185377Ssam int i, j; 588185377Ssam 589185377Ssam /* Test PHY & MAC registers */ 590185377Ssam for (i = 0; i < 2; i++) { 591185377Ssam uint32_t addr = regAddr[i]; 592185377Ssam uint32_t wrData, rdData; 593185377Ssam 594185377Ssam regHold[i] = OS_REG_READ(ah, addr); 595185377Ssam for (j = 0; j < 0x100; j++) { 596185377Ssam wrData = (j << 16) | j; 597185377Ssam OS_REG_WRITE(ah, addr, wrData); 598185377Ssam rdData = OS_REG_READ(ah, addr); 599185377Ssam if (rdData != wrData) { 600185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 601185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 602185377Ssam __func__, addr, wrData, rdData); 603185377Ssam return AH_FALSE; 604185377Ssam } 605185377Ssam } 606185377Ssam for (j = 0; j < 4; j++) { 607185377Ssam wrData = patternData[j]; 608185377Ssam OS_REG_WRITE(ah, addr, wrData); 609185377Ssam rdData = OS_REG_READ(ah, addr); 610185377Ssam if (wrData != rdData) { 611185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 612185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 613185377Ssam __func__, addr, wrData, rdData); 614185377Ssam return AH_FALSE; 615185377Ssam } 616185377Ssam } 617185377Ssam OS_REG_WRITE(ah, regAddr[i], regHold[i]); 618185377Ssam } 619185377Ssam OS_DELAY(100); 620185377Ssam return AH_TRUE; 621185377Ssam} 622185377Ssam 623185377Ssam/* 624185377Ssam * Store the channel edges for the requested operational mode 625185377Ssam */ 626185377SsamHAL_BOOL 627185377Ssamar5212GetChannelEdges(struct ath_hal *ah, 628185377Ssam uint16_t flags, uint16_t *low, uint16_t *high) 629185377Ssam{ 630187831Ssam if (flags & IEEE80211_CHAN_5GHZ) { 631185377Ssam *low = 4915; 632185377Ssam *high = 6100; 633185377Ssam return AH_TRUE; 634185377Ssam } 635187831Ssam if ((flags & IEEE80211_CHAN_2GHZ) && 636185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 637185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 638185377Ssam *low = 2312; 639185377Ssam *high = 2732; 640185377Ssam return AH_TRUE; 641185377Ssam } 642185377Ssam return AH_FALSE; 643185377Ssam} 644185377Ssam 645185377Ssam/* 646188979Ssam * Disable PLL when in L0s as well as receiver clock when in L1. 647188979Ssam * This power saving option must be enabled through the Serdes. 648188979Ssam * 649188979Ssam * Programming the Serdes must go through the same 288 bit serial shift 650188979Ssam * register as the other analog registers. Hence the 9 writes. 651188979Ssam * 652188979Ssam * XXX Clean up the magic numbers. 653188979Ssam */ 654188979Ssamstatic void 655188979Ssamar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 656188979Ssam{ 657188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 658188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 659188979Ssam 660188979Ssam /* RX shut off when elecidle is asserted */ 661188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 662188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 663188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 664188979Ssam 665188979Ssam /* Shut off PLL and CLKREQ active in L1 */ 666188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 667188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 668188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 669188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 670188979Ssam 671188979Ssam /* Load the new settings */ 672188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 673188979Ssam} 674188979Ssam 675188979Ssamstatic void 676188979Ssamar5212DisablePCIE(struct ath_hal *ah) 677188979Ssam{ 678188979Ssam /* NB: fill in for 9100 */ 679188979Ssam} 680188979Ssam 681188979Ssam/* 682185377Ssam * Fill all software cached or static hardware state information. 683185377Ssam * Return failure if capabilities are to come from EEPROM and 684185377Ssam * cannot be read. 685185377Ssam */ 686185377SsamHAL_BOOL 687185377Ssamar5212FillCapabilityInfo(struct ath_hal *ah) 688185377Ssam{ 689185377Ssam#define AR_KEYTABLE_SIZE 128 690185377Ssam#define IS_GRIFFIN_LITE(ah) \ 691185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 692185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 693185377Ssam#define IS_COBRA(ah) \ 694185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 695185377Ssam#define IS_2112(ah) \ 696185377Ssam ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 697185377Ssam 698185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 699185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 700185377Ssam uint16_t capField, val; 701185377Ssam 702185377Ssam /* Read the capability EEPROM location */ 703185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 704185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 705185377Ssam "%s: unable to read caps from eeprom\n", __func__); 706185377Ssam return AH_FALSE; 707185377Ssam } 708185377Ssam if (IS_2112(ah)) 709185377Ssam ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 710185377Ssam if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 711185377Ssam /* 712185377Ssam * For griffin-lite cards with unprogrammed capabilities. 713185377Ssam */ 714185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 715185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 716185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 717185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 718185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 719185377Ssam "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 720185377Ssam __func__, capField); 721185377Ssam } 722185377Ssam 723185377Ssam /* Modify reg domain on newer cards that need to work with older sw */ 724185377Ssam if (ahpriv->ah_opmode != HAL_M_HOSTAP && 725185377Ssam ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 726185377Ssam if (ahpriv->ah_currentRD == 0x64 || 727185377Ssam ahpriv->ah_currentRD == 0x65) 728185377Ssam ahpriv->ah_currentRD += 5; 729185377Ssam else if (ahpriv->ah_currentRD == 0x41) 730185377Ssam ahpriv->ah_currentRD = 0x43; 731185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 732185377Ssam __func__, ahpriv->ah_currentRD); 733185377Ssam } 734185377Ssam 735185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 736185377Ssam AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 737185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 738185377Ssam "%s: enable Bmode and disable turbo for Swan/Nala\n", 739185377Ssam __func__); 740185377Ssam ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 741185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 742185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 743185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 744185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 745185377Ssam } 746185377Ssam 747185377Ssam /* Construct wireless mode from EEPROM */ 748185377Ssam pCap->halWirelessModes = 0; 749185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 750185377Ssam pCap->halWirelessModes |= HAL_MODE_11A; 751185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 752185377Ssam pCap->halWirelessModes |= HAL_MODE_TURBO; 753185377Ssam } 754185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 755185377Ssam pCap->halWirelessModes |= HAL_MODE_11B; 756185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 757185377Ssam ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 758185377Ssam pCap->halWirelessModes |= HAL_MODE_11G; 759185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 760185377Ssam pCap->halWirelessModes |= HAL_MODE_108G; 761185377Ssam } 762185377Ssam 763185377Ssam pCap->halLow2GhzChan = 2312; 764185380Ssam /* XXX 2417 too? */ 765185380Ssam if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 766185377Ssam pCap->halHigh2GhzChan = 2500; 767185377Ssam else 768185377Ssam pCap->halHigh2GhzChan = 2732; 769185377Ssam 770185377Ssam pCap->halLow5GhzChan = 4915; 771185377Ssam pCap->halHigh5GhzChan = 6100; 772185377Ssam 773185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 774185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 775185377Ssam pCap->halCipherAesCcmSupport = 776185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 777185377Ssam ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 778185377Ssam ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 779185377Ssam (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 780185377Ssam 781185377Ssam pCap->halMicCkipSupport = AH_FALSE; 782185377Ssam pCap->halMicTkipSupport = AH_TRUE; 783185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 784185377Ssam /* 785185377Ssam * Starting with Griffin TX+RX mic keys can be combined 786185377Ssam * in one key cache slot. 787185377Ssam */ 788185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 789185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 790185377Ssam else 791185377Ssam pCap->halTkipMicTxRxKeySupport = AH_FALSE; 792185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 793185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 794185377Ssam 795185377Ssam if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 796185377Ssam pCap->halCompressSupport = 797185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 798185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 799185377Ssam pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 800185377Ssam pCap->halFastFramesSupport = 801185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 802185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 803185377Ssam pCap->halChapTuningSupport = AH_TRUE; 804185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 805185377Ssam } 806185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 807185377Ssam 808185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 809185377Ssam pCap->halVEOLSupport = AH_TRUE; 810185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 811185377Ssam pCap->halMcastKeySrchSupport = AH_TRUE; 812185377Ssam if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 813185377Ssam ahpriv->ah_macRev == 8) || 814185377Ssam ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 815185377Ssam pCap->halTsfAddSupport = AH_TRUE; 816185377Ssam 817185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 818185377Ssam pCap->halTotalQueues = val; 819185377Ssam else 820185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 821185377Ssam 822185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 823185377Ssam pCap->halKeyCacheSize = val; 824185377Ssam else 825185377Ssam pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 826185377Ssam 827185380Ssam pCap->halChanHalfRate = AH_TRUE; 828185380Ssam pCap->halChanQuarterRate = AH_TRUE; 829185377Ssam 830185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 831185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 832185377Ssam /* NB: enabled by default */ 833185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 834185377Ssam pCap->halRfSilentSupport = AH_TRUE; 835185377Ssam } 836185377Ssam 837185377Ssam /* NB: this is a guess, noone seems to know the answer */ 838185377Ssam ahpriv->ah_rxornIsFatal = 839185377Ssam (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 840185377Ssam 841195114Ssam /* enable features that first appeared in Hainan */ 842195114Ssam if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 843185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 844195114Ssam AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 845195114Ssam /* h/w phy counters */ 846195114Ssam pCap->halHwPhyCounterSupport = AH_TRUE; 847195114Ssam /* bssid match disable */ 848195114Ssam pCap->halBssidMatchSupport = AH_TRUE; 849195114Ssam } 850185377Ssam 851185377Ssam pCap->halTstampPrecision = 15; 852192396Ssam pCap->halIntrMask = HAL_INT_COMMON 853192396Ssam | HAL_INT_RX 854192396Ssam | HAL_INT_TX 855192396Ssam | HAL_INT_FATAL 856192396Ssam | HAL_INT_BNR 857192396Ssam | HAL_INT_BMISC 858192396Ssam ; 859192400Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 860192400Ssam pCap->halIntrMask &= ~HAL_INT_TBTT; 861185377Ssam 862185377Ssam return AH_TRUE; 863185377Ssam#undef IS_COBRA 864185377Ssam#undef IS_GRIFFIN_LITE 865185377Ssam#undef AR_KEYTABLE_SIZE 866185377Ssam} 867185406Ssam 868185406Ssamstatic const char* 869185406Ssamar5212Probe(uint16_t vendorid, uint16_t devid) 870185406Ssam{ 871185406Ssam if (vendorid == ATHEROS_VENDOR_ID || 872185406Ssam vendorid == ATHEROS_3COM_VENDOR_ID || 873185406Ssam vendorid == ATHEROS_3COM2_VENDOR_ID) { 874185406Ssam switch (devid) { 875185406Ssam case AR5212_FPGA: 876185406Ssam return "Atheros 5212 (FPGA)"; 877185406Ssam case AR5212_DEVID: 878185406Ssam case AR5212_DEVID_IBM: 879185406Ssam case AR5212_DEFAULT: 880185406Ssam return "Atheros 5212"; 881185406Ssam case AR5212_AR2413: 882185406Ssam return "Atheros 2413"; 883185406Ssam case AR5212_AR2417: 884185406Ssam return "Atheros 2417"; 885185406Ssam case AR5212_AR5413: 886185406Ssam return "Atheros 5413"; 887185406Ssam case AR5212_AR5424: 888185406Ssam return "Atheros 5424/2424"; 889185406Ssam } 890185406Ssam } 891185406Ssam return AH_NULL; 892185406Ssam} 893185418SsamAH_CHIP(AR5212, ar5212Probe, ar5212Attach); 894