ar5212_attach.c revision 195114
1185377Ssam/* 2187831Ssam * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17187831Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_attach.c 195114 2009-06-27 20:06:56Z sam $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25185377Ssam#include "ar5212/ar5212.h" 26185377Ssam#include "ar5212/ar5212reg.h" 27185377Ssam#include "ar5212/ar5212phy.h" 28185377Ssam 29185377Ssam#define AH_5212_COMMON 30185377Ssam#include "ar5212/ar5212.ini" 31185377Ssam 32188979Ssamstatic void ar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 33188979Ssamstatic void ar5212DisablePCIE(struct ath_hal *ah); 34188979Ssam 35185377Ssamstatic const struct ath_hal_private ar5212hal = {{ 36185377Ssam .ah_magic = AR5212_MAGIC, 37185377Ssam 38185377Ssam .ah_getRateTable = ar5212GetRateTable, 39185377Ssam .ah_detach = ar5212Detach, 40185377Ssam 41185377Ssam /* Reset Functions */ 42185377Ssam .ah_reset = ar5212Reset, 43185377Ssam .ah_phyDisable = ar5212PhyDisable, 44185377Ssam .ah_disable = ar5212Disable, 45188979Ssam .ah_configPCIE = ar5212ConfigPCIE, 46188979Ssam .ah_disablePCIE = ar5212DisablePCIE, 47185377Ssam .ah_setPCUConfig = ar5212SetPCUConfig, 48185377Ssam .ah_perCalibration = ar5212PerCalibration, 49185380Ssam .ah_perCalibrationN = ar5212PerCalibrationN, 50185380Ssam .ah_resetCalValid = ar5212ResetCalValid, 51185377Ssam .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 52185377Ssam .ah_getChanNoise = ath_hal_getChanNoise, 53185377Ssam 54185377Ssam /* Transmit functions */ 55185377Ssam .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 56185377Ssam .ah_setupTxQueue = ar5212SetupTxQueue, 57185377Ssam .ah_setTxQueueProps = ar5212SetTxQueueProps, 58185377Ssam .ah_getTxQueueProps = ar5212GetTxQueueProps, 59185377Ssam .ah_releaseTxQueue = ar5212ReleaseTxQueue, 60185377Ssam .ah_resetTxQueue = ar5212ResetTxQueue, 61185377Ssam .ah_getTxDP = ar5212GetTxDP, 62185377Ssam .ah_setTxDP = ar5212SetTxDP, 63185377Ssam .ah_numTxPending = ar5212NumTxPending, 64185377Ssam .ah_startTxDma = ar5212StartTxDma, 65185377Ssam .ah_stopTxDma = ar5212StopTxDma, 66185377Ssam .ah_setupTxDesc = ar5212SetupTxDesc, 67185377Ssam .ah_setupXTxDesc = ar5212SetupXTxDesc, 68185377Ssam .ah_fillTxDesc = ar5212FillTxDesc, 69185377Ssam .ah_procTxDesc = ar5212ProcTxDesc, 70185377Ssam .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 71185377Ssam .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 72185377Ssam 73185377Ssam /* RX Functions */ 74185377Ssam .ah_getRxDP = ar5212GetRxDP, 75185377Ssam .ah_setRxDP = ar5212SetRxDP, 76185377Ssam .ah_enableReceive = ar5212EnableReceive, 77185377Ssam .ah_stopDmaReceive = ar5212StopDmaReceive, 78185377Ssam .ah_startPcuReceive = ar5212StartPcuReceive, 79185377Ssam .ah_stopPcuReceive = ar5212StopPcuReceive, 80185377Ssam .ah_setMulticastFilter = ar5212SetMulticastFilter, 81185377Ssam .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 82185377Ssam .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 83185377Ssam .ah_getRxFilter = ar5212GetRxFilter, 84185377Ssam .ah_setRxFilter = ar5212SetRxFilter, 85185377Ssam .ah_setupRxDesc = ar5212SetupRxDesc, 86185377Ssam .ah_procRxDesc = ar5212ProcRxDesc, 87185377Ssam .ah_rxMonitor = ar5212AniPoll, 88185377Ssam .ah_procMibEvent = ar5212ProcessMibIntr, 89185377Ssam 90185377Ssam /* Misc Functions */ 91185377Ssam .ah_getCapability = ar5212GetCapability, 92185377Ssam .ah_setCapability = ar5212SetCapability, 93185377Ssam .ah_getDiagState = ar5212GetDiagState, 94185377Ssam .ah_getMacAddress = ar5212GetMacAddress, 95185377Ssam .ah_setMacAddress = ar5212SetMacAddress, 96185377Ssam .ah_getBssIdMask = ar5212GetBssIdMask, 97185377Ssam .ah_setBssIdMask = ar5212SetBssIdMask, 98185380Ssam .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 99185377Ssam .ah_setLedState = ar5212SetLedState, 100185377Ssam .ah_writeAssocid = ar5212WriteAssocid, 101185377Ssam .ah_gpioCfgInput = ar5212GpioCfgInput, 102185377Ssam .ah_gpioCfgOutput = ar5212GpioCfgOutput, 103185377Ssam .ah_gpioGet = ar5212GpioGet, 104185377Ssam .ah_gpioSet = ar5212GpioSet, 105185377Ssam .ah_gpioSetIntr = ar5212GpioSetIntr, 106185377Ssam .ah_getTsf32 = ar5212GetTsf32, 107185377Ssam .ah_getTsf64 = ar5212GetTsf64, 108185377Ssam .ah_resetTsf = ar5212ResetTsf, 109185377Ssam .ah_detectCardPresent = ar5212DetectCardPresent, 110185377Ssam .ah_updateMibCounters = ar5212UpdateMibCounters, 111185377Ssam .ah_getRfGain = ar5212GetRfgain, 112185377Ssam .ah_getDefAntenna = ar5212GetDefAntenna, 113185377Ssam .ah_setDefAntenna = ar5212SetDefAntenna, 114185377Ssam .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 115185377Ssam .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 116185377Ssam .ah_setSifsTime = ar5212SetSifsTime, 117185377Ssam .ah_getSifsTime = ar5212GetSifsTime, 118185377Ssam .ah_setSlotTime = ar5212SetSlotTime, 119185377Ssam .ah_getSlotTime = ar5212GetSlotTime, 120185377Ssam .ah_setAckTimeout = ar5212SetAckTimeout, 121185377Ssam .ah_getAckTimeout = ar5212GetAckTimeout, 122185377Ssam .ah_setAckCTSRate = ar5212SetAckCTSRate, 123185377Ssam .ah_getAckCTSRate = ar5212GetAckCTSRate, 124185377Ssam .ah_setCTSTimeout = ar5212SetCTSTimeout, 125185377Ssam .ah_getCTSTimeout = ar5212GetCTSTimeout, 126185377Ssam .ah_setDecompMask = ar5212SetDecompMask, 127185377Ssam .ah_setCoverageClass = ar5212SetCoverageClass, 128185377Ssam 129185377Ssam /* Key Cache Functions */ 130185377Ssam .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 131185377Ssam .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 132185377Ssam .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 133185377Ssam .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 134185377Ssam .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 135185377Ssam 136185377Ssam /* Power Management Functions */ 137185377Ssam .ah_setPowerMode = ar5212SetPowerMode, 138185377Ssam .ah_getPowerMode = ar5212GetPowerMode, 139185377Ssam 140185377Ssam /* Beacon Functions */ 141185377Ssam .ah_setBeaconTimers = ar5212SetBeaconTimers, 142185377Ssam .ah_beaconInit = ar5212BeaconInit, 143185377Ssam .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 144185377Ssam .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 145185377Ssam 146185377Ssam /* Interrupt Functions */ 147185377Ssam .ah_isInterruptPending = ar5212IsInterruptPending, 148185377Ssam .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 149185377Ssam .ah_getInterrupts = ar5212GetInterrupts, 150185377Ssam .ah_setInterrupts = ar5212SetInterrupts }, 151185377Ssam 152185377Ssam .ah_getChannelEdges = ar5212GetChannelEdges, 153185377Ssam .ah_getWirelessModes = ar5212GetWirelessModes, 154185377Ssam .ah_eepromRead = ar5212EepromRead, 155185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 156185377Ssam .ah_eepromWrite = ar5212EepromWrite, 157185377Ssam#endif 158185377Ssam .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 159185377Ssam}; 160185377Ssam 161185377Ssamuint32_t 162185377Ssamar5212GetRadioRev(struct ath_hal *ah) 163185377Ssam{ 164185377Ssam uint32_t val; 165185377Ssam int i; 166185377Ssam 167185377Ssam /* Read Radio Chip Rev Extract */ 168185377Ssam OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 169185377Ssam for (i = 0; i < 8; i++) 170185377Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 171185377Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 172185377Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 173185377Ssam return ath_hal_reverseBits(val, 8); 174185377Ssam} 175185377Ssam 176185377Ssamstatic void 177185377Ssamar5212AniSetup(struct ath_hal *ah) 178185377Ssam{ 179185377Ssam static const struct ar5212AniParams aniparams = { 180185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 181185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 182185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 183185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 184185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 185185377Ssam .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 186185377Ssam .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 187185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 188185377Ssam .firstep = { 0, 4, 8 }, 189185377Ssam .ofdmTrigHigh = 500, 190185377Ssam .ofdmTrigLow = 200, 191185377Ssam .cckTrigHigh = 200, 192185377Ssam .cckTrigLow = 100, 193185377Ssam .rssiThrHigh = 40, 194185377Ssam .rssiThrLow = 7, 195185377Ssam .period = 100, 196185377Ssam }; 197185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 198185377Ssam struct ar5212AniParams tmp; 199185377Ssam OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 200185377Ssam tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 201185377Ssam ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 202185377Ssam } else 203185377Ssam ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 204185377Ssam} 205185377Ssam 206185377Ssam/* 207185377Ssam * Attach for an AR5212 part. 208185377Ssam */ 209185377Ssamvoid 210185377Ssamar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 211185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 212185377Ssam{ 213185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 214185377Ssam static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 215185377Ssam { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 216185377Ssam struct ath_hal *ah; 217185377Ssam 218185377Ssam ah = &ahp->ah_priv.h; 219185377Ssam /* set initial values */ 220185377Ssam OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 221185377Ssam ah->ah_sc = sc; 222185377Ssam ah->ah_st = st; 223185377Ssam ah->ah_sh = sh; 224185377Ssam 225185377Ssam ah->ah_devid = devid; /* NB: for alq */ 226185377Ssam AH_PRIVATE(ah)->ah_devid = devid; 227185377Ssam AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 228185377Ssam 229185377Ssam AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 230185377Ssam AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 231185377Ssam 232185380Ssam ahp->ah_antControl = HAL_ANT_VARIABLE; 233185380Ssam ahp->ah_diversity = AH_TRUE; 234185377Ssam ahp->ah_bIQCalibration = AH_FALSE; 235185377Ssam /* 236185377Ssam * Enable MIC handling. 237185377Ssam */ 238185377Ssam ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 239185377Ssam ahp->ah_rssiThr = INIT_RSSI_THR; 240185377Ssam ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 241185380Ssam ahp->ah_phyPowerOn = AH_FALSE; 242185377Ssam ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 243185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CTS) 244185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 245185377Ssam ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 246185377Ssam ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 247185377Ssam ahp->ah_slottime = (u_int) -1; 248185377Ssam ahp->ah_acktimeout = (u_int) -1; 249185377Ssam ahp->ah_ctstimeout = (u_int) -1; 250185377Ssam ahp->ah_sifstime = (u_int) -1; 251185377Ssam OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 252185377Ssam#undef N 253185377Ssam} 254185377Ssam 255185377Ssam/* 256185377Ssam * Validate MAC version and revision. 257185377Ssam */ 258185377Ssamstatic HAL_BOOL 259185377Ssamar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 260185377Ssam{ 261185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 262185377Ssam static const struct { 263185377Ssam uint8_t version; 264185377Ssam uint8_t revMin, revMax; 265185377Ssam } macs[] = { 266185377Ssam { AR_SREV_VERSION_VENICE, 267185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 268185377Ssam { AR_SREV_VERSION_GRIFFIN, 269185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 270185377Ssam { AR_SREV_5413, 271185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 272185377Ssam { AR_SREV_5424, 273185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 274185377Ssam { AR_SREV_2425, 275185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 276185377Ssam { AR_SREV_2417, 277185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 278185377Ssam }; 279185377Ssam int i; 280185377Ssam 281185377Ssam for (i = 0; i < N(macs); i++) 282185377Ssam if (macs[i].version == macVersion && 283185377Ssam macs[i].revMin <= macRev && macRev <= macs[i].revMax) 284185377Ssam return AH_TRUE; 285185377Ssam return AH_FALSE; 286185377Ssam#undef N 287185377Ssam} 288185377Ssam 289185377Ssam/* 290185377Ssam * Attach for an AR5212 part. 291185377Ssam */ 292185406Ssamstatic struct ath_hal * 293185377Ssamar5212Attach(uint16_t devid, HAL_SOFTC sc, 294185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 295185377Ssam{ 296185377Ssam#define AH_EEPROM_PROTECT(ah) \ 297188979Ssam (AH_PRIVATE(ah)->ah_ispcie)? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 298185377Ssam struct ath_hal_5212 *ahp; 299185377Ssam struct ath_hal *ah; 300185406Ssam struct ath_hal_rf *rf; 301185377Ssam uint32_t val; 302185377Ssam uint16_t eeval; 303185377Ssam HAL_STATUS ecode; 304185377Ssam 305185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 306185377Ssam __func__, sc, (void*) st, (void*) sh); 307185377Ssam 308185377Ssam /* NB: memory is returned zero'd */ 309185377Ssam ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 310185377Ssam if (ahp == AH_NULL) { 311185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 312185377Ssam "%s: cannot allocate memory for state block\n", __func__); 313185377Ssam *status = HAL_ENOMEM; 314185377Ssam return AH_NULL; 315185377Ssam } 316185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 317185377Ssam ah = &ahp->ah_priv.h; 318185377Ssam 319185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 320185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 321185377Ssam __func__); 322185377Ssam ecode = HAL_EIO; 323185377Ssam goto bad; 324185377Ssam } 325185377Ssam /* Read Revisions from Chips before taking out of reset */ 326185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 327185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 328185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 329188979Ssam AH_PRIVATE(ah)->ah_ispcie = IS_5424(ah) || IS_2425(ah); 330185377Ssam 331185377Ssam if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 332185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 333185377Ssam "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 334185377Ssam __func__, AH_PRIVATE(ah)->ah_macVersion, 335185377Ssam AH_PRIVATE(ah)->ah_macRev); 336185377Ssam ecode = HAL_ENOTSUPP; 337185377Ssam goto bad; 338185377Ssam } 339185377Ssam 340185377Ssam /* setup common ini data; rf backends handle remainder */ 341185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 342185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 343185377Ssam 344185377Ssam if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 345185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 346185377Ssam ecode = HAL_EIO; 347185377Ssam goto bad; 348185377Ssam } 349185377Ssam 350185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 351185377Ssam 352188979Ssam if (AH_PRIVATE(ah)->ah_ispcie) { 353185377Ssam /* XXX: build flag to disable this? */ 354188979Ssam ath_hal_configPCIE(ah, AH_FALSE); 355185377Ssam } 356185377Ssam 357185377Ssam if (!ar5212ChipTest(ah)) { 358185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 359185377Ssam __func__); 360185377Ssam ecode = HAL_ESELFTEST; 361185377Ssam goto bad; 362185377Ssam } 363185377Ssam 364185377Ssam /* Enable PCI core retry fix in software for Hainan and up */ 365185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 366185377Ssam OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 367185377Ssam 368185377Ssam /* 369185377Ssam * Set correct Baseband to analog shift 370185377Ssam * setting to access analog chips. 371185377Ssam */ 372185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 373185377Ssam 374185377Ssam /* Read Radio Chip Rev Extract */ 375185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 376185406Ssam 377185406Ssam rf = ath_hal_rfprobe(ah, &ecode); 378185406Ssam if (rf == AH_NULL) 379185406Ssam goto bad; 380185406Ssam 381185377Ssam /* NB: silently accept anything in release code per Atheros */ 382185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 383185377Ssam case AR_RAD5111_SREV_MAJOR: 384185377Ssam case AR_RAD5112_SREV_MAJOR: 385185377Ssam case AR_RAD2112_SREV_MAJOR: 386185377Ssam case AR_RAD2111_SREV_MAJOR: 387185377Ssam case AR_RAD2413_SREV_MAJOR: 388185377Ssam case AR_RAD5413_SREV_MAJOR: 389185377Ssam case AR_RAD5424_SREV_MAJOR: 390185377Ssam break; 391185377Ssam default: 392185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 393185377Ssam /* 394185377Ssam * When RF_Silent is used, the 395185377Ssam * analog chip is reset. So when the system boots 396185377Ssam * up with the radio switch off we cannot determine 397185377Ssam * the RF chip rev. To workaround this check the 398185377Ssam * mac+phy revs and if Hainan, set the radio rev 399185377Ssam * to Derby. 400185377Ssam */ 401185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 402185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 403185377Ssam AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 404185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 405185377Ssam break; 406185377Ssam } 407185377Ssam if (IS_2413(ah)) { /* Griffin */ 408185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 409185380Ssam AR_RAD2413_SREV_MAJOR | 0x1; 410185377Ssam break; 411185377Ssam } 412185377Ssam if (IS_5413(ah)) { /* Eagle */ 413185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 414185380Ssam AR_RAD5413_SREV_MAJOR | 0x2; 415185377Ssam break; 416185377Ssam } 417185377Ssam if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 418185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 419185380Ssam AR_RAD5424_SREV_MAJOR | 0x2; 420185377Ssam break; 421185377Ssam } 422185377Ssam } 423185377Ssam#ifdef AH_DEBUG 424185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 425185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 426185377Ssam "this driver\n", 427185377Ssam __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 428185377Ssam ecode = HAL_ENOTSUPP; 429185377Ssam goto bad; 430185377Ssam#endif 431185377Ssam } 432185380Ssam if (IS_RAD5112_REV1(ah)) { 433185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 434185377Ssam "%s: 5112 Rev 1 is not supported by this " 435185377Ssam "driver (analog5GhzRev 0x%x)\n", __func__, 436185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 437185377Ssam ecode = HAL_ENOTSUPP; 438185377Ssam goto bad; 439185377Ssam } 440185377Ssam 441185377Ssam val = OS_REG_READ(ah, AR_PCICFG); 442185377Ssam val = MS(val, AR_PCICFG_EEPROM_SIZE); 443185377Ssam if (val == 0) { 444188979Ssam if (!AH_PRIVATE(ah)->ah_ispcie) { 445185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 446185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 447185377Ssam __func__, val, val); 448185377Ssam ecode = HAL_EESIZE; 449185377Ssam goto bad; 450185377Ssam } 451185377Ssam /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 452185377Ssam } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 453185377Ssam if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 454185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 455185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 456185377Ssam __func__, val, val); 457185377Ssam ecode = HAL_EESIZE; 458185377Ssam goto bad; 459185377Ssam } 460185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 461185377Ssam "%s: EEPROM size = %d. Must be %d (16k).\n", 462185377Ssam __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 463185377Ssam ecode = HAL_EESIZE; 464185377Ssam goto bad; 465185377Ssam } 466185377Ssam ecode = ath_hal_legacyEepromAttach(ah); 467185377Ssam if (ecode != HAL_OK) { 468185377Ssam goto bad; 469185377Ssam } 470185377Ssam ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 471185377Ssam 472185377Ssam /* 473185377Ssam * If Bmode and AR5212, verify 2.4 analog exists 474185377Ssam */ 475185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 476185377Ssam (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 477185377Ssam /* 478185377Ssam * Set correct Baseband to analog shift 479185377Ssam * setting to access analog chips. 480185377Ssam */ 481185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 482185377Ssam OS_DELAY(2000); 483185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 484185377Ssam 485185377Ssam /* Set baseband for 5GHz chip */ 486185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 487185377Ssam OS_DELAY(2000); 488185377Ssam if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 489185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 490185377Ssam "%s: 2G Radio Chip Rev 0x%02X is not " 491185377Ssam "supported by this driver\n", __func__, 492185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev); 493185377Ssam ecode = HAL_ENOTSUPP; 494185377Ssam goto bad; 495185377Ssam } 496185377Ssam } 497185377Ssam 498185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 499185377Ssam if (ecode != HAL_OK) { 500185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 501185377Ssam "%s: cannot read regulatory domain from EEPROM\n", 502185377Ssam __func__); 503185377Ssam goto bad; 504185377Ssam } 505185377Ssam AH_PRIVATE(ah)->ah_currentRD = eeval; 506185377Ssam /* XXX record serial number */ 507185377Ssam 508185377Ssam /* 509185377Ssam * Got everything we need now to setup the capabilities. 510185377Ssam */ 511185377Ssam if (!ar5212FillCapabilityInfo(ah)) { 512185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 513185377Ssam "%s: failed ar5212FillCapabilityInfo\n", __func__); 514185377Ssam ecode = HAL_EEREAD; 515185377Ssam goto bad; 516185377Ssam } 517185377Ssam 518185406Ssam if (!rf->attach(ah, &ecode)) { 519185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 520185377Ssam __func__, ecode); 521185377Ssam goto bad; 522185377Ssam } 523185377Ssam /* 524185377Ssam * Set noise floor adjust method; we arrange a 525185377Ssam * direct call instead of thunking. 526185377Ssam */ 527185377Ssam AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 528185377Ssam 529185377Ssam /* Initialize gain ladder thermal calibration structure */ 530185377Ssam ar5212InitializeGainValues(ah); 531185377Ssam 532185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 533185377Ssam if (ecode != HAL_OK) { 534185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 535185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 536185377Ssam goto bad; 537185377Ssam } 538185377Ssam 539185377Ssam ar5212AniSetup(ah); 540185377Ssam /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 541185377Ssam ar5212InitNfCalHistBuffer(ah); 542185377Ssam 543185377Ssam /* XXX EAR stuff goes here */ 544185377Ssam 545185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 546185377Ssam 547185377Ssam return ah; 548185377Ssam 549185377Ssambad: 550185377Ssam if (ahp) 551185377Ssam ar5212Detach((struct ath_hal *) ahp); 552185377Ssam if (status) 553185377Ssam *status = ecode; 554185377Ssam return AH_NULL; 555185377Ssam#undef AH_EEPROM_PROTECT 556185377Ssam} 557185377Ssam 558185377Ssamvoid 559185377Ssamar5212Detach(struct ath_hal *ah) 560185377Ssam{ 561185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 562185377Ssam 563185377Ssam HALASSERT(ah != AH_NULL); 564185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 565185377Ssam 566185377Ssam ar5212AniDetach(ah); 567185377Ssam ar5212RfDetach(ah); 568185377Ssam ar5212Disable(ah); 569185377Ssam ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 570185377Ssam 571185377Ssam ath_hal_eepromDetach(ah); 572185377Ssam ath_hal_free(ah); 573185377Ssam} 574185377Ssam 575185377SsamHAL_BOOL 576185377Ssamar5212ChipTest(struct ath_hal *ah) 577185377Ssam{ 578185377Ssam uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 579185377Ssam uint32_t regHold[2]; 580185377Ssam uint32_t patternData[4] = 581185377Ssam { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 582185377Ssam int i, j; 583185377Ssam 584185377Ssam /* Test PHY & MAC registers */ 585185377Ssam for (i = 0; i < 2; i++) { 586185377Ssam uint32_t addr = regAddr[i]; 587185377Ssam uint32_t wrData, rdData; 588185377Ssam 589185377Ssam regHold[i] = OS_REG_READ(ah, addr); 590185377Ssam for (j = 0; j < 0x100; j++) { 591185377Ssam wrData = (j << 16) | j; 592185377Ssam OS_REG_WRITE(ah, addr, wrData); 593185377Ssam rdData = OS_REG_READ(ah, addr); 594185377Ssam if (rdData != wrData) { 595185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 596185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 597185377Ssam __func__, addr, wrData, rdData); 598185377Ssam return AH_FALSE; 599185377Ssam } 600185377Ssam } 601185377Ssam for (j = 0; j < 4; j++) { 602185377Ssam wrData = patternData[j]; 603185377Ssam OS_REG_WRITE(ah, addr, wrData); 604185377Ssam rdData = OS_REG_READ(ah, addr); 605185377Ssam if (wrData != rdData) { 606185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 607185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 608185377Ssam __func__, addr, wrData, rdData); 609185377Ssam return AH_FALSE; 610185377Ssam } 611185377Ssam } 612185377Ssam OS_REG_WRITE(ah, regAddr[i], regHold[i]); 613185377Ssam } 614185377Ssam OS_DELAY(100); 615185377Ssam return AH_TRUE; 616185377Ssam} 617185377Ssam 618185377Ssam/* 619185377Ssam * Store the channel edges for the requested operational mode 620185377Ssam */ 621185377SsamHAL_BOOL 622185377Ssamar5212GetChannelEdges(struct ath_hal *ah, 623185377Ssam uint16_t flags, uint16_t *low, uint16_t *high) 624185377Ssam{ 625187831Ssam if (flags & IEEE80211_CHAN_5GHZ) { 626185377Ssam *low = 4915; 627185377Ssam *high = 6100; 628185377Ssam return AH_TRUE; 629185377Ssam } 630187831Ssam if ((flags & IEEE80211_CHAN_2GHZ) && 631185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 632185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 633185377Ssam *low = 2312; 634185377Ssam *high = 2732; 635185377Ssam return AH_TRUE; 636185377Ssam } 637185377Ssam return AH_FALSE; 638185377Ssam} 639185377Ssam 640185377Ssam/* 641188979Ssam * Disable PLL when in L0s as well as receiver clock when in L1. 642188979Ssam * This power saving option must be enabled through the Serdes. 643188979Ssam * 644188979Ssam * Programming the Serdes must go through the same 288 bit serial shift 645188979Ssam * register as the other analog registers. Hence the 9 writes. 646188979Ssam * 647188979Ssam * XXX Clean up the magic numbers. 648188979Ssam */ 649188979Ssamstatic void 650188979Ssamar5212ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 651188979Ssam{ 652188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 653188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 654188979Ssam 655188979Ssam /* RX shut off when elecidle is asserted */ 656188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 657188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 658188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 659188979Ssam 660188979Ssam /* Shut off PLL and CLKREQ active in L1 */ 661188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 662188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 663188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 664188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 665188979Ssam 666188979Ssam /* Load the new settings */ 667188979Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 668188979Ssam} 669188979Ssam 670188979Ssamstatic void 671188979Ssamar5212DisablePCIE(struct ath_hal *ah) 672188979Ssam{ 673188979Ssam /* NB: fill in for 9100 */ 674188979Ssam} 675188979Ssam 676188979Ssam/* 677185377Ssam * Fill all software cached or static hardware state information. 678185377Ssam * Return failure if capabilities are to come from EEPROM and 679185377Ssam * cannot be read. 680185377Ssam */ 681185377SsamHAL_BOOL 682185377Ssamar5212FillCapabilityInfo(struct ath_hal *ah) 683185377Ssam{ 684185377Ssam#define AR_KEYTABLE_SIZE 128 685185377Ssam#define IS_GRIFFIN_LITE(ah) \ 686185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 687185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 688185377Ssam#define IS_COBRA(ah) \ 689185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 690185377Ssam#define IS_2112(ah) \ 691185377Ssam ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 692185377Ssam 693185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 694185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 695185377Ssam uint16_t capField, val; 696185377Ssam 697185377Ssam /* Read the capability EEPROM location */ 698185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 699185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 700185377Ssam "%s: unable to read caps from eeprom\n", __func__); 701185377Ssam return AH_FALSE; 702185377Ssam } 703185377Ssam if (IS_2112(ah)) 704185377Ssam ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 705185377Ssam if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 706185377Ssam /* 707185377Ssam * For griffin-lite cards with unprogrammed capabilities. 708185377Ssam */ 709185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 710185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 711185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 712185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 713185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 714185377Ssam "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 715185377Ssam __func__, capField); 716185377Ssam } 717185377Ssam 718185377Ssam /* Modify reg domain on newer cards that need to work with older sw */ 719185377Ssam if (ahpriv->ah_opmode != HAL_M_HOSTAP && 720185377Ssam ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 721185377Ssam if (ahpriv->ah_currentRD == 0x64 || 722185377Ssam ahpriv->ah_currentRD == 0x65) 723185377Ssam ahpriv->ah_currentRD += 5; 724185377Ssam else if (ahpriv->ah_currentRD == 0x41) 725185377Ssam ahpriv->ah_currentRD = 0x43; 726185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 727185377Ssam __func__, ahpriv->ah_currentRD); 728185377Ssam } 729185377Ssam 730185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 731185377Ssam AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 732185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 733185377Ssam "%s: enable Bmode and disable turbo for Swan/Nala\n", 734185377Ssam __func__); 735185377Ssam ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 736185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 737185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 738185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 739185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 740185377Ssam } 741185377Ssam 742185377Ssam /* Construct wireless mode from EEPROM */ 743185377Ssam pCap->halWirelessModes = 0; 744185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 745185377Ssam pCap->halWirelessModes |= HAL_MODE_11A; 746185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 747185377Ssam pCap->halWirelessModes |= HAL_MODE_TURBO; 748185377Ssam } 749185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 750185377Ssam pCap->halWirelessModes |= HAL_MODE_11B; 751185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 752185377Ssam ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 753185377Ssam pCap->halWirelessModes |= HAL_MODE_11G; 754185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 755185377Ssam pCap->halWirelessModes |= HAL_MODE_108G; 756185377Ssam } 757185377Ssam 758185377Ssam pCap->halLow2GhzChan = 2312; 759185380Ssam /* XXX 2417 too? */ 760185380Ssam if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 761185377Ssam pCap->halHigh2GhzChan = 2500; 762185377Ssam else 763185377Ssam pCap->halHigh2GhzChan = 2732; 764185377Ssam 765185377Ssam pCap->halLow5GhzChan = 4915; 766185377Ssam pCap->halHigh5GhzChan = 6100; 767185377Ssam 768185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 769185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 770185377Ssam pCap->halCipherAesCcmSupport = 771185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 772185377Ssam ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 773185377Ssam ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 774185377Ssam (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 775185377Ssam 776185377Ssam pCap->halMicCkipSupport = AH_FALSE; 777185377Ssam pCap->halMicTkipSupport = AH_TRUE; 778185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 779185377Ssam /* 780185377Ssam * Starting with Griffin TX+RX mic keys can be combined 781185377Ssam * in one key cache slot. 782185377Ssam */ 783185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 784185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 785185377Ssam else 786185377Ssam pCap->halTkipMicTxRxKeySupport = AH_FALSE; 787185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 788185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 789185377Ssam 790185377Ssam if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 791185377Ssam pCap->halCompressSupport = 792185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 793185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 794185377Ssam pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 795185377Ssam pCap->halFastFramesSupport = 796185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 797185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 798185377Ssam pCap->halChapTuningSupport = AH_TRUE; 799185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 800185377Ssam } 801185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 802185377Ssam 803185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 804185377Ssam pCap->halVEOLSupport = AH_TRUE; 805185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 806185377Ssam pCap->halMcastKeySrchSupport = AH_TRUE; 807185377Ssam if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 808185377Ssam ahpriv->ah_macRev == 8) || 809185377Ssam ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 810185377Ssam pCap->halTsfAddSupport = AH_TRUE; 811185377Ssam 812185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 813185377Ssam pCap->halTotalQueues = val; 814185377Ssam else 815185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 816185377Ssam 817185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 818185377Ssam pCap->halKeyCacheSize = val; 819185377Ssam else 820185377Ssam pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 821185377Ssam 822185380Ssam pCap->halChanHalfRate = AH_TRUE; 823185380Ssam pCap->halChanQuarterRate = AH_TRUE; 824185377Ssam 825185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 826185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 827185377Ssam /* NB: enabled by default */ 828185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 829185377Ssam pCap->halRfSilentSupport = AH_TRUE; 830185377Ssam } 831185377Ssam 832185377Ssam /* NB: this is a guess, noone seems to know the answer */ 833185377Ssam ahpriv->ah_rxornIsFatal = 834185377Ssam (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 835185377Ssam 836195114Ssam /* enable features that first appeared in Hainan */ 837195114Ssam if ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 838185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 839195114Ssam AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) { 840195114Ssam /* h/w phy counters */ 841195114Ssam pCap->halHwPhyCounterSupport = AH_TRUE; 842195114Ssam /* bssid match disable */ 843195114Ssam pCap->halBssidMatchSupport = AH_TRUE; 844195114Ssam } 845185377Ssam 846185377Ssam pCap->halTstampPrecision = 15; 847192396Ssam pCap->halIntrMask = HAL_INT_COMMON 848192396Ssam | HAL_INT_RX 849192396Ssam | HAL_INT_TX 850192396Ssam | HAL_INT_FATAL 851192396Ssam | HAL_INT_BNR 852192396Ssam | HAL_INT_BMISC 853192396Ssam ; 854192400Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) 855192400Ssam pCap->halIntrMask &= ~HAL_INT_TBTT; 856185377Ssam 857185377Ssam return AH_TRUE; 858185377Ssam#undef IS_COBRA 859185377Ssam#undef IS_GRIFFIN_LITE 860185377Ssam#undef AR_KEYTABLE_SIZE 861185377Ssam} 862185406Ssam 863185406Ssamstatic const char* 864185406Ssamar5212Probe(uint16_t vendorid, uint16_t devid) 865185406Ssam{ 866185406Ssam if (vendorid == ATHEROS_VENDOR_ID || 867185406Ssam vendorid == ATHEROS_3COM_VENDOR_ID || 868185406Ssam vendorid == ATHEROS_3COM2_VENDOR_ID) { 869185406Ssam switch (devid) { 870185406Ssam case AR5212_FPGA: 871185406Ssam return "Atheros 5212 (FPGA)"; 872185406Ssam case AR5212_DEVID: 873185406Ssam case AR5212_DEVID_IBM: 874185406Ssam case AR5212_DEFAULT: 875185406Ssam return "Atheros 5212"; 876185406Ssam case AR5212_AR2413: 877185406Ssam return "Atheros 2413"; 878185406Ssam case AR5212_AR2417: 879185406Ssam return "Atheros 2417"; 880185406Ssam case AR5212_AR5413: 881185406Ssam return "Atheros 5413"; 882185406Ssam case AR5212_AR5424: 883185406Ssam return "Atheros 5424/2424"; 884185406Ssam } 885185406Ssam } 886185406Ssam return AH_NULL; 887185406Ssam} 888185418SsamAH_CHIP(AR5212, ar5212Probe, ar5212Attach); 889