ar5212_attach.c revision 185406
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17185380Ssam * $Id: ar5212_attach.c,v 1.18 2008/11/19 22:10:42 sam Exp $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#include "ah.h" 22185377Ssam#include "ah_internal.h" 23185377Ssam#include "ah_devid.h" 24185377Ssam 25185377Ssam#include "ar5212/ar5212.h" 26185377Ssam#include "ar5212/ar5212reg.h" 27185377Ssam#include "ar5212/ar5212phy.h" 28185377Ssam 29185377Ssam#define AH_5212_COMMON 30185377Ssam#include "ar5212/ar5212.ini" 31185377Ssam 32185377Ssamstatic const struct ath_hal_private ar5212hal = {{ 33185377Ssam .ah_magic = AR5212_MAGIC, 34185377Ssam .ah_abi = HAL_ABI_VERSION, 35185377Ssam .ah_countryCode = CTRY_DEFAULT, 36185377Ssam 37185377Ssam .ah_getRateTable = ar5212GetRateTable, 38185377Ssam .ah_detach = ar5212Detach, 39185377Ssam 40185377Ssam /* Reset Functions */ 41185377Ssam .ah_reset = ar5212Reset, 42185377Ssam .ah_phyDisable = ar5212PhyDisable, 43185377Ssam .ah_disable = ar5212Disable, 44185377Ssam .ah_setPCUConfig = ar5212SetPCUConfig, 45185377Ssam .ah_perCalibration = ar5212PerCalibration, 46185380Ssam .ah_perCalibrationN = ar5212PerCalibrationN, 47185380Ssam .ah_resetCalValid = ar5212ResetCalValid, 48185377Ssam .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 49185377Ssam .ah_getChanNoise = ath_hal_getChanNoise, 50185377Ssam 51185377Ssam /* Transmit functions */ 52185377Ssam .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 53185377Ssam .ah_setupTxQueue = ar5212SetupTxQueue, 54185377Ssam .ah_setTxQueueProps = ar5212SetTxQueueProps, 55185377Ssam .ah_getTxQueueProps = ar5212GetTxQueueProps, 56185377Ssam .ah_releaseTxQueue = ar5212ReleaseTxQueue, 57185377Ssam .ah_resetTxQueue = ar5212ResetTxQueue, 58185377Ssam .ah_getTxDP = ar5212GetTxDP, 59185377Ssam .ah_setTxDP = ar5212SetTxDP, 60185377Ssam .ah_numTxPending = ar5212NumTxPending, 61185377Ssam .ah_startTxDma = ar5212StartTxDma, 62185377Ssam .ah_stopTxDma = ar5212StopTxDma, 63185377Ssam .ah_setupTxDesc = ar5212SetupTxDesc, 64185377Ssam .ah_setupXTxDesc = ar5212SetupXTxDesc, 65185377Ssam .ah_fillTxDesc = ar5212FillTxDesc, 66185377Ssam .ah_procTxDesc = ar5212ProcTxDesc, 67185377Ssam .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 68185377Ssam .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 69185377Ssam 70185377Ssam /* RX Functions */ 71185377Ssam .ah_getRxDP = ar5212GetRxDP, 72185377Ssam .ah_setRxDP = ar5212SetRxDP, 73185377Ssam .ah_enableReceive = ar5212EnableReceive, 74185377Ssam .ah_stopDmaReceive = ar5212StopDmaReceive, 75185377Ssam .ah_startPcuReceive = ar5212StartPcuReceive, 76185377Ssam .ah_stopPcuReceive = ar5212StopPcuReceive, 77185377Ssam .ah_setMulticastFilter = ar5212SetMulticastFilter, 78185377Ssam .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 79185377Ssam .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 80185377Ssam .ah_getRxFilter = ar5212GetRxFilter, 81185377Ssam .ah_setRxFilter = ar5212SetRxFilter, 82185377Ssam .ah_setupRxDesc = ar5212SetupRxDesc, 83185377Ssam .ah_procRxDesc = ar5212ProcRxDesc, 84185377Ssam .ah_rxMonitor = ar5212AniPoll, 85185377Ssam .ah_procMibEvent = ar5212ProcessMibIntr, 86185377Ssam 87185377Ssam /* Misc Functions */ 88185377Ssam .ah_getCapability = ar5212GetCapability, 89185377Ssam .ah_setCapability = ar5212SetCapability, 90185377Ssam .ah_getDiagState = ar5212GetDiagState, 91185377Ssam .ah_getMacAddress = ar5212GetMacAddress, 92185377Ssam .ah_setMacAddress = ar5212SetMacAddress, 93185377Ssam .ah_getBssIdMask = ar5212GetBssIdMask, 94185377Ssam .ah_setBssIdMask = ar5212SetBssIdMask, 95185380Ssam .ah_setRegulatoryDomain = ar5212SetRegulatoryDomain, 96185377Ssam .ah_setLedState = ar5212SetLedState, 97185377Ssam .ah_writeAssocid = ar5212WriteAssocid, 98185377Ssam .ah_gpioCfgInput = ar5212GpioCfgInput, 99185377Ssam .ah_gpioCfgOutput = ar5212GpioCfgOutput, 100185377Ssam .ah_gpioGet = ar5212GpioGet, 101185377Ssam .ah_gpioSet = ar5212GpioSet, 102185377Ssam .ah_gpioSetIntr = ar5212GpioSetIntr, 103185377Ssam .ah_getTsf32 = ar5212GetTsf32, 104185377Ssam .ah_getTsf64 = ar5212GetTsf64, 105185377Ssam .ah_resetTsf = ar5212ResetTsf, 106185377Ssam .ah_detectCardPresent = ar5212DetectCardPresent, 107185377Ssam .ah_updateMibCounters = ar5212UpdateMibCounters, 108185377Ssam .ah_getRfGain = ar5212GetRfgain, 109185377Ssam .ah_getDefAntenna = ar5212GetDefAntenna, 110185377Ssam .ah_setDefAntenna = ar5212SetDefAntenna, 111185377Ssam .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 112185377Ssam .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 113185377Ssam .ah_setSifsTime = ar5212SetSifsTime, 114185377Ssam .ah_getSifsTime = ar5212GetSifsTime, 115185377Ssam .ah_setSlotTime = ar5212SetSlotTime, 116185377Ssam .ah_getSlotTime = ar5212GetSlotTime, 117185377Ssam .ah_setAckTimeout = ar5212SetAckTimeout, 118185377Ssam .ah_getAckTimeout = ar5212GetAckTimeout, 119185377Ssam .ah_setAckCTSRate = ar5212SetAckCTSRate, 120185377Ssam .ah_getAckCTSRate = ar5212GetAckCTSRate, 121185377Ssam .ah_setCTSTimeout = ar5212SetCTSTimeout, 122185377Ssam .ah_getCTSTimeout = ar5212GetCTSTimeout, 123185377Ssam .ah_setDecompMask = ar5212SetDecompMask, 124185377Ssam .ah_setCoverageClass = ar5212SetCoverageClass, 125185377Ssam 126185377Ssam /* Key Cache Functions */ 127185377Ssam .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 128185377Ssam .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 129185377Ssam .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 130185377Ssam .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 131185377Ssam .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 132185377Ssam 133185377Ssam /* Power Management Functions */ 134185377Ssam .ah_setPowerMode = ar5212SetPowerMode, 135185377Ssam .ah_getPowerMode = ar5212GetPowerMode, 136185377Ssam 137185377Ssam /* Beacon Functions */ 138185377Ssam .ah_setBeaconTimers = ar5212SetBeaconTimers, 139185377Ssam .ah_beaconInit = ar5212BeaconInit, 140185377Ssam .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 141185377Ssam .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 142185377Ssam 143185377Ssam /* Interrupt Functions */ 144185377Ssam .ah_isInterruptPending = ar5212IsInterruptPending, 145185377Ssam .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 146185377Ssam .ah_getInterrupts = ar5212GetInterrupts, 147185377Ssam .ah_setInterrupts = ar5212SetInterrupts }, 148185377Ssam 149185377Ssam .ah_getChannelEdges = ar5212GetChannelEdges, 150185377Ssam .ah_getWirelessModes = ar5212GetWirelessModes, 151185377Ssam .ah_eepromRead = ar5212EepromRead, 152185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 153185377Ssam .ah_eepromWrite = ar5212EepromWrite, 154185377Ssam#endif 155185377Ssam .ah_gpioCfgOutput = ar5212GpioCfgOutput, 156185377Ssam .ah_gpioCfgInput = ar5212GpioCfgInput, 157185377Ssam .ah_gpioGet = ar5212GpioGet, 158185377Ssam .ah_gpioSet = ar5212GpioSet, 159185377Ssam .ah_gpioSetIntr = ar5212GpioSetIntr, 160185377Ssam .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 161185377Ssam}; 162185377Ssam 163185377Ssam/* 164185377Ssam * Disable PLL when in L0s as well as receiver clock when in L1. 165185377Ssam * This power saving option must be enabled through the Serdes. 166185377Ssam * 167185377Ssam * Programming the Serdes must go through the same 288 bit serial shift 168185377Ssam * register as the other analog registers. Hence the 9 writes. 169185377Ssam * 170185377Ssam * XXX Clean up the magic numbers. 171185377Ssam */ 172185377Ssamstatic void 173185377SsamconfigurePciePowerSave(struct ath_hal *ah) 174185377Ssam{ 175185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 176185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 177185377Ssam 178185377Ssam /* RX shut off when elecidle is asserted */ 179185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 180185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 181185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 182185377Ssam 183185377Ssam /* Shut off PLL and CLKREQ active in L1 */ 184185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 185185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 186185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 187185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 188185377Ssam 189185377Ssam /* Load the new settings */ 190185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 191185377Ssam} 192185377Ssam 193185377Ssamuint32_t 194185377Ssamar5212GetRadioRev(struct ath_hal *ah) 195185377Ssam{ 196185377Ssam uint32_t val; 197185377Ssam int i; 198185377Ssam 199185377Ssam /* Read Radio Chip Rev Extract */ 200185377Ssam OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 201185377Ssam for (i = 0; i < 8; i++) 202185377Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 203185377Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 204185377Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 205185377Ssam return ath_hal_reverseBits(val, 8); 206185377Ssam} 207185377Ssam 208185377Ssamstatic void 209185377Ssamar5212AniSetup(struct ath_hal *ah) 210185377Ssam{ 211185377Ssam static const struct ar5212AniParams aniparams = { 212185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 213185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 214185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 215185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 216185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 217185377Ssam .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 218185377Ssam .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 219185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 220185377Ssam .firstep = { 0, 4, 8 }, 221185377Ssam .ofdmTrigHigh = 500, 222185377Ssam .ofdmTrigLow = 200, 223185377Ssam .cckTrigHigh = 200, 224185377Ssam .cckTrigLow = 100, 225185377Ssam .rssiThrHigh = 40, 226185377Ssam .rssiThrLow = 7, 227185377Ssam .period = 100, 228185377Ssam }; 229185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 230185377Ssam struct ar5212AniParams tmp; 231185377Ssam OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 232185377Ssam tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 233185377Ssam ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 234185377Ssam } else 235185377Ssam ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 236185377Ssam} 237185377Ssam 238185377Ssam/* 239185377Ssam * Attach for an AR5212 part. 240185377Ssam */ 241185377Ssamvoid 242185377Ssamar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 243185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 244185377Ssam{ 245185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 246185377Ssam static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 247185377Ssam { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 248185377Ssam struct ath_hal *ah; 249185377Ssam 250185377Ssam ah = &ahp->ah_priv.h; 251185377Ssam /* set initial values */ 252185377Ssam OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 253185377Ssam ah->ah_sc = sc; 254185377Ssam ah->ah_st = st; 255185377Ssam ah->ah_sh = sh; 256185377Ssam 257185377Ssam ah->ah_devid = devid; /* NB: for alq */ 258185377Ssam AH_PRIVATE(ah)->ah_devid = devid; 259185377Ssam AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 260185377Ssam 261185377Ssam AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 262185377Ssam AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 263185377Ssam 264185380Ssam ahp->ah_antControl = HAL_ANT_VARIABLE; 265185380Ssam ahp->ah_diversity = AH_TRUE; 266185377Ssam ahp->ah_bIQCalibration = AH_FALSE; 267185377Ssam /* 268185377Ssam * Enable MIC handling. 269185377Ssam */ 270185377Ssam ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 271185377Ssam ahp->ah_rssiThr = INIT_RSSI_THR; 272185377Ssam ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 273185380Ssam ahp->ah_phyPowerOn = AH_FALSE; 274185377Ssam ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 275185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CTS) 276185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 277185377Ssam ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 278185377Ssam ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 279185377Ssam ahp->ah_slottime = (u_int) -1; 280185377Ssam ahp->ah_acktimeout = (u_int) -1; 281185377Ssam ahp->ah_ctstimeout = (u_int) -1; 282185377Ssam ahp->ah_sifstime = (u_int) -1; 283185377Ssam OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 284185377Ssam#undef N 285185377Ssam} 286185377Ssam 287185377Ssam/* 288185377Ssam * Validate MAC version and revision. 289185377Ssam */ 290185377Ssamstatic HAL_BOOL 291185377Ssamar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 292185377Ssam{ 293185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 294185377Ssam static const struct { 295185377Ssam uint8_t version; 296185377Ssam uint8_t revMin, revMax; 297185377Ssam } macs[] = { 298185377Ssam { AR_SREV_VERSION_VENICE, 299185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 300185377Ssam { AR_SREV_VERSION_GRIFFIN, 301185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 302185377Ssam { AR_SREV_5413, 303185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 304185377Ssam { AR_SREV_5424, 305185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 306185377Ssam { AR_SREV_2425, 307185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 308185377Ssam { AR_SREV_2417, 309185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 310185377Ssam }; 311185377Ssam int i; 312185377Ssam 313185377Ssam for (i = 0; i < N(macs); i++) 314185377Ssam if (macs[i].version == macVersion && 315185377Ssam macs[i].revMin <= macRev && macRev <= macs[i].revMax) 316185377Ssam return AH_TRUE; 317185377Ssam return AH_FALSE; 318185377Ssam#undef N 319185377Ssam} 320185377Ssam 321185377Ssam/* 322185377Ssam * Attach for an AR5212 part. 323185377Ssam */ 324185406Ssamstatic struct ath_hal * 325185377Ssamar5212Attach(uint16_t devid, HAL_SOFTC sc, 326185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 327185377Ssam{ 328185377Ssam#define AH_EEPROM_PROTECT(ah) \ 329185377Ssam (IS_PCIE(ah) ? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 330185377Ssam struct ath_hal_5212 *ahp; 331185377Ssam struct ath_hal *ah; 332185406Ssam struct ath_hal_rf *rf; 333185377Ssam uint32_t val; 334185377Ssam uint16_t eeval; 335185377Ssam HAL_STATUS ecode; 336185377Ssam 337185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 338185377Ssam __func__, sc, (void*) st, (void*) sh); 339185377Ssam 340185377Ssam /* NB: memory is returned zero'd */ 341185377Ssam ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 342185377Ssam if (ahp == AH_NULL) { 343185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 344185377Ssam "%s: cannot allocate memory for state block\n", __func__); 345185377Ssam *status = HAL_ENOMEM; 346185377Ssam return AH_NULL; 347185377Ssam } 348185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 349185377Ssam ah = &ahp->ah_priv.h; 350185377Ssam 351185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 352185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 353185377Ssam __func__); 354185377Ssam ecode = HAL_EIO; 355185377Ssam goto bad; 356185377Ssam } 357185377Ssam /* Read Revisions from Chips before taking out of reset */ 358185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 359185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 360185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 361185377Ssam 362185377Ssam if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 363185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 364185377Ssam "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 365185377Ssam __func__, AH_PRIVATE(ah)->ah_macVersion, 366185377Ssam AH_PRIVATE(ah)->ah_macRev); 367185377Ssam ecode = HAL_ENOTSUPP; 368185377Ssam goto bad; 369185377Ssam } 370185377Ssam 371185377Ssam /* setup common ini data; rf backends handle remainder */ 372185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 373185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 374185377Ssam 375185377Ssam if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 376185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 377185377Ssam ecode = HAL_EIO; 378185377Ssam goto bad; 379185377Ssam } 380185377Ssam 381185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 382185377Ssam 383185377Ssam if (IS_PCIE(ah)) { 384185377Ssam /* XXX: build flag to disable this? */ 385185377Ssam configurePciePowerSave(ah); 386185377Ssam } 387185377Ssam 388185377Ssam if (!ar5212ChipTest(ah)) { 389185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 390185377Ssam __func__); 391185377Ssam ecode = HAL_ESELFTEST; 392185377Ssam goto bad; 393185377Ssam } 394185377Ssam 395185377Ssam /* Enable PCI core retry fix in software for Hainan and up */ 396185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 397185377Ssam OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 398185377Ssam 399185377Ssam /* 400185377Ssam * Set correct Baseband to analog shift 401185377Ssam * setting to access analog chips. 402185377Ssam */ 403185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 404185377Ssam 405185377Ssam /* Read Radio Chip Rev Extract */ 406185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 407185406Ssam 408185406Ssam rf = ath_hal_rfprobe(ah, &ecode); 409185406Ssam if (rf == AH_NULL) 410185406Ssam goto bad; 411185406Ssam 412185377Ssam /* NB: silently accept anything in release code per Atheros */ 413185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 414185377Ssam case AR_RAD5111_SREV_MAJOR: 415185377Ssam case AR_RAD5112_SREV_MAJOR: 416185377Ssam case AR_RAD2112_SREV_MAJOR: 417185377Ssam case AR_RAD2111_SREV_MAJOR: 418185377Ssam case AR_RAD2413_SREV_MAJOR: 419185377Ssam case AR_RAD5413_SREV_MAJOR: 420185377Ssam case AR_RAD5424_SREV_MAJOR: 421185377Ssam break; 422185377Ssam default: 423185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 424185377Ssam /* 425185377Ssam * When RF_Silent is used, the 426185377Ssam * analog chip is reset. So when the system boots 427185377Ssam * up with the radio switch off we cannot determine 428185377Ssam * the RF chip rev. To workaround this check the 429185377Ssam * mac+phy revs and if Hainan, set the radio rev 430185377Ssam * to Derby. 431185377Ssam */ 432185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 433185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 434185377Ssam AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 435185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 436185377Ssam break; 437185377Ssam } 438185377Ssam if (IS_2413(ah)) { /* Griffin */ 439185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 440185380Ssam AR_RAD2413_SREV_MAJOR | 0x1; 441185377Ssam break; 442185377Ssam } 443185377Ssam if (IS_5413(ah)) { /* Eagle */ 444185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 445185380Ssam AR_RAD5413_SREV_MAJOR | 0x2; 446185377Ssam break; 447185377Ssam } 448185377Ssam if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 449185380Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 450185380Ssam AR_RAD5424_SREV_MAJOR | 0x2; 451185377Ssam break; 452185377Ssam } 453185377Ssam } 454185377Ssam#ifdef AH_DEBUG 455185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 456185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 457185377Ssam "this driver\n", 458185377Ssam __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 459185377Ssam ecode = HAL_ENOTSUPP; 460185377Ssam goto bad; 461185377Ssam#endif 462185377Ssam } 463185380Ssam if (IS_RAD5112_REV1(ah)) { 464185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 465185377Ssam "%s: 5112 Rev 1 is not supported by this " 466185377Ssam "driver (analog5GhzRev 0x%x)\n", __func__, 467185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 468185377Ssam ecode = HAL_ENOTSUPP; 469185377Ssam goto bad; 470185377Ssam } 471185377Ssam 472185377Ssam val = OS_REG_READ(ah, AR_PCICFG); 473185377Ssam val = MS(val, AR_PCICFG_EEPROM_SIZE); 474185377Ssam if (val == 0) { 475185377Ssam if (!IS_PCIE(ah)) { 476185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 477185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 478185377Ssam __func__, val, val); 479185377Ssam ecode = HAL_EESIZE; 480185377Ssam goto bad; 481185377Ssam } 482185377Ssam /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 483185377Ssam } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 484185377Ssam if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 485185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 486185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 487185377Ssam __func__, val, val); 488185377Ssam ecode = HAL_EESIZE; 489185377Ssam goto bad; 490185377Ssam } 491185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 492185377Ssam "%s: EEPROM size = %d. Must be %d (16k).\n", 493185377Ssam __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 494185377Ssam ecode = HAL_EESIZE; 495185377Ssam goto bad; 496185377Ssam } 497185377Ssam ecode = ath_hal_legacyEepromAttach(ah); 498185377Ssam if (ecode != HAL_OK) { 499185377Ssam goto bad; 500185377Ssam } 501185377Ssam ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 502185377Ssam 503185377Ssam /* 504185377Ssam * If Bmode and AR5212, verify 2.4 analog exists 505185377Ssam */ 506185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 507185377Ssam (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 508185377Ssam /* 509185377Ssam * Set correct Baseband to analog shift 510185377Ssam * setting to access analog chips. 511185377Ssam */ 512185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 513185377Ssam OS_DELAY(2000); 514185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 515185377Ssam 516185377Ssam /* Set baseband for 5GHz chip */ 517185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 518185377Ssam OS_DELAY(2000); 519185377Ssam if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 520185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 521185377Ssam "%s: 2G Radio Chip Rev 0x%02X is not " 522185377Ssam "supported by this driver\n", __func__, 523185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev); 524185377Ssam ecode = HAL_ENOTSUPP; 525185377Ssam goto bad; 526185377Ssam } 527185377Ssam } 528185377Ssam 529185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 530185377Ssam if (ecode != HAL_OK) { 531185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 532185377Ssam "%s: cannot read regulatory domain from EEPROM\n", 533185377Ssam __func__); 534185377Ssam goto bad; 535185377Ssam } 536185377Ssam AH_PRIVATE(ah)->ah_currentRD = eeval; 537185377Ssam /* XXX record serial number */ 538185377Ssam 539185377Ssam /* 540185377Ssam * Got everything we need now to setup the capabilities. 541185377Ssam */ 542185377Ssam if (!ar5212FillCapabilityInfo(ah)) { 543185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 544185377Ssam "%s: failed ar5212FillCapabilityInfo\n", __func__); 545185377Ssam ecode = HAL_EEREAD; 546185377Ssam goto bad; 547185377Ssam } 548185377Ssam 549185406Ssam if (!rf->attach(ah, &ecode)) { 550185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 551185377Ssam __func__, ecode); 552185377Ssam goto bad; 553185377Ssam } 554185377Ssam /* 555185377Ssam * Set noise floor adjust method; we arrange a 556185377Ssam * direct call instead of thunking. 557185377Ssam */ 558185377Ssam AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 559185377Ssam 560185377Ssam /* Initialize gain ladder thermal calibration structure */ 561185377Ssam ar5212InitializeGainValues(ah); 562185377Ssam 563185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 564185377Ssam if (ecode != HAL_OK) { 565185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 566185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 567185377Ssam goto bad; 568185377Ssam } 569185377Ssam 570185377Ssam ar5212AniSetup(ah); 571185377Ssam /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 572185377Ssam ar5212InitNfCalHistBuffer(ah); 573185377Ssam 574185377Ssam /* XXX EAR stuff goes here */ 575185377Ssam 576185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 577185377Ssam 578185377Ssam return ah; 579185377Ssam 580185377Ssambad: 581185377Ssam if (ahp) 582185377Ssam ar5212Detach((struct ath_hal *) ahp); 583185377Ssam if (status) 584185377Ssam *status = ecode; 585185377Ssam return AH_NULL; 586185377Ssam#undef AH_EEPROM_PROTECT 587185377Ssam} 588185377Ssam 589185377Ssamvoid 590185377Ssamar5212Detach(struct ath_hal *ah) 591185377Ssam{ 592185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 593185377Ssam 594185377Ssam HALASSERT(ah != AH_NULL); 595185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 596185377Ssam 597185377Ssam ar5212AniDetach(ah); 598185377Ssam ar5212RfDetach(ah); 599185377Ssam ar5212Disable(ah); 600185377Ssam ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 601185377Ssam 602185377Ssam ath_hal_eepromDetach(ah); 603185377Ssam ath_hal_free(ah); 604185377Ssam} 605185377Ssam 606185377SsamHAL_BOOL 607185377Ssamar5212ChipTest(struct ath_hal *ah) 608185377Ssam{ 609185377Ssam uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 610185377Ssam uint32_t regHold[2]; 611185377Ssam uint32_t patternData[4] = 612185377Ssam { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 613185377Ssam int i, j; 614185377Ssam 615185377Ssam /* Test PHY & MAC registers */ 616185377Ssam for (i = 0; i < 2; i++) { 617185377Ssam uint32_t addr = regAddr[i]; 618185377Ssam uint32_t wrData, rdData; 619185377Ssam 620185377Ssam regHold[i] = OS_REG_READ(ah, addr); 621185377Ssam for (j = 0; j < 0x100; j++) { 622185377Ssam wrData = (j << 16) | j; 623185377Ssam OS_REG_WRITE(ah, addr, wrData); 624185377Ssam rdData = OS_REG_READ(ah, addr); 625185377Ssam if (rdData != wrData) { 626185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 627185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 628185377Ssam __func__, addr, wrData, rdData); 629185377Ssam return AH_FALSE; 630185377Ssam } 631185377Ssam } 632185377Ssam for (j = 0; j < 4; j++) { 633185377Ssam wrData = patternData[j]; 634185377Ssam OS_REG_WRITE(ah, addr, wrData); 635185377Ssam rdData = OS_REG_READ(ah, addr); 636185377Ssam if (wrData != rdData) { 637185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 638185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 639185377Ssam __func__, addr, wrData, rdData); 640185377Ssam return AH_FALSE; 641185377Ssam } 642185377Ssam } 643185377Ssam OS_REG_WRITE(ah, regAddr[i], regHold[i]); 644185377Ssam } 645185377Ssam OS_DELAY(100); 646185377Ssam return AH_TRUE; 647185377Ssam} 648185377Ssam 649185377Ssam/* 650185377Ssam * Store the channel edges for the requested operational mode 651185377Ssam */ 652185377SsamHAL_BOOL 653185377Ssamar5212GetChannelEdges(struct ath_hal *ah, 654185377Ssam uint16_t flags, uint16_t *low, uint16_t *high) 655185377Ssam{ 656185377Ssam if (flags & CHANNEL_5GHZ) { 657185377Ssam *low = 4915; 658185377Ssam *high = 6100; 659185377Ssam return AH_TRUE; 660185377Ssam } 661185377Ssam if ((flags & CHANNEL_2GHZ) && 662185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 663185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 664185377Ssam *low = 2312; 665185377Ssam *high = 2732; 666185377Ssam return AH_TRUE; 667185377Ssam } 668185377Ssam return AH_FALSE; 669185377Ssam} 670185377Ssam 671185377Ssam/* 672185377Ssam * Fill all software cached or static hardware state information. 673185377Ssam * Return failure if capabilities are to come from EEPROM and 674185377Ssam * cannot be read. 675185377Ssam */ 676185377SsamHAL_BOOL 677185377Ssamar5212FillCapabilityInfo(struct ath_hal *ah) 678185377Ssam{ 679185377Ssam#define AR_KEYTABLE_SIZE 128 680185377Ssam#define IS_GRIFFIN_LITE(ah) \ 681185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 682185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 683185377Ssam#define IS_COBRA(ah) \ 684185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 685185377Ssam#define IS_2112(ah) \ 686185377Ssam ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 687185377Ssam 688185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 689185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 690185377Ssam uint16_t capField, val; 691185377Ssam 692185377Ssam /* Read the capability EEPROM location */ 693185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 694185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 695185377Ssam "%s: unable to read caps from eeprom\n", __func__); 696185377Ssam return AH_FALSE; 697185377Ssam } 698185377Ssam if (IS_2112(ah)) 699185377Ssam ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 700185377Ssam if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 701185377Ssam /* 702185377Ssam * For griffin-lite cards with unprogrammed capabilities. 703185377Ssam */ 704185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 705185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 706185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 707185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 708185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 709185377Ssam "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 710185377Ssam __func__, capField); 711185377Ssam } 712185377Ssam 713185377Ssam /* Modify reg domain on newer cards that need to work with older sw */ 714185377Ssam if (ahpriv->ah_opmode != HAL_M_HOSTAP && 715185377Ssam ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 716185377Ssam if (ahpriv->ah_currentRD == 0x64 || 717185377Ssam ahpriv->ah_currentRD == 0x65) 718185377Ssam ahpriv->ah_currentRD += 5; 719185377Ssam else if (ahpriv->ah_currentRD == 0x41) 720185377Ssam ahpriv->ah_currentRD = 0x43; 721185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 722185377Ssam __func__, ahpriv->ah_currentRD); 723185377Ssam } 724185377Ssam 725185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 726185377Ssam AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 727185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 728185377Ssam "%s: enable Bmode and disable turbo for Swan/Nala\n", 729185377Ssam __func__); 730185377Ssam ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 731185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 732185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 733185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 734185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 735185377Ssam } 736185377Ssam 737185377Ssam /* Construct wireless mode from EEPROM */ 738185377Ssam pCap->halWirelessModes = 0; 739185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 740185377Ssam pCap->halWirelessModes |= HAL_MODE_11A; 741185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 742185377Ssam pCap->halWirelessModes |= HAL_MODE_TURBO; 743185377Ssam } 744185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 745185377Ssam pCap->halWirelessModes |= HAL_MODE_11B; 746185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 747185377Ssam ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 748185377Ssam pCap->halWirelessModes |= HAL_MODE_11G; 749185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 750185377Ssam pCap->halWirelessModes |= HAL_MODE_108G; 751185377Ssam } 752185377Ssam 753185377Ssam pCap->halLow2GhzChan = 2312; 754185380Ssam /* XXX 2417 too? */ 755185380Ssam if (IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah)) 756185377Ssam pCap->halHigh2GhzChan = 2500; 757185377Ssam else 758185377Ssam pCap->halHigh2GhzChan = 2732; 759185377Ssam 760185377Ssam pCap->halLow5GhzChan = 4915; 761185377Ssam pCap->halHigh5GhzChan = 6100; 762185377Ssam 763185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 764185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 765185377Ssam pCap->halCipherAesCcmSupport = 766185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 767185377Ssam ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 768185377Ssam ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 769185377Ssam (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 770185377Ssam 771185377Ssam pCap->halMicCkipSupport = AH_FALSE; 772185377Ssam pCap->halMicTkipSupport = AH_TRUE; 773185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 774185377Ssam /* 775185377Ssam * Starting with Griffin TX+RX mic keys can be combined 776185377Ssam * in one key cache slot. 777185377Ssam */ 778185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 779185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 780185377Ssam else 781185377Ssam pCap->halTkipMicTxRxKeySupport = AH_FALSE; 782185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 783185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 784185377Ssam 785185377Ssam if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 786185377Ssam pCap->halCompressSupport = 787185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 788185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 789185377Ssam pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 790185377Ssam pCap->halFastFramesSupport = 791185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 792185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 793185377Ssam pCap->halChapTuningSupport = AH_TRUE; 794185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 795185377Ssam } 796185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 797185377Ssam 798185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 799185377Ssam pCap->halVEOLSupport = AH_TRUE; 800185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 801185377Ssam pCap->halMcastKeySrchSupport = AH_TRUE; 802185377Ssam if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 803185377Ssam ahpriv->ah_macRev == 8) || 804185377Ssam ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 805185377Ssam pCap->halTsfAddSupport = AH_TRUE; 806185377Ssam 807185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 808185377Ssam pCap->halTotalQueues = val; 809185377Ssam else 810185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 811185377Ssam 812185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 813185377Ssam pCap->halKeyCacheSize = val; 814185377Ssam else 815185377Ssam pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 816185377Ssam 817185380Ssam pCap->halChanHalfRate = AH_TRUE; 818185380Ssam pCap->halChanQuarterRate = AH_TRUE; 819185377Ssam 820185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 821185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 822185377Ssam /* NB: enabled by default */ 823185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 824185377Ssam pCap->halRfSilentSupport = AH_TRUE; 825185377Ssam } 826185377Ssam 827185377Ssam /* NB: this is a guess, noone seems to know the answer */ 828185377Ssam ahpriv->ah_rxornIsFatal = 829185377Ssam (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 830185377Ssam 831185377Ssam /* h/w phy counters first appeared in Hainan */ 832185377Ssam pCap->halHwPhyCounterSupport = 833185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 834185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 835185377Ssam AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE; 836185377Ssam 837185377Ssam pCap->halTstampPrecision = 15; 838185377Ssam 839185377Ssam return AH_TRUE; 840185377Ssam#undef IS_COBRA 841185377Ssam#undef IS_GRIFFIN_LITE 842185377Ssam#undef AR_KEYTABLE_SIZE 843185377Ssam} 844185406Ssam 845185406Ssamstatic const char* 846185406Ssamar5212Probe(uint16_t vendorid, uint16_t devid) 847185406Ssam{ 848185406Ssam if (vendorid == ATHEROS_VENDOR_ID || 849185406Ssam vendorid == ATHEROS_3COM_VENDOR_ID || 850185406Ssam vendorid == ATHEROS_3COM2_VENDOR_ID) { 851185406Ssam switch (devid) { 852185406Ssam case AR5212_FPGA: 853185406Ssam return "Atheros 5212 (FPGA)"; 854185406Ssam case AR5212_DEVID: 855185406Ssam case AR5212_DEVID_IBM: 856185406Ssam case AR5212_DEFAULT: 857185406Ssam return "Atheros 5212"; 858185406Ssam case AR5212_AR2413: 859185406Ssam return "Atheros 2413"; 860185406Ssam case AR5212_AR2417: 861185406Ssam return "Atheros 2417"; 862185406Ssam case AR5212_AR5413: 863185406Ssam return "Atheros 5413"; 864185406Ssam case AR5212_AR5424: 865185406Ssam return "Atheros 5424/2424"; 866185406Ssam } 867185406Ssam } 868185406Ssam return AH_NULL; 869185406Ssam} 870185406SsamAH_CHIP(ar5212, ar5212Probe, ar5212Attach); 871