ar5212_attach.c revision 185377
1185377Ssam/* 2185377Ssam * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3185377Ssam * Copyright (c) 2002-2008 Atheros Communications, Inc. 4185377Ssam * 5185377Ssam * Permission to use, copy, modify, and/or distribute this software for any 6185377Ssam * purpose with or without fee is hereby granted, provided that the above 7185377Ssam * copyright notice and this permission notice appear in all copies. 8185377Ssam * 9185377Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10185377Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11185377Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12185377Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13185377Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14185377Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15185377Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16185377Ssam * 17185377Ssam * $Id: ar5212_attach.c,v 1.12 2008/11/10 04:08:03 sam Exp $ 18185377Ssam */ 19185377Ssam#include "opt_ah.h" 20185377Ssam 21185377Ssam#ifdef AH_SUPPORT_AR5212 22185377Ssam 23185377Ssam#if !defined(AH_SUPPORT_5112) && \ 24185377Ssam !defined(AH_SUPPORT_5111) && \ 25185377Ssam !defined(AH_SUPPORT_2413) && \ 26185377Ssam !defined(AH_SUPPORT_5413) && \ 27185377Ssam !defined(AH_SUPPORT_AR5312) 28185377Ssam#error "No 5212 RF support defined" 29185377Ssam#endif 30185377Ssam 31185377Ssam#include "ah.h" 32185377Ssam#include "ah_internal.h" 33185377Ssam#include "ah_devid.h" 34185377Ssam 35185377Ssam#include "ar5212/ar5212.h" 36185377Ssam#include "ar5212/ar5212reg.h" 37185377Ssam#include "ar5212/ar5212phy.h" 38185377Ssam#ifdef AH_SUPPORT_AR5311 39185377Ssam#include "ar5212/ar5311reg.h" 40185377Ssam#endif 41185377Ssam 42185377Ssam#define AH_5212_COMMON 43185377Ssam#include "ar5212/ar5212.ini" 44185377Ssam 45185377Ssamstatic const struct ath_hal_private ar5212hal = {{ 46185377Ssam .ah_magic = AR5212_MAGIC, 47185377Ssam .ah_abi = HAL_ABI_VERSION, 48185377Ssam .ah_countryCode = CTRY_DEFAULT, 49185377Ssam 50185377Ssam .ah_getRateTable = ar5212GetRateTable, 51185377Ssam .ah_detach = ar5212Detach, 52185377Ssam 53185377Ssam /* Reset Functions */ 54185377Ssam .ah_reset = ar5212Reset, 55185377Ssam .ah_phyDisable = ar5212PhyDisable, 56185377Ssam .ah_disable = ar5212Disable, 57185377Ssam .ah_setPCUConfig = ar5212SetPCUConfig, 58185377Ssam .ah_perCalibration = ar5212PerCalibration, 59185377Ssam .ah_setTxPowerLimit = ar5212SetTxPowerLimit, 60185377Ssam .ah_getChanNoise = ath_hal_getChanNoise, 61185377Ssam 62185377Ssam /* Transmit functions */ 63185377Ssam .ah_updateTxTrigLevel = ar5212UpdateTxTrigLevel, 64185377Ssam .ah_setupTxQueue = ar5212SetupTxQueue, 65185377Ssam .ah_setTxQueueProps = ar5212SetTxQueueProps, 66185377Ssam .ah_getTxQueueProps = ar5212GetTxQueueProps, 67185377Ssam .ah_releaseTxQueue = ar5212ReleaseTxQueue, 68185377Ssam .ah_resetTxQueue = ar5212ResetTxQueue, 69185377Ssam .ah_getTxDP = ar5212GetTxDP, 70185377Ssam .ah_setTxDP = ar5212SetTxDP, 71185377Ssam .ah_numTxPending = ar5212NumTxPending, 72185377Ssam .ah_startTxDma = ar5212StartTxDma, 73185377Ssam .ah_stopTxDma = ar5212StopTxDma, 74185377Ssam .ah_setupTxDesc = ar5212SetupTxDesc, 75185377Ssam .ah_setupXTxDesc = ar5212SetupXTxDesc, 76185377Ssam .ah_fillTxDesc = ar5212FillTxDesc, 77185377Ssam .ah_procTxDesc = ar5212ProcTxDesc, 78185377Ssam .ah_getTxIntrQueue = ar5212GetTxIntrQueue, 79185377Ssam .ah_reqTxIntrDesc = ar5212IntrReqTxDesc, 80185377Ssam 81185377Ssam /* RX Functions */ 82185377Ssam .ah_getRxDP = ar5212GetRxDP, 83185377Ssam .ah_setRxDP = ar5212SetRxDP, 84185377Ssam .ah_enableReceive = ar5212EnableReceive, 85185377Ssam .ah_stopDmaReceive = ar5212StopDmaReceive, 86185377Ssam .ah_startPcuReceive = ar5212StartPcuReceive, 87185377Ssam .ah_stopPcuReceive = ar5212StopPcuReceive, 88185377Ssam .ah_setMulticastFilter = ar5212SetMulticastFilter, 89185377Ssam .ah_setMulticastFilterIndex = ar5212SetMulticastFilterIndex, 90185377Ssam .ah_clrMulticastFilterIndex = ar5212ClrMulticastFilterIndex, 91185377Ssam .ah_getRxFilter = ar5212GetRxFilter, 92185377Ssam .ah_setRxFilter = ar5212SetRxFilter, 93185377Ssam .ah_setupRxDesc = ar5212SetupRxDesc, 94185377Ssam .ah_procRxDesc = ar5212ProcRxDesc, 95185377Ssam .ah_rxMonitor = ar5212AniPoll, 96185377Ssam .ah_procMibEvent = ar5212ProcessMibIntr, 97185377Ssam 98185377Ssam /* Misc Functions */ 99185377Ssam .ah_getCapability = ar5212GetCapability, 100185377Ssam .ah_setCapability = ar5212SetCapability, 101185377Ssam .ah_getDiagState = ar5212GetDiagState, 102185377Ssam .ah_getMacAddress = ar5212GetMacAddress, 103185377Ssam .ah_setMacAddress = ar5212SetMacAddress, 104185377Ssam .ah_getBssIdMask = ar5212GetBssIdMask, 105185377Ssam .ah_setBssIdMask = ar5212SetBssIdMask, 106185377Ssam .ah_setLedState = ar5212SetLedState, 107185377Ssam .ah_writeAssocid = ar5212WriteAssocid, 108185377Ssam .ah_gpioCfgInput = ar5212GpioCfgInput, 109185377Ssam .ah_gpioCfgOutput = ar5212GpioCfgOutput, 110185377Ssam .ah_gpioGet = ar5212GpioGet, 111185377Ssam .ah_gpioSet = ar5212GpioSet, 112185377Ssam .ah_gpioSetIntr = ar5212GpioSetIntr, 113185377Ssam .ah_getTsf32 = ar5212GetTsf32, 114185377Ssam .ah_getTsf64 = ar5212GetTsf64, 115185377Ssam .ah_resetTsf = ar5212ResetTsf, 116185377Ssam .ah_detectCardPresent = ar5212DetectCardPresent, 117185377Ssam .ah_updateMibCounters = ar5212UpdateMibCounters, 118185377Ssam .ah_getRfGain = ar5212GetRfgain, 119185377Ssam .ah_getDefAntenna = ar5212GetDefAntenna, 120185377Ssam .ah_setDefAntenna = ar5212SetDefAntenna, 121185377Ssam .ah_getAntennaSwitch = ar5212GetAntennaSwitch, 122185377Ssam .ah_setAntennaSwitch = ar5212SetAntennaSwitch, 123185377Ssam .ah_setSifsTime = ar5212SetSifsTime, 124185377Ssam .ah_getSifsTime = ar5212GetSifsTime, 125185377Ssam .ah_setSlotTime = ar5212SetSlotTime, 126185377Ssam .ah_getSlotTime = ar5212GetSlotTime, 127185377Ssam .ah_setAckTimeout = ar5212SetAckTimeout, 128185377Ssam .ah_getAckTimeout = ar5212GetAckTimeout, 129185377Ssam .ah_setAckCTSRate = ar5212SetAckCTSRate, 130185377Ssam .ah_getAckCTSRate = ar5212GetAckCTSRate, 131185377Ssam .ah_setCTSTimeout = ar5212SetCTSTimeout, 132185377Ssam .ah_getCTSTimeout = ar5212GetCTSTimeout, 133185377Ssam .ah_setDecompMask = ar5212SetDecompMask, 134185377Ssam .ah_setCoverageClass = ar5212SetCoverageClass, 135185377Ssam 136185377Ssam /* Key Cache Functions */ 137185377Ssam .ah_getKeyCacheSize = ar5212GetKeyCacheSize, 138185377Ssam .ah_resetKeyCacheEntry = ar5212ResetKeyCacheEntry, 139185377Ssam .ah_isKeyCacheEntryValid = ar5212IsKeyCacheEntryValid, 140185377Ssam .ah_setKeyCacheEntry = ar5212SetKeyCacheEntry, 141185377Ssam .ah_setKeyCacheEntryMac = ar5212SetKeyCacheEntryMac, 142185377Ssam 143185377Ssam /* Power Management Functions */ 144185377Ssam .ah_setPowerMode = ar5212SetPowerMode, 145185377Ssam .ah_getPowerMode = ar5212GetPowerMode, 146185377Ssam 147185377Ssam /* Beacon Functions */ 148185377Ssam .ah_setBeaconTimers = ar5212SetBeaconTimers, 149185377Ssam .ah_beaconInit = ar5212BeaconInit, 150185377Ssam .ah_setStationBeaconTimers = ar5212SetStaBeaconTimers, 151185377Ssam .ah_resetStationBeaconTimers = ar5212ResetStaBeaconTimers, 152185377Ssam 153185377Ssam /* Interrupt Functions */ 154185377Ssam .ah_isInterruptPending = ar5212IsInterruptPending, 155185377Ssam .ah_getPendingInterrupts = ar5212GetPendingInterrupts, 156185377Ssam .ah_getInterrupts = ar5212GetInterrupts, 157185377Ssam .ah_setInterrupts = ar5212SetInterrupts }, 158185377Ssam 159185377Ssam .ah_getChannelEdges = ar5212GetChannelEdges, 160185377Ssam .ah_getWirelessModes = ar5212GetWirelessModes, 161185377Ssam .ah_eepromRead = ar5212EepromRead, 162185377Ssam#ifdef AH_SUPPORT_WRITE_EEPROM 163185377Ssam .ah_eepromWrite = ar5212EepromWrite, 164185377Ssam#endif 165185377Ssam .ah_gpioCfgOutput = ar5212GpioCfgOutput, 166185377Ssam .ah_gpioCfgInput = ar5212GpioCfgInput, 167185377Ssam .ah_gpioGet = ar5212GpioGet, 168185377Ssam .ah_gpioSet = ar5212GpioSet, 169185377Ssam .ah_gpioSetIntr = ar5212GpioSetIntr, 170185377Ssam .ah_getChipPowerLimits = ar5212GetChipPowerLimits, 171185377Ssam}; 172185377Ssam 173185377Ssam/* 174185377Ssam * Disable PLL when in L0s as well as receiver clock when in L1. 175185377Ssam * This power saving option must be enabled through the Serdes. 176185377Ssam * 177185377Ssam * Programming the Serdes must go through the same 288 bit serial shift 178185377Ssam * register as the other analog registers. Hence the 9 writes. 179185377Ssam * 180185377Ssam * XXX Clean up the magic numbers. 181185377Ssam */ 182185377Ssamstatic void 183185377SsamconfigurePciePowerSave(struct ath_hal *ah) 184185377Ssam{ 185185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 186185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 187185377Ssam 188185377Ssam /* RX shut off when elecidle is asserted */ 189185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 190185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 191185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 192185377Ssam 193185377Ssam /* Shut off PLL and CLKREQ active in L1 */ 194185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 195185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 196185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 197185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); 198185377Ssam 199185377Ssam /* Load the new settings */ 200185377Ssam OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 201185377Ssam} 202185377Ssam 203185377Ssamuint32_t 204185377Ssamar5212GetRadioRev(struct ath_hal *ah) 205185377Ssam{ 206185377Ssam uint32_t val; 207185377Ssam int i; 208185377Ssam 209185377Ssam /* Read Radio Chip Rev Extract */ 210185377Ssam OS_REG_WRITE(ah, AR_PHY(0x34), 0x00001c16); 211185377Ssam for (i = 0; i < 8; i++) 212185377Ssam OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 213185377Ssam val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 214185377Ssam val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 215185377Ssam return ath_hal_reverseBits(val, 8); 216185377Ssam} 217185377Ssam 218185377Ssamstatic void 219185377Ssamar5212AniSetup(struct ath_hal *ah) 220185377Ssam{ 221185377Ssam static const struct ar5212AniParams aniparams = { 222185377Ssam .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 223185377Ssam .totalSizeDesired = { -55, -55, -55, -55, -62 }, 224185377Ssam .coarseHigh = { -14, -14, -14, -14, -12 }, 225185377Ssam .coarseLow = { -64, -64, -64, -64, -70 }, 226185377Ssam .firpwr = { -78, -78, -78, -78, -80 }, 227185377Ssam .maxSpurImmunityLevel = 2, /* NB: depends on chip rev */ 228185377Ssam .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 229185377Ssam .maxFirstepLevel = 2, /* levels 0..2 */ 230185377Ssam .firstep = { 0, 4, 8 }, 231185377Ssam .ofdmTrigHigh = 500, 232185377Ssam .ofdmTrigLow = 200, 233185377Ssam .cckTrigHigh = 200, 234185377Ssam .cckTrigLow = 100, 235185377Ssam .rssiThrHigh = 40, 236185377Ssam .rssiThrLow = 7, 237185377Ssam .period = 100, 238185377Ssam }; 239185377Ssam if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { 240185377Ssam struct ar5212AniParams tmp; 241185377Ssam OS_MEMCPY(&tmp, &aniparams, sizeof(struct ar5212AniParams)); 242185377Ssam tmp.maxSpurImmunityLevel = 7; /* Venice and earlier */ 243185377Ssam ar5212AniAttach(ah, &tmp, &tmp, AH_TRUE); 244185377Ssam } else 245185377Ssam ar5212AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 246185377Ssam} 247185377Ssam 248185377Ssam/* 249185377Ssam * Attach for an AR5212 part. 250185377Ssam */ 251185377Ssamvoid 252185377Ssamar5212InitState(struct ath_hal_5212 *ahp, uint16_t devid, HAL_SOFTC sc, 253185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 254185377Ssam{ 255185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 256185377Ssam static const uint8_t defbssidmask[IEEE80211_ADDR_LEN] = 257185377Ssam { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 258185377Ssam struct ath_hal *ah; 259185377Ssam 260185377Ssam ah = &ahp->ah_priv.h; 261185377Ssam /* set initial values */ 262185377Ssam OS_MEMCPY(&ahp->ah_priv, &ar5212hal, sizeof(struct ath_hal_private)); 263185377Ssam ah->ah_sc = sc; 264185377Ssam ah->ah_st = st; 265185377Ssam ah->ah_sh = sh; 266185377Ssam 267185377Ssam ah->ah_devid = devid; /* NB: for alq */ 268185377Ssam AH_PRIVATE(ah)->ah_devid = devid; 269185377Ssam AH_PRIVATE(ah)->ah_subvendorid = 0; /* XXX */ 270185377Ssam 271185377Ssam AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER; 272185377Ssam AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX; /* no scaling */ 273185377Ssam 274185377Ssam ahp->ah_diversityControl = HAL_ANT_VARIABLE; 275185377Ssam ahp->ah_bIQCalibration = AH_FALSE; 276185377Ssam /* 277185377Ssam * Enable MIC handling. 278185377Ssam */ 279185377Ssam ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE; 280185377Ssam ahp->ah_rssiThr = INIT_RSSI_THR; 281185377Ssam ahp->ah_tpcEnabled = AH_FALSE; /* disabled by default */ 282185377Ssam ahp->ah_macTPC = SM(MAX_RATE_POWER, AR_TPC_ACK) 283185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CTS) 284185377Ssam | SM(MAX_RATE_POWER, AR_TPC_CHIRP); 285185377Ssam ahp->ah_beaconInterval = 100; /* XXX [20..1000] */ 286185377Ssam ahp->ah_enable32kHzClock = DONT_USE_32KHZ;/* XXX */ 287185377Ssam ahp->ah_slottime = (u_int) -1; 288185377Ssam ahp->ah_acktimeout = (u_int) -1; 289185377Ssam ahp->ah_ctstimeout = (u_int) -1; 290185377Ssam ahp->ah_sifstime = (u_int) -1; 291185377Ssam OS_MEMCPY(&ahp->ah_bssidmask, defbssidmask, IEEE80211_ADDR_LEN); 292185377Ssam 293185377Ssam /* 294185377Ssam * 11g-specific stuff 295185377Ssam */ 296185377Ssam ahp->ah_gBeaconRate = 0; /* adhoc beacon fixed rate */ 297185377Ssam#undef N 298185377Ssam} 299185377Ssam 300185377Ssam/* 301185377Ssam * Validate MAC version and revision. 302185377Ssam */ 303185377Ssamstatic HAL_BOOL 304185377Ssamar5212IsMacSupported(uint8_t macVersion, uint8_t macRev) 305185377Ssam{ 306185377Ssam#define N(a) (sizeof(a)/sizeof(a[0])) 307185377Ssam static const struct { 308185377Ssam uint8_t version; 309185377Ssam uint8_t revMin, revMax; 310185377Ssam } macs[] = { 311185377Ssam { AR_SREV_VERSION_VENICE, 312185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 313185377Ssam { AR_SREV_VERSION_GRIFFIN, 314185377Ssam AR_SREV_D2PLUS, AR_SREV_REVISION_MAX }, 315185377Ssam { AR_SREV_5413, 316185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 317185377Ssam { AR_SREV_5424, 318185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 319185377Ssam { AR_SREV_2425, 320185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 321185377Ssam { AR_SREV_2417, 322185377Ssam AR_SREV_REVISION_MIN, AR_SREV_REVISION_MAX }, 323185377Ssam }; 324185377Ssam int i; 325185377Ssam 326185377Ssam for (i = 0; i < N(macs); i++) 327185377Ssam if (macs[i].version == macVersion && 328185377Ssam macs[i].revMin <= macRev && macRev <= macs[i].revMax) 329185377Ssam return AH_TRUE; 330185377Ssam return AH_FALSE; 331185377Ssam#undef N 332185377Ssam} 333185377Ssam 334185377Ssam/* 335185377Ssam * Attach for an AR5212 part. 336185377Ssam */ 337185377Ssamstruct ath_hal * 338185377Ssamar5212Attach(uint16_t devid, HAL_SOFTC sc, 339185377Ssam HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 340185377Ssam{ 341185377Ssam#define AH_EEPROM_PROTECT(ah) \ 342185377Ssam (IS_PCIE(ah) ? AR_EEPROM_PROTECT_PCIE : AR_EEPROM_PROTECT) 343185377Ssam struct ath_hal_5212 *ahp; 344185377Ssam struct ath_hal *ah; 345185377Ssam uint32_t val; 346185377Ssam uint16_t eeval; 347185377Ssam HAL_STATUS ecode; 348185377Ssam HAL_BOOL rfStatus; 349185377Ssam 350185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 351185377Ssam __func__, sc, (void*) st, (void*) sh); 352185377Ssam 353185377Ssam /* NB: memory is returned zero'd */ 354185377Ssam ahp = ath_hal_malloc(sizeof (struct ath_hal_5212)); 355185377Ssam if (ahp == AH_NULL) { 356185377Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 357185377Ssam "%s: cannot allocate memory for state block\n", __func__); 358185377Ssam *status = HAL_ENOMEM; 359185377Ssam return AH_NULL; 360185377Ssam } 361185377Ssam ar5212InitState(ahp, devid, sc, st, sh, status); 362185377Ssam ah = &ahp->ah_priv.h; 363185377Ssam 364185377Ssam if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 365185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 366185377Ssam __func__); 367185377Ssam ecode = HAL_EIO; 368185377Ssam goto bad; 369185377Ssam } 370185377Ssam /* Read Revisions from Chips before taking out of reset */ 371185377Ssam val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 372185377Ssam AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 373185377Ssam AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 374185377Ssam 375185377Ssam if (!ar5212IsMacSupported(AH_PRIVATE(ah)->ah_macVersion, AH_PRIVATE(ah)->ah_macRev)) { 376185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 377185377Ssam "%s: Mac Chip Rev 0x%02x.%x not supported\n" , 378185377Ssam __func__, AH_PRIVATE(ah)->ah_macVersion, 379185377Ssam AH_PRIVATE(ah)->ah_macRev); 380185377Ssam ecode = HAL_ENOTSUPP; 381185377Ssam goto bad; 382185377Ssam } 383185377Ssam 384185377Ssam /* setup common ini data; rf backends handle remainder */ 385185377Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar5212Modes, 6); 386185377Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar5212Common, 2); 387185377Ssam 388185377Ssam if (!ar5212ChipReset(ah, AH_NULL)) { /* reset chip */ 389185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 390185377Ssam ecode = HAL_EIO; 391185377Ssam goto bad; 392185377Ssam } 393185377Ssam 394185377Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 395185377Ssam 396185377Ssam if (IS_PCIE(ah)) { 397185377Ssam /* XXX: build flag to disable this? */ 398185377Ssam configurePciePowerSave(ah); 399185377Ssam } 400185377Ssam 401185377Ssam if (!ar5212ChipTest(ah)) { 402185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 403185377Ssam __func__); 404185377Ssam ecode = HAL_ESELFTEST; 405185377Ssam goto bad; 406185377Ssam } 407185377Ssam 408185377Ssam /* Enable PCI core retry fix in software for Hainan and up */ 409185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_VENICE) 410185377Ssam OS_REG_SET_BIT(ah, AR_PCICFG, AR_PCICFG_RETRYFIXEN); 411185377Ssam 412185377Ssam /* 413185377Ssam * Set correct Baseband to analog shift 414185377Ssam * setting to access analog chips. 415185377Ssam */ 416185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 417185377Ssam 418185377Ssam /* Read Radio Chip Rev Extract */ 419185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 420185377Ssam /* NB: silently accept anything in release code per Atheros */ 421185377Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 422185377Ssam case AR_RAD5111_SREV_MAJOR: 423185377Ssam case AR_RAD5112_SREV_MAJOR: 424185377Ssam case AR_RAD2112_SREV_MAJOR: 425185377Ssam case AR_RAD2111_SREV_MAJOR: 426185377Ssam case AR_RAD2413_SREV_MAJOR: 427185377Ssam case AR_RAD5413_SREV_MAJOR: 428185377Ssam case AR_RAD5424_SREV_MAJOR: 429185377Ssam break; 430185377Ssam default: 431185377Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 432185377Ssam /* 433185377Ssam * When RF_Silent is used, the 434185377Ssam * analog chip is reset. So when the system boots 435185377Ssam * up with the radio switch off we cannot determine 436185377Ssam * the RF chip rev. To workaround this check the 437185377Ssam * mac+phy revs and if Hainan, set the radio rev 438185377Ssam * to Derby. 439185377Ssam */ 440185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 441185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN && 442185377Ssam AH_PRIVATE(ah)->ah_phyRev == AR_PHYREV_HAINAN) { 443185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = AR_ANALOG5REV_HAINAN; 444185377Ssam break; 445185377Ssam } 446185377Ssam if (IS_2413(ah)) { /* Griffin */ 447185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 0x51; 448185377Ssam break; 449185377Ssam } 450185377Ssam if (IS_5413(ah)) { /* Eagle */ 451185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 0x62; 452185377Ssam break; 453185377Ssam } 454185377Ssam if (IS_2425(ah) || IS_2417(ah)) {/* Swan or Nala */ 455185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 0xA2; 456185377Ssam break; 457185377Ssam } 458185377Ssam } 459185377Ssam#ifdef AH_DEBUG 460185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 461185377Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 462185377Ssam "this driver\n", 463185377Ssam __func__, AH_PRIVATE(ah)->ah_analog5GhzRev); 464185377Ssam ecode = HAL_ENOTSUPP; 465185377Ssam goto bad; 466185377Ssam#endif 467185377Ssam } 468185377Ssam if (!IS_5413(ah) && IS_5112(ah) && IS_RAD5112_REV1(ah)) { 469185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 470185377Ssam "%s: 5112 Rev 1 is not supported by this " 471185377Ssam "driver (analog5GhzRev 0x%x)\n", __func__, 472185377Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 473185377Ssam ecode = HAL_ENOTSUPP; 474185377Ssam goto bad; 475185377Ssam } 476185377Ssam 477185377Ssam val = OS_REG_READ(ah, AR_PCICFG); 478185377Ssam val = MS(val, AR_PCICFG_EEPROM_SIZE); 479185377Ssam if (val == 0) { 480185377Ssam if (!IS_PCIE(ah)) { 481185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 482185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 483185377Ssam __func__, val, val); 484185377Ssam ecode = HAL_EESIZE; 485185377Ssam goto bad; 486185377Ssam } 487185377Ssam /* XXX AH_PRIVATE(ah)->ah_isPciExpress = AH_TRUE; */ 488185377Ssam } else if (val != AR_PCICFG_EEPROM_SIZE_16K) { 489185377Ssam if (AR_PCICFG_EEPROM_SIZE_FAILED == val) { 490185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 491185377Ssam "%s: unsupported EEPROM size %u (0x%x) found\n", 492185377Ssam __func__, val, val); 493185377Ssam ecode = HAL_EESIZE; 494185377Ssam goto bad; 495185377Ssam } 496185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 497185377Ssam "%s: EEPROM size = %d. Must be %d (16k).\n", 498185377Ssam __func__, val, AR_PCICFG_EEPROM_SIZE_16K); 499185377Ssam ecode = HAL_EESIZE; 500185377Ssam goto bad; 501185377Ssam } 502185377Ssam ecode = ath_hal_legacyEepromAttach(ah); 503185377Ssam if (ecode != HAL_OK) { 504185377Ssam goto bad; 505185377Ssam } 506185377Ssam ahp->ah_isHb63 = IS_2425(ah) && ath_hal_eepromGetFlag(ah, AR_EEP_ISTALON); 507185377Ssam 508185377Ssam /* 509185377Ssam * If Bmode and AR5212, verify 2.4 analog exists 510185377Ssam */ 511185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) && 512185377Ssam (AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD5111_SREV_MAJOR) { 513185377Ssam /* 514185377Ssam * Set correct Baseband to analog shift 515185377Ssam * setting to access analog chips. 516185377Ssam */ 517185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00004007); 518185377Ssam OS_DELAY(2000); 519185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev = ar5212GetRadioRev(ah); 520185377Ssam 521185377Ssam /* Set baseband for 5GHz chip */ 522185377Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 523185377Ssam OS_DELAY(2000); 524185377Ssam if ((AH_PRIVATE(ah)->ah_analog2GhzRev & 0xF0) != AR_RAD2111_SREV_MAJOR) { 525185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 526185377Ssam "%s: 2G Radio Chip Rev 0x%02X is not " 527185377Ssam "supported by this driver\n", __func__, 528185377Ssam AH_PRIVATE(ah)->ah_analog2GhzRev); 529185377Ssam ecode = HAL_ENOTSUPP; 530185377Ssam goto bad; 531185377Ssam } 532185377Ssam } 533185377Ssam 534185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, &eeval); 535185377Ssam if (ecode != HAL_OK) { 536185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 537185377Ssam "%s: cannot read regulatory domain from EEPROM\n", 538185377Ssam __func__); 539185377Ssam goto bad; 540185377Ssam } 541185377Ssam AH_PRIVATE(ah)->ah_currentRD = eeval; 542185377Ssam /* XXX record serial number */ 543185377Ssam 544185377Ssam /* 545185377Ssam * Got everything we need now to setup the capabilities. 546185377Ssam */ 547185377Ssam if (!ar5212FillCapabilityInfo(ah)) { 548185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 549185377Ssam "%s: failed ar5212FillCapabilityInfo\n", __func__); 550185377Ssam ecode = HAL_EEREAD; 551185377Ssam goto bad; 552185377Ssam } 553185377Ssam 554185377Ssam rfStatus = AH_FALSE; 555185377Ssam if (IS_5413(ah)) { 556185377Ssam#ifdef AH_SUPPORT_5413 557185377Ssam rfStatus = ar5413RfAttach(ah, &ecode); 558185377Ssam#else 559185377Ssam ecode = HAL_ENOTSUPP; 560185377Ssam#endif 561185377Ssam } 562185377Ssam else if (IS_2413(ah)) 563185377Ssam#ifdef AH_SUPPORT_2413 564185377Ssam rfStatus = ar2413RfAttach(ah, &ecode); 565185377Ssam#else 566185377Ssam ecode = HAL_ENOTSUPP; 567185377Ssam#endif 568185377Ssam else if (IS_5112(ah)) 569185377Ssam#ifdef AH_SUPPORT_5112 570185377Ssam rfStatus = ar5112RfAttach(ah, &ecode); 571185377Ssam#else 572185377Ssam ecode = HAL_ENOTSUPP; 573185377Ssam#endif 574185377Ssam else if (IS_2425(ah) || IS_2417(ah)) 575185377Ssam#ifdef AH_SUPPORT_2425 576185377Ssam rfStatus = ar2425RfAttach(ah, &ecode); 577185377Ssam#else 578185377Ssam ecode = HAL_ENOTSUPP; 579185377Ssam#endif 580185377Ssam else 581185377Ssam#ifdef AH_SUPPORT_5111 582185377Ssam rfStatus = ar5111RfAttach(ah, &ecode); 583185377Ssam#else 584185377Ssam ecode = HAL_ENOTSUPP; 585185377Ssam#endif 586185377Ssam if (!rfStatus) { 587185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 588185377Ssam __func__, ecode); 589185377Ssam goto bad; 590185377Ssam } 591185377Ssam /* 592185377Ssam * Set noise floor adjust method; we arrange a 593185377Ssam * direct call instead of thunking. 594185377Ssam */ 595185377Ssam AH_PRIVATE(ah)->ah_getNfAdjust = ahp->ah_rfHal->getNfAdjust; 596185377Ssam 597185377Ssam /* Initialize gain ladder thermal calibration structure */ 598185377Ssam ar5212InitializeGainValues(ah); 599185377Ssam 600185377Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 601185377Ssam if (ecode != HAL_OK) { 602185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 603185377Ssam "%s: error getting mac address from EEPROM\n", __func__); 604185377Ssam goto bad; 605185377Ssam } 606185377Ssam 607185377Ssam ar5212AniSetup(ah); 608185377Ssam /* Setup of Radar/AR structures happens in ath_hal_initchannels*/ 609185377Ssam ar5212InitNfCalHistBuffer(ah); 610185377Ssam 611185377Ssam /* XXX EAR stuff goes here */ 612185377Ssam 613185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 614185377Ssam 615185377Ssam return ah; 616185377Ssam 617185377Ssambad: 618185377Ssam if (ahp) 619185377Ssam ar5212Detach((struct ath_hal *) ahp); 620185377Ssam if (status) 621185377Ssam *status = ecode; 622185377Ssam return AH_NULL; 623185377Ssam#undef AH_EEPROM_PROTECT 624185377Ssam} 625185377Ssam 626185377Ssamvoid 627185377Ssamar5212Detach(struct ath_hal *ah) 628185377Ssam{ 629185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 630185377Ssam 631185377Ssam HALASSERT(ah != AH_NULL); 632185377Ssam HALASSERT(ah->ah_magic == AR5212_MAGIC); 633185377Ssam 634185377Ssam ar5212AniDetach(ah); 635185377Ssam ar5212RfDetach(ah); 636185377Ssam ar5212Disable(ah); 637185377Ssam ar5212SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 638185377Ssam 639185377Ssam ath_hal_eepromDetach(ah); 640185377Ssam ath_hal_free(ah); 641185377Ssam} 642185377Ssam 643185377SsamHAL_BOOL 644185377Ssamar5212ChipTest(struct ath_hal *ah) 645185377Ssam{ 646185377Ssam uint32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) }; 647185377Ssam uint32_t regHold[2]; 648185377Ssam uint32_t patternData[4] = 649185377Ssam { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 }; 650185377Ssam int i, j; 651185377Ssam 652185377Ssam /* Test PHY & MAC registers */ 653185377Ssam for (i = 0; i < 2; i++) { 654185377Ssam uint32_t addr = regAddr[i]; 655185377Ssam uint32_t wrData, rdData; 656185377Ssam 657185377Ssam regHold[i] = OS_REG_READ(ah, addr); 658185377Ssam for (j = 0; j < 0x100; j++) { 659185377Ssam wrData = (j << 16) | j; 660185377Ssam OS_REG_WRITE(ah, addr, wrData); 661185377Ssam rdData = OS_REG_READ(ah, addr); 662185377Ssam if (rdData != wrData) { 663185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 664185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 665185377Ssam __func__, addr, wrData, rdData); 666185377Ssam return AH_FALSE; 667185377Ssam } 668185377Ssam } 669185377Ssam for (j = 0; j < 4; j++) { 670185377Ssam wrData = patternData[j]; 671185377Ssam OS_REG_WRITE(ah, addr, wrData); 672185377Ssam rdData = OS_REG_READ(ah, addr); 673185377Ssam if (wrData != rdData) { 674185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 675185377Ssam"%s: address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 676185377Ssam __func__, addr, wrData, rdData); 677185377Ssam return AH_FALSE; 678185377Ssam } 679185377Ssam } 680185377Ssam OS_REG_WRITE(ah, regAddr[i], regHold[i]); 681185377Ssam } 682185377Ssam OS_DELAY(100); 683185377Ssam return AH_TRUE; 684185377Ssam} 685185377Ssam 686185377Ssam/* 687185377Ssam * Store the channel edges for the requested operational mode 688185377Ssam */ 689185377SsamHAL_BOOL 690185377Ssamar5212GetChannelEdges(struct ath_hal *ah, 691185377Ssam uint16_t flags, uint16_t *low, uint16_t *high) 692185377Ssam{ 693185377Ssam if (flags & CHANNEL_5GHZ) { 694185377Ssam *low = 4915; 695185377Ssam *high = 6100; 696185377Ssam return AH_TRUE; 697185377Ssam } 698185377Ssam if ((flags & CHANNEL_2GHZ) && 699185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE) || 700185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_GMODE))) { 701185377Ssam *low = 2312; 702185377Ssam *high = 2732; 703185377Ssam return AH_TRUE; 704185377Ssam } 705185377Ssam return AH_FALSE; 706185377Ssam} 707185377Ssam 708185377Ssam/* 709185377Ssam * Fill all software cached or static hardware state information. 710185377Ssam * Return failure if capabilities are to come from EEPROM and 711185377Ssam * cannot be read. 712185377Ssam */ 713185377SsamHAL_BOOL 714185377Ssamar5212FillCapabilityInfo(struct ath_hal *ah) 715185377Ssam{ 716185377Ssam#define AR_KEYTABLE_SIZE 128 717185377Ssam#define IS_GRIFFIN_LITE(ah) \ 718185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_GRIFFIN && \ 719185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_GRIFFIN_LITE) 720185377Ssam#define IS_COBRA(ah) \ 721185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_COBRA) 722185377Ssam#define IS_2112(ah) \ 723185377Ssam ((AH_PRIVATE(ah)->ah_analog5GhzRev & 0xF0) == AR_RAD2112_SREV_MAJOR) 724185377Ssam 725185377Ssam struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 726185377Ssam HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 727185377Ssam uint16_t capField, val; 728185377Ssam 729185377Ssam /* Read the capability EEPROM location */ 730185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_OPCAP, &capField) != HAL_OK) { 731185377Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 732185377Ssam "%s: unable to read caps from eeprom\n", __func__); 733185377Ssam return AH_FALSE; 734185377Ssam } 735185377Ssam if (IS_2112(ah)) 736185377Ssam ath_hal_eepromSet(ah, AR_EEP_AMODE, AH_FALSE); 737185377Ssam if (capField == 0 && IS_GRIFFIN_LITE(ah)) { 738185377Ssam /* 739185377Ssam * For griffin-lite cards with unprogrammed capabilities. 740185377Ssam */ 741185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 742185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 743185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 744185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 745185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 746185377Ssam "%s: override caps for griffin-lite, now 0x%x (+!turbo)\n", 747185377Ssam __func__, capField); 748185377Ssam } 749185377Ssam 750185377Ssam /* Modify reg domain on newer cards that need to work with older sw */ 751185377Ssam if (ahpriv->ah_opmode != HAL_M_HOSTAP && 752185377Ssam ahpriv->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) { 753185377Ssam if (ahpriv->ah_currentRD == 0x64 || 754185377Ssam ahpriv->ah_currentRD == 0x65) 755185377Ssam ahpriv->ah_currentRD += 5; 756185377Ssam else if (ahpriv->ah_currentRD == 0x41) 757185377Ssam ahpriv->ah_currentRD = 0x43; 758185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: regdomain mapped to 0x%x\n", 759185377Ssam __func__, ahpriv->ah_currentRD); 760185377Ssam } 761185377Ssam 762185377Ssam if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2417 || 763185377Ssam AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425) { 764185377Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 765185377Ssam "%s: enable Bmode and disable turbo for Swan/Nala\n", 766185377Ssam __func__); 767185377Ssam ath_hal_eepromSet(ah, AR_EEP_BMODE, AH_TRUE); 768185377Ssam ath_hal_eepromSet(ah, AR_EEP_COMPRESS, AH_FALSE); 769185377Ssam ath_hal_eepromSet(ah, AR_EEP_FASTFRAME, AH_FALSE); 770185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO5DISABLE, AH_TRUE); 771185377Ssam ath_hal_eepromSet(ah, AR_EEP_TURBO2DISABLE, AH_TRUE); 772185377Ssam } 773185377Ssam 774185377Ssam /* Construct wireless mode from EEPROM */ 775185377Ssam pCap->halWirelessModes = 0; 776185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 777185377Ssam pCap->halWirelessModes |= HAL_MODE_11A; 778185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE)) 779185377Ssam pCap->halWirelessModes |= HAL_MODE_TURBO; 780185377Ssam } 781185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) 782185377Ssam pCap->halWirelessModes |= HAL_MODE_11B; 783185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) && 784185377Ssam ahpriv->ah_subvendorid != AR_SUBVENDOR_ID_NOG) { 785185377Ssam pCap->halWirelessModes |= HAL_MODE_11G; 786185377Ssam if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE)) 787185377Ssam pCap->halWirelessModes |= HAL_MODE_108G; 788185377Ssam } 789185377Ssam 790185377Ssam pCap->halLow2GhzChan = 2312; 791185377Ssam if (IS_5112(ah) || IS_2413(ah) || IS_5413(ah) || IS_2425(ah)) 792185377Ssam pCap->halHigh2GhzChan = 2500; 793185377Ssam else 794185377Ssam pCap->halHigh2GhzChan = 2732; 795185377Ssam 796185377Ssam pCap->halLow5GhzChan = 4915; 797185377Ssam pCap->halHigh5GhzChan = 6100; 798185377Ssam 799185377Ssam pCap->halCipherCkipSupport = AH_FALSE; 800185377Ssam pCap->halCipherTkipSupport = AH_TRUE; 801185377Ssam pCap->halCipherAesCcmSupport = 802185377Ssam (ath_hal_eepromGetFlag(ah, AR_EEP_AES) && 803185377Ssam ((AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE) || 804185377Ssam ((AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE) && 805185377Ssam (AH_PRIVATE(ah)->ah_macRev >= AR_SREV_VERSION_OAHU)))); 806185377Ssam 807185377Ssam pCap->halMicCkipSupport = AH_FALSE; 808185377Ssam pCap->halMicTkipSupport = AH_TRUE; 809185377Ssam pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 810185377Ssam /* 811185377Ssam * Starting with Griffin TX+RX mic keys can be combined 812185377Ssam * in one key cache slot. 813185377Ssam */ 814185377Ssam if (AH_PRIVATE(ah)->ah_macVersion >= AR_SREV_VERSION_GRIFFIN) 815185377Ssam pCap->halTkipMicTxRxKeySupport = AH_TRUE; 816185377Ssam else 817185377Ssam pCap->halTkipMicTxRxKeySupport = AH_FALSE; 818185377Ssam pCap->halChanSpreadSupport = AH_TRUE; 819185377Ssam pCap->halSleepAfterBeaconBroken = AH_TRUE; 820185377Ssam 821185377Ssam if (ahpriv->ah_macRev > 1 || IS_COBRA(ah)) { 822185377Ssam pCap->halCompressSupport = 823185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_COMPRESS) && 824185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 825185377Ssam pCap->halBurstSupport = ath_hal_eepromGetFlag(ah, AR_EEP_BURST); 826185377Ssam pCap->halFastFramesSupport = 827185377Ssam ath_hal_eepromGetFlag(ah, AR_EEP_FASTFRAME) && 828185377Ssam (pCap->halWirelessModes & (HAL_MODE_11A|HAL_MODE_11G)) != 0; 829185377Ssam pCap->halChapTuningSupport = AH_TRUE; 830185377Ssam pCap->halTurboPrimeSupport = AH_TRUE; 831185377Ssam } 832185377Ssam pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 833185377Ssam 834185377Ssam pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 835185377Ssam pCap->halVEOLSupport = AH_TRUE; 836185377Ssam pCap->halBssIdMaskSupport = AH_TRUE; 837185377Ssam pCap->halMcastKeySrchSupport = AH_TRUE; 838185377Ssam if ((ahpriv->ah_macVersion == AR_SREV_VERSION_VENICE && 839185377Ssam ahpriv->ah_macRev == 8) || 840185377Ssam ahpriv->ah_macVersion > AR_SREV_VERSION_VENICE) 841185377Ssam pCap->halTsfAddSupport = AH_TRUE; 842185377Ssam 843185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 844185377Ssam pCap->halTotalQueues = val; 845185377Ssam else 846185377Ssam pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 847185377Ssam 848185377Ssam if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 849185377Ssam pCap->halKeyCacheSize = val; 850185377Ssam else 851185377Ssam pCap->halKeyCacheSize = AR_KEYTABLE_SIZE; 852185377Ssam 853185377Ssam if (IS_5112(ah)) { 854185377Ssam pCap->halChanHalfRate = AH_TRUE; 855185377Ssam pCap->halChanQuarterRate = AH_TRUE; 856185377Ssam } else { 857185377Ssam /* XXX not needed */ 858185377Ssam pCap->halChanHalfRate = AH_FALSE; 859185377Ssam pCap->halChanQuarterRate = AH_FALSE; 860185377Ssam } 861185377Ssam 862185377Ssam if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 863185377Ssam ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 864185377Ssam /* NB: enabled by default */ 865185377Ssam ahpriv->ah_rfkillEnabled = AH_TRUE; 866185377Ssam pCap->halRfSilentSupport = AH_TRUE; 867185377Ssam } 868185377Ssam 869185377Ssam /* NB: this is a guess, noone seems to know the answer */ 870185377Ssam ahpriv->ah_rxornIsFatal = 871185377Ssam (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_VENICE); 872185377Ssam 873185377Ssam /* h/w phy counters first appeared in Hainan */ 874185377Ssam pCap->halHwPhyCounterSupport = 875185377Ssam (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE && 876185377Ssam AH_PRIVATE(ah)->ah_macRev == AR_SREV_HAINAN) || 877185377Ssam AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE; 878185377Ssam 879185377Ssam pCap->halTstampPrecision = 15; 880185377Ssam 881185377Ssam return AH_TRUE; 882185377Ssam#undef IS_COBRA 883185377Ssam#undef IS_GRIFFIN_LITE 884185377Ssam#undef AR_KEYTABLE_SIZE 885185377Ssam} 886185377Ssam#endif /* AH_SUPPORT_AR5212 */ 887