ar5211phy.h revision 303975
1202375Srdivacky/* 2202375Srdivacky * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3202375Srdivacky * Copyright (c) 2002-2006 Atheros Communications, Inc. 4202375Srdivacky * 5202375Srdivacky * Permission to use, copy, modify, and/or distribute this software for any 6202375Srdivacky * purpose with or without fee is hereby granted, provided that the above 7202375Srdivacky * copyright notice and this permission notice appear in all copies. 8202375Srdivacky * 9202375Srdivacky * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10202375Srdivacky * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11202375Srdivacky * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12202375Srdivacky * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13202375Srdivacky * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14202375Srdivacky * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15202375Srdivacky * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16218893Sdim * 17249423Sdim * $FreeBSD: releng/11.0/sys/dev/ath/ath_hal/ar5211/ar5211phy.h 204644 2010-03-03 17:32:32Z rpaulo $ 18202375Srdivacky */ 19202375Srdivacky#ifndef _DEV_ATH_AR5211PHY_H 20202375Srdivacky#define _DEV_ATH_AR5211PHY_H 21202375Srdivacky 22223017Sdim/* 23223017Sdim * Definitions for the PHY on the Atheros AR5211/5311 chipset. 24223017Sdim */ 25223017Sdim 26223017Sdim/* PHY registers */ 27223017Sdim#define AR_PHY_BASE 0x9800 /* PHY registers base address */ 28223017Sdim#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 29223017Sdim 30223017Sdim#define AR_PHY_TURBO 0x9804 /* PHY frame control register */ 31251662Sdim#define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */ 32223017Sdim#define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */ 33223017Sdim 34223017Sdim#define AR_PHY_CHIP_ID 0x9818 /* PHY chip revision ID */ 35223017Sdim 36223017Sdim#define AR_PHY_ACTIVE 0x981C /* PHY activation register */ 37223017Sdim#define AR_PHY_ACTIVE_EN 0x00000001 /* Activate PHY chips */ 38223017Sdim#define AR_PHY_ACTIVE_DIS 0x00000000 /* Deactivate PHY chips */ 39223017Sdim 40249423Sdim#define AR_PHY_AGC_CONTROL 0x9860 /* PHY chip calibration and noise floor setting */ 41226633Sdim#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* Perform PHY chip internal calibration */ 42223017Sdim#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* Perform PHY chip noise-floor calculation */ 43223017Sdim 44251662Sdim#define AR_PHY_PLL_CTL 0x987c /* PLL control register */ 45223017Sdim#define AR_PHY_PLL_CTL_44 0x19 /* 44 MHz for 11b channels and FPGA */ 46223017Sdim#define AR_PHY_PLL_CTL_40 0x18 /* 40 MHz */ 47223017Sdim#define AR_PHY_PLL_CTL_20 0x13 /* 20 MHz half rate 11a for emulation */ 48249423Sdim 49223017Sdim 50223017Sdim#define AR_PHY_RX_DELAY 0x9914 /* PHY analog_power_on_time, in 100ns increments */ 51223017Sdim#define AR_PHY_RX_DELAY_M 0x00003FFF /* Mask for delay from active assertion (wake up) */ 52223017Sdim /* to enable_receiver */ 53223017Sdim 54223017Sdim#define AR_PHY_TIMING_CTRL4 0x9920 /* PHY */ 55251662Sdim#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_M 0x0000001F /* Mask for kcos_theta-1 for q correction */ 56223017Sdim#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_M 0x000007E0 /* Mask for sin_theta for i correction */ 57223017Sdim#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5 /* Shift for sin_theta for i correction */ 58223017Sdim#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x00000800 /* enable IQ correction */ 59223017Sdim#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_M 0x0000F000 /* Mask for max number of samples (logarithmic) */ 60251662Sdim#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12 /* Shift for max number of samples */ 61223017Sdim#define AR_PHY_TIMING_CTRL4_DO_IQCAL 0x00010000 /* perform IQ calibration */ 62223017Sdim 63223017Sdim#define AR_PHY_PAPD_PROBE 0x9930 64223017Sdim#define AR_PHY_PAPD_PROBE_POWERTX 0x00007E00 65223017Sdim#define AR_PHY_PAPD_PROBE_POWERTX_S 9 66223017Sdim#define AR_PHY_PAPD_PROBE_NEXT_TX 0x00008000 /* command to take next reading */ 67223017Sdim#define AR_PHY_PAPD_PROBE_GAINF 0xFE000000 68223017Sdim#define AR_PHY_PAPD_PROBE_GAINF_S 25 69223017Sdim 70251662Sdim#define AR_PHY_POWER_TX_RATE1 0x9934 71223017Sdim#define AR_PHY_POWER_TX_RATE2 0x9938 72223017Sdim#define AR_PHY_POWER_TX_RATE_MAX 0x993c 73223017Sdim 74223017Sdim#define AR_PHY_FRAME_CTL 0x9944 75202375Srdivacky#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038 76202375Srdivacky#define AR_PHY_FRAME_CTL_TX_CLIP_S 3 77202375Srdivacky#define AR_PHY_FRAME_CTL_ERR_SERV 0x20000000 78202375Srdivacky#define AR_PHY_FRAME_CTL_ERR_SERV_S 29 79202375Srdivacky 80202375Srdivacky#define AR_PHY_RADAR_0 0x9954 /* PHY radar detection settings */ 81218893Sdim#define AR_PHY_RADAR_0_ENA 0x00000001 /* Enable radar detection */ 82218893Sdim 83202375Srdivacky#define AR_PHY_IQCAL_RES_PWR_MEAS_I 0x9c10 /*PHY IQ calibration results - power measurement for I */ 84218893Sdim#define AR_PHY_IQCAL_RES_PWR_MEAS_Q 0x9c14 /*PHY IQ calibration results - power measurement for Q */ 85218893Sdim#define AR_PHY_IQCAL_RES_IQ_CORR_MEAS 0x9c18 /*PHY IQ calibration results - IQ correlation measurement */ 86202375Srdivacky#define AR_PHY_CURRENT_RSSI 0x9c1c /* rssi of current frame being received */ 87251662Sdim 88202375Srdivacky#define AR5211_PHY_MODE 0xA200 /* Mode register */ 89251662Sdim#define AR5211_PHY_MODE_OFDM 0x0 /* bit 0 = 0 for OFDM */ 90202375Srdivacky#define AR5211_PHY_MODE_CCK 0x1 /* bit 0 = 1 for CCK */ 91202375Srdivacky#define AR5211_PHY_MODE_RF5GHZ 0x0 /* bit 1 = 0 for 5 GHz */ 92251662Sdim#define AR5211_PHY_MODE_RF2GHZ 0x2 /* bit 1 = 1 for 2.4 GHz */ 93202375Srdivacky 94202375Srdivacky#endif /* _DEV_ATH_AR5211PHY_H */ 95202375Srdivacky