ah_eeprom_v4k.h revision 208711
150397Sobrien/* 2169689Skan * Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org> 3169689Skan * Copyright (c) 2008 Sam Leffler, Errno Consulting 450397Sobrien * Copyright (c) 2008 Atheros Communications, Inc. 550397Sobrien * 650397Sobrien * Permission to use, copy, modify, and/or distribute this software for any 790075Sobrien * purpose with or without fee is hereby granted, provided that the above 850397Sobrien * copyright notice and this permission notice appear in all copies. 990075Sobrien * 1090075Sobrien * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1190075Sobrien * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1290075Sobrien * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1350397Sobrien * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1490075Sobrien * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1590075Sobrien * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1690075Sobrien * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1790075Sobrien * 1850397Sobrien * $FreeBSD: head/sys/dev/ath/ath_hal/ah_eeprom_v4k.h 208711 2010-06-01 15:33:10Z rpaulo $ 1990075Sobrien */ 2090075Sobrien#ifndef _AH_EEPROM_V4K_H_ 21169689Skan#define _AH_EEPROM_V4K_H_ 22169689Skan 2350397Sobrien#include "ah_eeprom.h" 2490075Sobrien#include "ah_eeprom_v14.h" 2590075Sobrien 2690075Sobrien#define AR9285_RDEXT_DEFAULT 0x1F 2750397Sobrien 2850397Sobrien#undef owl_eep_start_loc 2950397Sobrien#ifdef __LINUX_ARM_ARCH__ /* AP71 */ 3050397Sobrien#define owl_eep_start_loc 0 3150397Sobrien#else 3250397Sobrien#define owl_eep_start_loc 64 3350397Sobrien#endif 3450397Sobrien 3550397Sobrien// 16-bit offset location start of calibration struct 3650397Sobrien#define AR5416_4K_EEP_START_LOC 64 3750397Sobrien#define AR5416_4K_NUM_2G_CAL_PIERS 3 3850397Sobrien#define AR5416_4K_NUM_2G_CCK_TARGET_POWERS 3 3950397Sobrien#define AR5416_4K_NUM_2G_20_TARGET_POWERS 3 4050397Sobrien#define AR5416_4K_NUM_2G_40_TARGET_POWERS 3 4150397Sobrien#define AR5416_4K_NUM_CTLS 12 4250397Sobrien#define AR5416_4K_NUM_BAND_EDGES 4 4350397Sobrien#define AR5416_4K_NUM_PD_GAINS 2 4450397Sobrien#define AR5416_4K_MAX_CHAINS 1 4550397Sobrien 4650397Sobrien/* 4750397Sobrien * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version 4850397Sobrien * and length are swapped). We reverse their position after reading 4950397Sobrien * the data into host memory so the version field is at the same 5050397Sobrien * offset as in previous EEPROM layouts. This makes utilities that 5150397Sobrien * inspect the EEPROM contents work without looking at the PCI device 5250397Sobrien * id which may or may not be reliable. 5350397Sobrien */ 5450397Sobrientypedef struct BaseEepHeader4k { 5550397Sobrien uint16_t version; /* NB: length in EEPROM */ 5650397Sobrien uint16_t checksum; 5750397Sobrien uint16_t length; /* NB: version in EEPROM */ 5850397Sobrien uint8_t opCapFlags; 5950397Sobrien uint8_t eepMisc; 6050397Sobrien uint16_t regDmn[2]; 6150397Sobrien uint8_t macAddr[6]; 6250397Sobrien uint8_t rxMask; 6350397Sobrien uint8_t txMask; 6450397Sobrien uint16_t rfSilent; 6550397Sobrien uint16_t blueToothOptions; 6650397Sobrien uint16_t deviceCap; 6750397Sobrien uint32_t binBuildNumber; 6850397Sobrien uint8_t deviceType; 6950397Sobrien uint8_t txGainType; /* high power tx gain table support */ 7050397Sobrien} __packed BASE_EEP4K_HEADER; // 32 B 7150397Sobrien 7250397Sobrientypedef struct ModalEepHeader4k { 7350397Sobrien uint32_t antCtrlChain[AR5416_4K_MAX_CHAINS]; // 12 7450397Sobrien uint32_t antCtrlCommon; // 4 7550397Sobrien int8_t antennaGainCh[AR5416_4K_MAX_CHAINS]; // 1 7650397Sobrien uint8_t switchSettling; // 1 7750397Sobrien uint8_t txRxAttenCh[AR5416_4K_MAX_CHAINS]; // 1 7850397Sobrien uint8_t rxTxMarginCh[AR5416_4K_MAX_CHAINS]; // 1 7950397Sobrien uint8_t adcDesiredSize; // 1 8050397Sobrien int8_t pgaDesiredSize; // 1 8150397Sobrien uint8_t xlnaGainCh[AR5416_4K_MAX_CHAINS]; // 1 8250397Sobrien uint8_t txEndToXpaOff; // 1 8350397Sobrien uint8_t txEndToRxOn; // 1 8450397Sobrien uint8_t txFrameToXpaOn; // 1 8550397Sobrien uint8_t thresh62; // 1 8650397Sobrien uint8_t noiseFloorThreshCh[AR5416_4K_MAX_CHAINS]; // 1 8750397Sobrien uint8_t xpdGain; // 1 8850397Sobrien uint8_t xpd; // 1 8950397Sobrien int8_t iqCalICh[AR5416_4K_MAX_CHAINS]; // 1 9050397Sobrien int8_t iqCalQCh[AR5416_4K_MAX_CHAINS]; // 1 9150397Sobrien uint8_t pdGainOverlap; // 1 9250397Sobrien uint8_t ob; // 1 9350397Sobrien uint8_t db; // 1 9450397Sobrien uint8_t xpaBiasLvl; // 1 9550397Sobrien#if 0 9650397Sobrien uint8_t pwrDecreaseFor2Chain; // 1 9750397Sobrien uint8_t pwrDecreaseFor3Chain; // 1 -> 48 B 9850397Sobrien#endif 9950397Sobrien uint8_t txFrameToDataStart; // 1 10050397Sobrien uint8_t txFrameToPaOn; // 1 10150397Sobrien uint8_t ht40PowerIncForPdadc; // 1 10250397Sobrien uint8_t bswAtten[AR5416_4K_MAX_CHAINS]; // 1 10350397Sobrien uint8_t bswMargin[AR5416_4K_MAX_CHAINS]; // 1 10450397Sobrien uint8_t swSettleHt40; // 1 10550397Sobrien uint8_t xatten2Db[AR5416_4K_MAX_CHAINS]; // 1 10650397Sobrien uint8_t xatten2Margin[AR5416_4K_MAX_CHAINS]; // 1 10750397Sobrien uint8_t ob_ch1; // 1 -> ob and db become chain specific from AR9280 10850397Sobrien uint8_t db_ch1; // 1 10950397Sobrien uint8_t flagBits; // 1 11050397Sobrien#define AR5416_EEP_FLAG_USEANT1 0x01 /* +1 configured antenna */ 11150397Sobrien#define AR5416_EEP_FLAG_FORCEXPAON 0x02 /* force XPA bit for 5G */ 11250397Sobrien#define AR5416_EEP_FLAG_LOCALBIAS 0x04 /* enable local bias */ 11350397Sobrien#define AR5416_EEP_FLAG_FEMBANDSELECT 0x08 /* FEM band select used */ 11450397Sobrien#define AR5416_EEP_FLAG_XLNABUFIN 0x10 11550397Sobrien#define AR5416_EEP_FLAG_XLNAISEL 0x60 11650397Sobrien#define AR5416_EEP_FLAG_XLNAISEL_S 5 11750397Sobrien#define AR5416_EEP_FLAG_XLNABUFMODE 0x80 11850397Sobrien uint8_t miscBits; // [0..1]: bb_tx_dac_scale_cck 119132718Skan uint16_t xpaBiasLvlFreq[3]; // 6 12050397Sobrien uint8_t futureModal[2]; // 2 12150397Sobrien 12250397Sobrien SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B 12350397Sobrien} __packed MODAL_EEP4K_HEADER; // == 68 B 12450397Sobrien 12590075Sobrientypedef struct CalCtlData4k { 12650397Sobrien CAL_CTL_EDGES ctlEdges[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_BAND_EDGES]; 12750397Sobrien} __packed CAL_CTL_DATA_4K; 12850397Sobrien 129132718Skantypedef struct calDataPerFreq4k { 130132718Skan uint8_t pwrPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 13152284Sobrien uint8_t vpdPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 13250397Sobrien} __packed CAL_DATA_PER_FREQ_4K; 13390075Sobrien 13490075Sobrienstruct ar5416eeprom_4k { 13550397Sobrien BASE_EEP4K_HEADER baseEepHeader; // 32 B 13690075Sobrien uint8_t custData[20]; // 20 B 13750397Sobrien MODAL_EEP4K_HEADER modalHeader; // 68 B 13850397Sobrien uint8_t calFreqPier2G[AR5416_4K_NUM_2G_CAL_PIERS]; 13950397Sobrien CAL_DATA_PER_FREQ_4K calPierData2G[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_2G_CAL_PIERS]; 14050397Sobrien CAL_TARGET_POWER_LEG calTargetPowerCck[AR5416_4K_NUM_2G_CCK_TARGET_POWERS]; 14150397Sobrien CAL_TARGET_POWER_LEG calTargetPower2G[AR5416_4K_NUM_2G_20_TARGET_POWERS]; 14252284Sobrien CAL_TARGET_POWER_HT calTargetPower2GHT20[AR5416_4K_NUM_2G_20_TARGET_POWERS]; 14390075Sobrien CAL_TARGET_POWER_HT calTargetPower2GHT40[AR5416_4K_NUM_2G_40_TARGET_POWERS]; 14490075Sobrien uint8_t ctlIndex[AR5416_4K_NUM_CTLS]; 145169689Skan CAL_CTL_DATA_4K ctlData[AR5416_4K_NUM_CTLS]; 146169689Skan uint8_t padding; 14750397Sobrien} __packed; 14850397Sobrien 14950397Sobrientypedef struct { 15050397Sobrien struct ar5416eeprom_4k ee_base; 15150397Sobrien#define NUM_EDGES 8 15250397Sobrien uint16_t ee_numCtls; 15350397Sobrien RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_4K_NUM_CTLS]; 15450397Sobrien /* XXX these are dynamically calculated for use by shared code */ 15550397Sobrien int8_t ee_antennaGainMax; 15650397Sobrien} HAL_EEPROM_v4k; 15790075Sobrien#endif /* _AH_EEPROM_V4K_H_ */ 15850397Sobrien