ata-dma.c revision 56988
1/*- 2 * Copyright (c) 1998,1999,2000 S�ren Schmidt 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 56988 2000-02-04 10:20:22Z sos $ 29 */ 30 31#include "pci.h" 32#include "apm.h" 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/buf.h> 36#include <sys/malloc.h> 37#include <sys/bus.h> 38#include <sys/disk.h> 39#include <sys/devicestat.h> 40#include <vm/vm.h> 41#include <vm/pmap.h> 42#if NPCI > 0 43#include <pci/pcivar.h> 44#endif 45#if NAPM > 0 46#include <machine/apm_bios.h> 47#endif 48#include <dev/ata/ata-all.h> 49#include <dev/ata/ata-disk.h> 50 51#if NPCI > 0 52 53/* prototypes */ 54static void promise_timing(struct ata_softc *, int32_t, int32_t); 55static void hpt366_timing(struct ata_softc *, int32_t, int32_t); 56 57/* misc defines */ 58#ifdef __alpha__ 59#undef vtophys 60#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 61#endif 62 63void 64ata_dmainit(struct ata_softc *scp, int32_t device, 65 int32_t apiomode, int32_t wdmamode, int32_t udmamode) 66{ 67 int32_t devno = (scp->unit << 1) + ATA_DEV(device); 68 int32_t error; 69 70 /* set our most pessimistic default mode */ 71 scp->mode[ATA_DEV(device)] = ATA_PIO; 72 73 if (!scp->bmaddr) 74 return; 75 76 /* if simplex controller, only allow DMA on primary channel */ 77 if (scp->unit == 1) { 78 outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 79 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 80 if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 81 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 82 return; 83 } 84 } 85 86 if (!scp->dmatab[ATA_DEV(device)]) { 87 void *dmatab; 88 89 if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) 90 return; 91 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 92 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 93 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 94 free(dmatab, M_DEVBUF); 95 return; 96 } 97 scp->dmatab[ATA_DEV(device)] = dmatab; 98 } 99 100 switch (scp->chiptype) { 101 102 case 0x71118086: /* Intel PIIX4 */ 103 case 0x71998086: /* Intel PIIX4e */ 104 case 0x24118086: /* Intel ICH */ 105 case 0x24218086: /* Intel ICH0 */ 106 if (udmamode >= 2) { 107 int32_t mask48, new48; 108 109 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 110 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 111 if (bootverbose) 112 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 113 (error) ? "failed" : "success", 114 (scp->chiptype == 0x24118086) ? "ICH" : 115 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 116 if (!error) { 117 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 118 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 119 pci_write_config(scp->dev, 0x48, 120 (pci_read_config(scp->dev, 0x48, 4) & 121 ~mask48) | new48, 4); 122 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 123 return; 124 } 125 } 126 /* FALLTHROUGH */ 127 128 case 0x70108086: /* Intel PIIX3 */ 129 if (wdmamode >= 2 && apiomode >= 4) { 130 int32_t mask40, new40, mask44, new44; 131 132 /* if SITRE not set doit for both channels */ 133 if (!((pci_read_config(scp->dev, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 134 new40 = pci_read_config(scp->dev, 0x40, 4); 135 new44 = pci_read_config(scp->dev, 0x44, 4); 136 if (!(new40 & 0x00004000)) { 137 new44 &= ~0x0000000f; 138 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 139 } 140 if (!(new40 & 0x40000000)) { 141 new44 &= ~0x000000f0; 142 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 143 } 144 new40 |= 0x40004000; 145 pci_write_config(scp->dev, 0x40, new40, 4); 146 pci_write_config(scp->dev, 0x44, new44, 4); 147 } 148 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 149 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 150 if (bootverbose) 151 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 152 (error) ? "failed" : "success", 153 (scp->chiptype == 0x70108086) ? "PIIX3" : 154 (scp->chiptype == 0x24118086) ? "ICH" : 155 (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 156 if (!error) { 157 if (device == ATA_MASTER) { 158 mask40 = 0x0000330f; 159 new40 = 0x00002307; 160 mask44 = 0; 161 new44 = 0; 162 } 163 else { 164 mask40 = 0x000000f0; 165 new40 = 0x00000070; 166 mask44 = 0x0000000f; 167 new44 = 0x0000000b; 168 } 169 if (scp->unit) { 170 mask40 <<= 16; 171 new40 <<= 16; 172 mask44 <<= 4; 173 new44 <<= 4; 174 } 175 pci_write_config(scp->dev, 0x40, 176 (pci_read_config(scp->dev, 0x40, 4) & ~mask40)| 177 new40, 4); 178 pci_write_config(scp->dev, 0x44, 179 (pci_read_config(scp->dev, 0x44, 4) & ~mask44)| 180 new44, 4); 181 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 182 return; 183 } 184 } 185 /* we could set PIO mode timings, but we assume the BIOS did that */ 186 break; 187 188 case 0x12308086: /* Intel PIIX */ 189 if (wdmamode >= 2 && apiomode >= 4) { 190 int32_t word40; 191 192 word40 = pci_read_config(scp->dev, 0x40, 4); 193 word40 >>= scp->unit * 16; 194 195 /* Check for timing config usable for DMA on controller */ 196 if (!((word40 & 0x3300) == 0x2300 && 197 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 198 break; 199 200 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 201 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 202 if (bootverbose) 203 ata_printf(scp, device, 204 "%s setting up WDMA2 mode on PIIX chip\n", 205 (error) ? "failed" : "success"); 206 if (!error) { 207 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 208 return; 209 } 210 } 211 break; 212 213 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 214 /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 215 if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 216 ata_printf(scp, device, 217 "Aladdin: two atapi devices on this channel, no DMA\n"); 218 break; 219 } 220 if (udmamode >= 2) { 221 int32_t word54 = pci_read_config(scp->dev, 0x54, 4); 222 223 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 224 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 225 if (bootverbose) 226 ata_printf(scp, device, 227 "%s setting up UDMA2 mode on Aladdin chip\n", 228 (error) ? "failed" : "success"); 229 if (!error) { 230 word54 |= 0x5555; 231 word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2))); 232 pci_write_config(scp->dev, 0x54, word54, 4); 233 pci_write_config(scp->dev, 0x53, 234 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 235 scp->flags |= ATA_ATAPI_DMA_RO; 236 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 237 return; 238 } 239 } 240 if (wdmamode >= 2 && apiomode >= 4) { 241 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 242 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 243 if (bootverbose) 244 ata_printf(scp, device, 245 "%s setting up WDMA2 mode on Aladdin chip\n", 246 (error) ? "failed" : "success"); 247 if (!error) { 248 pci_write_config(scp->dev, 0x53, 249 pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 250 scp->flags |= ATA_ATAPI_DMA_RO; 251 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 252 return; 253 } 254 } 255 /* we could set PIO mode timings, but we assume the BIOS did that */ 256 break; 257 258 case 0x06861106: /* VIA 82C686 */ 259 if (udmamode >= 4) { 260 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 261 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 262 if (bootverbose) 263 ata_printf(scp, device, 264 "%s setting up UDMA4 mode on VIA chip\n", 265 (error) ? "failed" : "success"); 266 if (!error) { 267 pci_write_config(scp->dev, 0x53 - devno, 0xe8, 1); 268 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 269 return; 270 } 271 } 272 if (udmamode >= 2) { 273 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 274 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 275 if (bootverbose) 276 ata_printf(scp, device, 277 "%s setting up UDMA2 mode on VIA chip\n", 278 (error) ? "failed" : "success"); 279 if (!error) { 280 pci_write_config(scp->dev, 0x53 - devno, 0xea, 1); 281 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 282 return; 283 } 284 } 285 goto via_generic; 286 287 case 0x74091022: /* AMD 756 */ 288 if (udmamode >= 4) { 289 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 290 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 291 if (bootverbose) 292 ata_printf(scp, device, 293 "%s setting up UDMA4 mode on AMD chip\n", 294 (error) ? "failed" : "success"); 295 if (!error) { 296 pci_write_config(scp->dev, 0x53 - devno, 0xc3, 1); 297 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 298 return; 299 } 300 } 301 /* FALLTHROUGH */ 302 303 case 0x05961106: /* VIA 82C596 */ 304 case 0x05861106: /* VIA 82C586 */ 305 306 /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */ 307 if ((udmamode >= 2 && scp->chiptype == 0x05861106 && 308 pci_read_config(scp->dev, 0x08, 1) >= 0x01) || 309 (udmamode >= 2 && scp->chiptype == 0x05961106) || 310 (udmamode >= 2 && scp->chiptype == 0x74091022)) { 311 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 312 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 313 if (bootverbose) 314 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 315 (error) ? "failed" : "success", 316 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 317 if (!error) { 318 pci_write_config(scp->dev, 0x53 - devno, 0xc0, 1); 319 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 320 return; 321 } 322 } 323 /* FALLTHROUGH */ 324 325 case 0x05711106: /* VIA 82C571 */ 326via_generic: 327 if (wdmamode >= 2 && apiomode >= 4) { 328 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 329 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 330 if (bootverbose) 331 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 332 (error) ? "failed" : "success", 333 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 334 if (!error) { 335 pci_write_config(scp->dev, 0x53 - devno, 0x82, 1); 336 pci_write_config(scp->dev, 0x4b - devno, 0x31, 1); 337 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 338 return; 339 } 340 } 341 /* we could set PIO mode timings, but we assume the BIOS did that */ 342 break; 343 344 case 0x55131039: /* SiS 5591 */ 345 if (udmamode >= 2) { 346 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 347 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 348 if (bootverbose) 349 ata_printf(scp, device, 350 "%s setting up UDMA2 mode on SiS chip\n", 351 (error) ? "failed" : "success"); 352 if (!error) { 353 pci_write_config(scp->dev, 0x40 + (devno << 1), 0xa301, 2); 354 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 355 return; 356 } 357 } 358 if (wdmamode >=2 && apiomode >= 4) { 359 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 360 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 361 if (bootverbose) 362 ata_printf(scp, device, 363 "%s setting up WDMA2 mode on SiS chip\n", 364 (error) ? "failed" : "success"); 365 if (!error) { 366 pci_write_config(scp->dev, 0x40 + (devno << 1), 0x0301, 2); 367 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 368 return; 369 } 370 } 371 /* we could set PIO mode timings, but we assume the BIOS did that */ 372 break; 373 374 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 375 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ 376 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 377 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 378 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 379 break; 380 381 if (udmamode >=4 && scp->chiptype == 0x4d38105a && 382 !(pci_read_config(scp->dev, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 383 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 384 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 385 if (bootverbose) 386 ata_printf(scp, device, 387 "%s setting up UDMA4 mode on Promise chip\n", 388 (error) ? "failed" : "success"); 389 if (!error) { 390 promise_timing(scp, devno, ATA_UDMA4); 391 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 392 return; 393 } 394 } 395 if (udmamode >= 2) { 396 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 397 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 398 if (bootverbose) 399 ata_printf(scp, device, 400 "%s setting up UDMA2 mode on Promise chip\n", 401 (error) ? "failed" : "success"); 402 if (!error) { 403 promise_timing(scp, devno, ATA_UDMA2); 404 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 405 return; 406 } 407 } 408 if (wdmamode >= 2 && apiomode >= 4) { 409 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 410 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 411 if (bootverbose) 412 ata_printf(scp, device, 413 "%s setting up WDMA2 mode on Promise chip\n", 414 (error) ? "failed" : "success"); 415 if (!error) { 416 promise_timing(scp, devno, ATA_WDMA2); 417 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 418 return; 419 } 420 } 421 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 422 ata_pio2mode(apiomode), 423 ATA_C_F_SETXFER, ATA_WAIT_READY); 424 if (bootverbose) 425 ata_printf(scp, device, 426 "%s setting up PIO%d mode on Promise chip\n", 427 (error) ? "failed" : "success", 428 (apiomode >= 0) ? apiomode : 0); 429 promise_timing(scp, devno, ata_pio2mode(apiomode)); 430 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 431 return; 432 433 case 0x00041103: /* HighPoint HPT366 controller */ 434 /* no ATAPI devices for now */ 435 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 436 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 437 break; 438 439 if (udmamode >=4 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) { 440 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 441 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 442 if (bootverbose) 443 ata_printf(scp, device, 444 "%s setting up UDMA4 mode on HPT366 chip\n", 445 (error) ? "failed" : "success"); 446 if (!error) { 447 hpt366_timing(scp, devno, ATA_UDMA4); 448 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 449 return; 450 } 451 } 452 if (udmamode >= 2) { 453 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 454 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 455 if (bootverbose) 456 ata_printf(scp, device, 457 "%s setting up UDMA2 mode on HPT366 chip\n", 458 (error) ? "failed" : "success"); 459 if (!error) { 460 hpt366_timing(scp, devno, ATA_UDMA2); 461 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 462 return; 463 } 464 } 465 if (wdmamode >= 2 && apiomode >= 4) { 466 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 467 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 468 if (bootverbose) 469 ata_printf(scp, device, 470 "%s setting up WDMA2 mode on HPT366 chip\n", 471 (error) ? "failed" : "success"); 472 if (!error) { 473 hpt366_timing(scp, devno, ATA_WDMA2); 474 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 475 return; 476 } 477 } 478 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 479 ata_pio2mode(apiomode), 480 ATA_C_F_SETXFER, ATA_WAIT_READY); 481 if (bootverbose) 482 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n", 483 (error) ? "failed" : "success", 484 (apiomode >= 0) ? apiomode : 0); 485 hpt366_timing(scp, devno, ata_pio2mode(apiomode)); 486 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 487 return; 488 489 default: /* unknown controller chip */ 490 /* better not try generic DMA on ATAPI devices it almost never works */ 491 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 492 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 493 break; 494 495 /* if controller says its setup for DMA take the easy way out */ 496 /* the downside is we dont know what DMA mode we are in */ 497 if ((udmamode >= 0 || wdmamode > 1) && 498 (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 499 ((device==ATA_MASTER) ? 500 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 501 scp->mode[ATA_DEV(device)] = ATA_DMA; 502 return; 503 } 504 505 /* well, we have no support for this, but try anyways */ 506 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 507 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 508 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 509 if (bootverbose) 510 ata_printf(scp, device, 511 "%s setting up WDMA2 mode on generic chip\n", 512 (error) ? "failed" : "success"); 513 if (!error) { 514 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 515 return; 516 } 517 } 518 } 519 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 520 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 521 if (bootverbose) 522 ata_printf(scp, device, "%s setting up PIO%d mode on generic chip\n", 523 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 524 if (!error) 525 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 526 else 527 if (bootverbose) 528 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 529} 530 531int32_t 532ata_dmasetup(struct ata_softc *scp, int32_t device, 533 int8_t *data, int32_t count, int32_t flags) 534{ 535 struct ata_dmaentry *dmatab; 536 u_int32_t dma_count, dma_base; 537 int32_t i = 0; 538 539 if (((uintptr_t)data & 1) || (count & 1)) 540 return -1; 541 542 if (!count) { 543 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 544 return -1; 545 } 546 547 dmatab = scp->dmatab[ATA_DEV(device)]; 548 dma_base = vtophys(data); 549 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 550 data += dma_count; 551 count -= dma_count; 552 553 while (count) { 554 dmatab[i].base = dma_base; 555 dmatab[i].count = (dma_count & 0xffff); 556 i++; 557 if (i >= ATA_DMA_ENTRIES) { 558 ata_printf(scp, device, "too many segments in DMA table\n"); 559 return -1; 560 } 561 dma_base = vtophys(data); 562 dma_count = min(count, PAGE_SIZE); 563 data += min(count, PAGE_SIZE); 564 count -= min(count, PAGE_SIZE); 565 } 566 dmatab[i].base = dma_base; 567 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 568 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 569 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0); 570 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 571 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 572 return 0; 573} 574 575void 576ata_dmastart(struct ata_softc *scp) 577{ 578 scp->flags |= ATA_DMA_ACTIVE; 579 outb(scp->bmaddr + ATA_BMCMD_PORT, 580 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 581} 582 583int32_t 584ata_dmadone(struct ata_softc *scp) 585{ 586 outb(scp->bmaddr + ATA_BMCMD_PORT, 587 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 588 scp->flags &= ~ATA_DMA_ACTIVE; 589 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 590} 591 592int32_t 593ata_dmastatus(struct ata_softc *scp) 594{ 595 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 596} 597 598static void 599promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 600{ 601 u_int32_t timing = 0; 602 struct promise_timing { 603 u_int8_t pa:4; 604 u_int8_t prefetch:1; 605 u_int8_t iordy:1; 606 u_int8_t errdy:1; 607 u_int8_t syncin:1; 608 u_int8_t pb:5; 609 u_int8_t mb:3; 610 u_int8_t mc:4; 611 u_int8_t dmaw:1; 612 u_int8_t dmar:1; 613 u_int8_t iordyp:1; 614 u_int8_t dmarqp:1; 615 u_int8_t reserved:8; 616 } *t = (struct promise_timing*)&timing; 617 618 t->iordy = 1; t->iordyp = 1; 619 if (mode >= ATA_DMA) { 620 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 621 } 622 623 switch (scp->chiptype) { 624 case 0x4d33105a: /* Promise 33's */ 625 switch (mode) { 626 default: 627 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 628 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 629 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 630 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 631 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 632 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 633 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 634 } 635 break; 636 637 case 0x4d38105a: /* Promise 66's */ 638 switch (mode) { 639 default: 640 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 641 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 642 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 643 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 644 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 645 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 646 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 647 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 648 } 649 break; 650 } 651 pci_write_config(scp->dev, 0x60 + (devno << 2), timing, 4); 652} 653 654static void 655hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 656{ 657 u_int32_t timing; 658 659 switch (pci_read_config(scp->dev, 0x41 + (devno << 2), 1)) { 660 case 0x85: /* 25Mhz */ 661 switch (mode) { 662 case ATA_PIO0: timing = 0xc0d08585; break; 663 case ATA_PIO1: timing = 0xc0d08572; break; 664 case ATA_PIO2: timing = 0xc0ca8542; break; 665 case ATA_PIO3: timing = 0xc0ca8532; break; 666 case ATA_PIO4: timing = 0xc0ca8521; break; 667 case ATA_WDMA2: timing = 0xa0ca8521; break; 668 case ATA_UDMA2: timing = 0x90cf8521; break; 669 case ATA_UDMA4: timing = 0x90c98521; break; 670 default: timing = 0x01208585; 671 } 672 break; 673 default: 674 case 0xa7: /* 33MHz */ 675 switch (mode) { 676 case ATA_PIO0: timing = 0xc0d0a7aa; break; 677 case ATA_PIO1: timing = 0xc0d0a7a3; break; 678 case ATA_PIO2: timing = 0xc0d0a753; break; 679 case ATA_PIO3: timing = 0xc0c8a742; break; 680 case ATA_PIO4: timing = 0xc0c8a731; break; 681 case ATA_WDMA2: timing = 0xa0c8a731; break; 682 case ATA_UDMA2: timing = 0x90caa731; break; 683 case ATA_UDMA4: timing = 0x90c9a731; break; 684 default: timing = 0x0120a7a7; 685 } 686 break; 687 case 0xd9: /* 40Mhz */ 688 switch (mode) { 689 case ATA_PIO0: timing = 0xc018d9d9; break; 690 case ATA_PIO1: timing = 0xc010d9c7; break; 691 case ATA_PIO2: timing = 0xc010d997; break; 692 case ATA_PIO3: timing = 0xc010d974; break; 693 case ATA_PIO4: timing = 0xc008d963; break; 694 case ATA_WDMA2: timing = 0xa008d943; break; 695 case ATA_UDMA2: timing = 0x900bd943; break; 696 case ATA_UDMA4: timing = 0x900fd943; break; 697 default: timing = 0x0120d9d9; 698 } 699 } 700 pci_write_config(scp->dev, 0x40 + (devno << 2) , (timing & ~0x80000000), 4); 701} 702 703#else /* NPCI > 0 */ 704 705void 706ata_dmainit(struct ata_softc *scp, int32_t device, 707 int32_t piomode, int32_t wdmamode, int32_t udmamode) 708{ 709} 710 711int32_t 712ata_dmasetup(struct ata_softc *scp, int32_t device, 713 int8_t *data, int32_t count, int32_t flags) 714{ 715 return -1; 716} 717 718void 719ata_dmastart(struct ata_softc *scp) 720{ 721} 722 723int32_t 724ata_dmadone(struct ata_softc *scp) 725{ 726 return -1; 727} 728 729int32_t 730ata_dmastatus(struct ata_softc *scp) 731{ 732 return -1; 733} 734 735#endif /* NPCI > 0 */ 736