ata-dma.c revision 93674
1/*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 93674 2002-04-02 16:45:06Z sos $ 29 */ 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/ata.h> 34#include <sys/bio.h> 35#include <sys/malloc.h> 36#include <sys/bus.h> 37#include <sys/disk.h> 38#include <sys/devicestat.h> 39#include <vm/vm.h> 40#include <vm/pmap.h> 41#include <pci/pcivar.h> 42#include <machine/bus.h> 43#include <sys/rman.h> 44#include <dev/ata/ata-all.h> 45 46/* prototypes */ 47static void cyrix_timing(struct ata_channel *, int, int); 48static void promise_timing(struct ata_channel *, int, int); 49static void hpt_timing(struct ata_channel *, int, int); 50static int hpt_cable80(struct ata_channel *); 51 52/* misc defines */ 53#ifdef __alpha__ 54#undef vtophys 55#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 56#endif 57#define ATAPI_DEVICE(ch, device) \ 58 ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || \ 59 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)) 60 61void * 62ata_dmaalloc(struct ata_channel *ch, int device) 63{ 64 void *dmatab; 65 66 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 67 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 68 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 69 ata_printf(ch, device, "dmatab crosses page boundary, no DMA\n"); 70 free(dmatab, M_DEVBUF); 71 dmatab = NULL; 72 } 73 } 74 return dmatab; 75} 76 77void 78ata_dmainit(struct ata_channel *ch, int device, 79 int apiomode, int wdmamode, int udmamode) 80{ 81 struct ata_device *atadev = &ch->device[ATA_DEV(device)]; 82 device_t parent = device_get_parent(ch->dev); 83 int devno = (ch->unit << 1) + ATA_DEV(device); 84 int error; 85 86 /* set our most pessimistic default mode */ 87 atadev->mode = ATA_PIO; 88 89 if (!ch->r_bmio) 90 return; 91 92 /* if simplex controller, only allow DMA on primary channel */ 93 if (ch->unit == 1) { 94 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 95 ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & 96 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 97 if (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 98 ata_prtdev(atadev, "simplex device, DMA on primary only\n"); 99 return; 100 } 101 } 102 103 /* DMA engine address alignment is usually 1 word (2 bytes) */ 104 ch->alignment = 0x1; 105 106#if 1 107 if (udmamode > 2 && !ch->device[ATA_DEV(device)].param->hwres_cblid) { 108 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n"); 109 udmamode = 2; 110 } 111#endif 112 switch (ch->chiptype) { 113 114 case 0x248a8086: /* Intel ICH3 mobile */ 115 case 0x248b8086: /* Intel ICH3 */ 116 case 0x244a8086: /* Intel ICH2 mobile */ 117 case 0x244b8086: /* Intel ICH2 */ 118 if (udmamode >= 5) { 119 int32_t mask48, new48; 120 int16_t word54; 121 122 word54 = pci_read_config(parent, 0x54, 2); 123 if (word54 & (0x10 << devno)) { 124 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 125 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 126 if (bootverbose) 127 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n", 128 (error) ? "failed" : "success"); 129 if (!error) { 130 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 131 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 132 pci_write_config(parent, 0x48, 133 (pci_read_config(parent, 0x48, 4) & 134 ~mask48) | new48, 4); 135 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 136 atadev->mode = ATA_UDMA5; 137 return; 138 } 139 } 140 } 141 /* make sure eventual ATA100 mode from the BIOS is disabled */ 142 pci_write_config(parent, 0x54, 143 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 144 /* FALLTHROUGH */ 145 146 case 0x24118086: /* Intel ICH */ 147 case 0x76018086: /* Intel ICH */ 148 if (udmamode >= 4) { 149 int32_t mask48, new48; 150 int16_t word54; 151 152 word54 = pci_read_config(parent, 0x54, 2); 153 if (word54 & (0x10 << devno)) { 154 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 155 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 156 if (bootverbose) 157 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n", 158 (error) ? "failed" : "success"); 159 if (!error) { 160 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 161 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 162 pci_write_config(parent, 0x48, 163 (pci_read_config(parent, 0x48, 4) & 164 ~mask48) | new48, 4); 165 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 166 atadev->mode = ATA_UDMA4; 167 return; 168 } 169 } 170 } 171 /* make sure eventual ATA66 mode from the BIOS is disabled */ 172 pci_write_config(parent, 0x54, 173 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 174 /* FALLTHROUGH */ 175 176 case 0x71118086: /* Intel PIIX4 */ 177 case 0x84CA8086: /* Intel PIIX4 */ 178 case 0x71998086: /* Intel PIIX4e */ 179 case 0x24218086: /* Intel ICH0 */ 180 if (udmamode >= 2) { 181 int32_t mask48, new48; 182 183 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 184 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 185 if (bootverbose) 186 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n", 187 (error) ? "failed" : "success"); 188 if (!error) { 189 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 190 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 191 pci_write_config(parent, 0x48, 192 (pci_read_config(parent, 0x48, 4) & 193 ~mask48) | new48, 4); 194 atadev->mode = ATA_UDMA2; 195 return; 196 } 197 } 198 /* make sure eventual ATA33 mode from the BIOS is disabled */ 199 pci_write_config(parent, 0x48, 200 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 201 /* FALLTHROUGH */ 202 203 case 0x70108086: /* Intel PIIX3 */ 204 if (wdmamode >= 2 && apiomode >= 4) { 205 int32_t mask40, new40, mask44, new44; 206 207 /* if SITRE not set doit for both channels */ 208 if (!((pci_read_config(parent,0x40,4)>>(ch->unit<<8))&0x4000)) { 209 new40 = pci_read_config(parent, 0x40, 4); 210 new44 = pci_read_config(parent, 0x44, 4); 211 if (!(new40 & 0x00004000)) { 212 new44 &= ~0x0000000f; 213 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 214 } 215 if (!(new40 & 0x40000000)) { 216 new44 &= ~0x000000f0; 217 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 218 } 219 new40 |= 0x40004000; 220 pci_write_config(parent, 0x40, new40, 4); 221 pci_write_config(parent, 0x44, new44, 4); 222 } 223 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 224 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 225 if (bootverbose) 226 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 227 (error) ? "failed" : "success"); 228 if (!error) { 229 if (device == ATA_MASTER) { 230 mask40 = 0x0000330f; 231 new40 = 0x00002307; 232 mask44 = 0; 233 new44 = 0; 234 } 235 else { 236 mask40 = 0x000000f0; 237 new40 = 0x00000070; 238 mask44 = 0x0000000f; 239 new44 = 0x0000000b; 240 } 241 if (ch->unit) { 242 mask40 <<= 16; 243 new40 <<= 16; 244 mask44 <<= 4; 245 new44 <<= 4; 246 } 247 pci_write_config(parent, 0x40, 248 (pci_read_config(parent, 0x40, 4) & ~mask40)| 249 new40, 4); 250 pci_write_config(parent, 0x44, 251 (pci_read_config(parent, 0x44, 4) & ~mask44)| 252 new44, 4); 253 atadev->mode = ATA_WDMA2; 254 return; 255 } 256 } 257 /* we could set PIO mode timings, but we assume the BIOS did that */ 258 break; 259 260 case 0x12308086: /* Intel PIIX */ 261 if (wdmamode >= 2 && apiomode >= 4) { 262 int32_t word40; 263 264 word40 = pci_read_config(parent, 0x40, 4); 265 word40 >>= ch->unit * 16; 266 267 /* Check for timing config usable for DMA on controller */ 268 if (!((word40 & 0x3300) == 0x2300 && 269 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 270 break; 271 272 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 273 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 274 if (bootverbose) 275 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 276 (error) ? "failed" : "success"); 277 if (!error) { 278 atadev->mode = ATA_WDMA2; 279 return; 280 } 281 } 282 break; 283 284 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 285 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 286 if (pci_get_revid(parent) < 0xc2 && 287 ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) { 288 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n"); 289 break; 290 } 291 if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) { 292 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 293 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 294 if (bootverbose) 295 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n", 296 (error) ? "failed" : "success"); 297 if (!error) { 298 int32_t word54 = pci_read_config(parent, 0x54, 4); 299 300 pci_write_config(parent, 0x4b, 301 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 302 word54 &= ~(0x000f000f << (devno << 2)); 303 word54 |= (0x000f0005 << (devno << 2)); 304 pci_write_config(parent, 0x54, word54, 4); 305 pci_write_config(parent, 0x53, 306 pci_read_config(parent, 0x53, 1) | 0x03, 1); 307 atadev->mode = ATA_UDMA5; 308 return; 309 } 310 } 311 if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) { 312 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 313 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 314 if (bootverbose) 315 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n", 316 (error) ? "failed" : "success"); 317 if (!error) { 318 int32_t word54 = pci_read_config(parent, 0x54, 4); 319 320 pci_write_config(parent, 0x4b, 321 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 322 word54 &= ~(0x000f000f << (devno << 2)); 323 word54 |= (0x00080005 << (devno << 2)); 324 pci_write_config(parent, 0x54, word54, 4); 325 pci_write_config(parent, 0x53, 326 pci_read_config(parent, 0x53, 1) | 0x03, 1); 327 atadev->mode = ATA_UDMA4; 328 return; 329 } 330 } 331 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 332 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 333 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 334 if (bootverbose) 335 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n", 336 (error) ? "failed" : "success"); 337 if (!error) { 338 int32_t word54 = pci_read_config(parent, 0x54, 4); 339 340 word54 &= ~(0x000f000f << (devno << 2)); 341 word54 |= (0x000a0005 << (devno << 2)); 342 pci_write_config(parent, 0x54, word54, 4); 343 pci_write_config(parent, 0x53, 344 pci_read_config(parent, 0x53, 1) | 0x03, 1); 345 ch->flags |= ATA_ATAPI_DMA_RO; 346 atadev->mode = ATA_UDMA2; 347 return; 348 } 349 } 350 351 /* make sure eventual UDMA mode from the BIOS is disabled */ 352 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 353 ~(0x0008 << (devno << 2)), 2); 354 355 if (wdmamode >= 2 && apiomode >= 4) { 356 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 357 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 358 if (bootverbose) 359 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n", 360 (error) ? "failed" : "success"); 361 if (!error) { 362 pci_write_config(parent, 0x53, 363 pci_read_config(parent, 0x53, 1) | 0x03, 1); 364 ch->flags |= ATA_ATAPI_DMA_RO; 365 atadev->mode = ATA_WDMA2; 366 return; 367 } 368 } 369 pci_write_config(parent, 0x53, 370 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 371 /* we could set PIO mode timings, but we assume the BIOS did that */ 372 break; 373 374 case 0x74411022: /* AMD 768 */ 375 case 0x74111022: /* AMD 766 */ 376 if (udmamode >= 5) { 377 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 378 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 379 if (bootverbose) 380 ata_prtdev(atadev, "%s setting UDMA5 on AMD chip\n", 381 (error) ? "failed" : "success"); 382 if (!error) { 383 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 384 atadev->mode = ATA_UDMA5; 385 return; 386 } 387 } 388 /* FALLTHROUGH */ 389 390 case 0x74091022: /* AMD 756 */ 391 if (udmamode >= 4) { 392 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 393 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 394 if (bootverbose) 395 ata_prtdev(atadev, "%s setting UDMA4 on AMD chip\n", 396 (error) ? "failed" : "success"); 397 if (!error) { 398 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 399 atadev->mode = ATA_UDMA4; 400 return; 401 } 402 } 403 goto via_82c586; 404 405 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 , 8231, 8233 */ 406 { 407 int via_modes[4][7] = { 408 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* ATA33 */ 409 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* ATA66 */ 410 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* ATA100 */ 411 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }}; /* ATA133 */ 412 int *reg_val = NULL; 413 414 if (ata_find_dev(parent, 0x31471106, 0)) { /* 8233a */ 415 udmamode = imin(udmamode, 6); 416 reg_val = via_modes[3]; 417 } 418 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */ 419 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */ 420 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */ 421 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */ 422 udmamode = imin(udmamode, 5); 423 reg_val = via_modes[2]; 424 } 425 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */ 426 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 427 udmamode = imin(udmamode, 4); 428 reg_val = via_modes[1]; 429 } 430 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */ 431 udmamode = imin(udmamode, 2); 432 reg_val = via_modes[1]; 433 } 434 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 435 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 436via_82c586: 437 udmamode = imin(udmamode, 2); 438 reg_val = via_modes[0]; 439 } 440 else 441 udmamode = 0; 442 443 if (udmamode >= 6) { 444 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 445 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 446 if (bootverbose) 447 ata_prtdev(atadev, "%s setting UDMA6 on VIA chip\n", 448 (error) ? "failed" : "success"); 449 if (!error) { 450 pci_write_config(parent, 0x53 - devno, reg_val[6], 1); 451 atadev->mode = ATA_UDMA6; 452 return; 453 } 454 } 455 if (udmamode >= 5) { 456 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 457 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 458 if (bootverbose) 459 ata_prtdev(atadev, "%s setting UDMA5 on VIA chip\n", 460 (error) ? "failed" : "success"); 461 if (!error) { 462 pci_write_config(parent, 0x53 - devno, reg_val[5], 1); 463 atadev->mode = ATA_UDMA5; 464 return; 465 } 466 } 467 if (udmamode >= 4) { 468 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 469 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 470 if (bootverbose) 471 ata_prtdev(atadev, "%s setting UDMA4 on VIA chip\n", 472 (error) ? "failed" : "success"); 473 if (!error) { 474 pci_write_config(parent, 0x53 - devno, reg_val[4], 1); 475 atadev->mode = ATA_UDMA4; 476 return; 477 } 478 } 479 if (udmamode >= 2) { 480 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 481 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 482 if (bootverbose) 483 ata_prtdev(atadev, "%s setting UDMA2 on VIA chip\n", 484 (error) ? "failed" : "success"); 485 if (!error) { 486 pci_write_config(parent, 0x53 - devno, reg_val[2], 1); 487 atadev->mode = ATA_UDMA2; 488 return; 489 } 490 } 491 492 } 493 if (wdmamode >= 2 && apiomode >= 4) { 494 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 495 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 496 if (bootverbose) 497 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n", 498 (error) ? "failed" : "success", 499 (ch->chiptype == 0x74091022) ? "AMD" : "VIA"); 500 if (!error) { 501 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 502 pci_write_config(parent, 0x4b - devno, 0x31, 1); 503 atadev->mode = ATA_WDMA2; 504 return; 505 } 506 } 507 /* we could set PIO mode timings, but we assume the BIOS did that */ 508 break; 509 510 case 0x55131039: /* SiS 5591 */ 511 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */ 512 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */ 513 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */ 514 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */ 515 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */ 516 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */ 517 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */ 518 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */ 519 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */ 520 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */ 521 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */ 522 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */ 523 int8_t reg = 0x40 + (devno << 1); 524 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 525 526 if (udmamode >= 5) { 527 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 528 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 529 if (bootverbose) 530 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n", 531 (error) ? "failed" : "success"); 532 if (!error) { 533 pci_write_config(parent, reg, val | 0x8000, 2); 534 atadev->mode = ATA_UDMA5; 535 return; 536 } 537 } 538 if (udmamode >= 4) { 539 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 540 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 541 if (bootverbose) 542 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 543 (error) ? "failed" : "success"); 544 if (!error) { 545 pci_write_config(parent, reg, val | 0x9000, 2); 546 atadev->mode = ATA_UDMA4; 547 return; 548 } 549 } 550 if (udmamode >= 2) { 551 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 552 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 553 if (bootverbose) 554 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 555 (error) ? "failed" : "success"); 556 if (!error) { 557 pci_write_config(parent, reg, val | 0xb000, 2); 558 atadev->mode = ATA_UDMA2; 559 return; 560 } 561 } 562 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */ 563 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */ 564 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */ 565 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */ 566 int8_t reg = 0x40 + (devno << 1); 567 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 568 569 if (udmamode >= 4) { 570 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 571 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 572 if (bootverbose) 573 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 574 (error) ? "failed" : "success"); 575 if (!error) { 576 pci_write_config(parent, reg, val | 0x9000, 2); 577 atadev->mode = ATA_UDMA4; 578 return; 579 } 580 } 581 if (udmamode >= 2) { 582 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 583 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 584 if (bootverbose) 585 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 586 (error) ? "failed" : "success"); 587 if (!error) { 588 pci_write_config(parent, reg, val | 0xa000, 2); 589 atadev->mode = ATA_UDMA2; 590 return; 591 } 592 } 593 } else if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 594 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 595 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 596 if (bootverbose) 597 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 598 (error) ? "failed" : "success"); 599 if (!error) { 600 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 601 atadev->mode = ATA_UDMA2; 602 return; 603 } 604 } 605 if (wdmamode >=2 && apiomode >= 4) { 606 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 607 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 608 if (bootverbose) 609 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n", 610 (error) ? "failed" : "success"); 611 if (!error) { 612 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 613 atadev->mode = ATA_WDMA2; 614 return; 615 } 616 } 617 /* we could set PIO mode timings, but we assume the BIOS did that */ 618 break; 619 620 case 0x06491095: /* CMD 649 ATA100 controller */ 621 if (udmamode >= 5) { 622 u_int8_t umode; 623 624 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 625 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 626 if (bootverbose) 627 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n", 628 (error) ? "failed" : "success"); 629 if (!error) { 630 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1); 631 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 632 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 633 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1); 634 atadev->mode = ATA_UDMA5; 635 return; 636 } 637 } 638 /* FALLTHROUGH */ 639 640 case 0x06481095: /* CMD 648 ATA66 controller */ 641 if (udmamode >= 4) { 642 u_int8_t umode; 643 644 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 645 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 646 if (bootverbose) 647 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n", 648 (error) ? "failed" : "success"); 649 if (!error) { 650 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1); 651 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 652 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 653 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1); 654 atadev->mode = ATA_UDMA4; 655 return; 656 } 657 } 658 if (udmamode >= 2) { 659 u_int8_t umode; 660 661 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 662 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 663 if (bootverbose) 664 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n", 665 (error) ? "failed" : "success"); 666 if (!error) { 667 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1); 668 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 669 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 670 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1); 671 atadev->mode = ATA_UDMA2; 672 return; 673 } 674 } 675 /* make sure eventual UDMA mode from the BIOS is disabled */ 676 pci_write_config(parent, ch->unit ? 0x7b : 0x73, 677 pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1)& 678 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 679 /* FALLTHROUGH */ 680 681 case 0x06461095: /* CMD 646 ATA controller */ 682 if (wdmamode >= 2 && apiomode >= 4) { 683 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 684 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 685 if (bootverbose) 686 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n", 687 error ? "failed" : "success"); 688 if (!error) { 689 int32_t offset = (devno < 3) ? (devno << 1) : 7; 690 691 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 692 atadev->mode = ATA_WDMA2; 693 return; 694 } 695 } 696 /* we could set PIO mode timings, but we assume the BIOS did that */ 697 break; 698 699 case 0xc6931080: /* Cypress 82c693 ATA controller */ 700 if (wdmamode >= 2 && apiomode >= 4) { 701 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 702 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 703 if (bootverbose) 704 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n", 705 error ? "failed" : "success"); 706 if (!error) { 707 pci_write_config(ch->dev, ch->unit ? 0x4e:0x4c, 0x2020, 2); 708 atadev->mode = ATA_WDMA2; 709 return; 710 } 711 } 712 /* we could set PIO mode timings, but we assume the BIOS did that */ 713 break; 714 715 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 716 ch->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 717 if (udmamode >= 2) { 718 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 719 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 720 if (bootverbose) 721 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n", 722 (error) ? "failed" : "success"); 723 if (!error) { 724 cyrix_timing(ch, devno, ATA_UDMA2); 725 atadev->mode = ATA_UDMA2; 726 return; 727 } 728 } 729 if (wdmamode >= 2 && apiomode >= 4) { 730 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 731 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 732 if (bootverbose) 733 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n", 734 (error) ? "failed" : "success"); 735 if (!error) { 736 cyrix_timing(ch, devno, ATA_WDMA2); 737 atadev->mode = ATA_WDMA2; 738 return; 739 } 740 } 741 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 742 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 743 ATA_WAIT_READY); 744 if (bootverbose) 745 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n", 746 (error) ? "failed" : "success", 747 ata_mode2str(ATA_PIO0 + apiomode)); 748 cyrix_timing(ch, devno, ATA_PIO0 + apiomode); 749 atadev->mode = ATA_PIO0 + apiomode; 750 return; 751 752 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */ 753 if (udmamode >= 5 && pci_get_revid(parent) >= 0x92) { 754 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 755 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 756 if (bootverbose) 757 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n", 758 (error) ? "failed" : "success"); 759 if (!error) { 760 u_int16_t reg56; 761 762 pci_write_config(parent, 0x54, 763 pci_read_config(parent, 0x54, 1) | 764 (0x01 << devno), 1); 765 reg56 = pci_read_config(parent, 0x56, 2); 766 reg56 &= ~(0xf << (devno * 4)); 767 reg56 |= (0x5 << (devno * 4)); 768 pci_write_config(parent, 0x56, reg56, 2); 769 atadev->mode = ATA_UDMA5; 770 return; 771 } 772 } 773 if (udmamode >= 4) { 774 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 775 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 776 if (bootverbose) 777 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n", 778 (error) ? "failed" : "success"); 779 if (!error) { 780 u_int16_t reg56; 781 782 pci_write_config(parent, 0x54, 783 pci_read_config(parent, 0x54, 1) | 784 (0x01 << devno), 1); 785 reg56 = pci_read_config(parent, 0x56, 2); 786 reg56 &= ~(0xf << (devno * 4)); 787 reg56 |= (0x4 << (devno * 4)); 788 pci_write_config(parent, 0x56, reg56, 2); 789 atadev->mode = ATA_UDMA4; 790 return; 791 } 792 } 793 /* FALLTHROUGH */ 794 795 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 796 if (udmamode >= 2) { 797 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 798 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 799 if (bootverbose) 800 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n", 801 (error) ? "failed" : "success"); 802 if (!error) { 803 u_int16_t reg56; 804 805 pci_write_config(parent, 0x54, 806 pci_read_config(parent, 0x54, 1) | 807 (0x01 << devno), 1); 808 reg56 = pci_read_config(parent, 0x56, 2); 809 reg56 &= ~(0xf << (devno * 4)); 810 reg56 |= (0x2 << (devno * 4)); 811 pci_write_config(parent, 0x56, reg56, 2); 812 atadev->mode = ATA_UDMA2; 813 return; 814 } 815 } 816 if (wdmamode >= 2 && apiomode >= 4) { 817 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 818 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 819 if (bootverbose) 820 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n", 821 (error) ? "failed" : "success"); 822 if (!error) { 823 int offset = (ch->unit * 2) + (device == ATA_MASTER); 824 int word44 = pci_read_config(parent, 0x44, 4); 825 826 pci_write_config(parent, 0x54, 827 pci_read_config(parent, 0x54, 1) & 828 ~(0x01 << devno), 1); 829 word44 &= ~(0xff << (offset << 8)); 830 word44 |= (0x20 << (offset << 8)); 831 pci_write_config(parent, 0x44, 0x20, 4); 832 atadev->mode = ATA_WDMA2; 833 return; 834 } 835 } 836 /* we could set PIO mode timings, but we assume the BIOS did that */ 837 break; 838 839 case 0x4d69105a: /* Promise TX2 ATA133 controllers */ 840 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 841 if (udmamode >= 6 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 842 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 843 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 844 if (bootverbose) 845 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n", 846 (error) ? "failed" : "success"); 847 if (!error) { 848 atadev->mode = ATA_UDMA6; 849 return; 850 } 851 } 852 /* FALLTHROUGH */ 853 854 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 855 case 0x6268105a: /* Promise TX2 ATA100 controllers */ 856 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 857 if (udmamode >= 5 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 858 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 859 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 860 if (bootverbose) 861 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 862 (error) ? "failed" : "success"); 863 if (!error) { 864 atadev->mode = ATA_UDMA5; 865 return; 866 } 867 } 868 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 869 if (udmamode >= 4 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 870 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 871 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 872 if (bootverbose) 873 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 874 (error) ? "failed" : "success"); 875 if (!error) { 876 atadev->mode = ATA_UDMA4; 877 return; 878 } 879 } 880 if (udmamode >= 2) { 881 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 882 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 883 if (bootverbose) 884 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n", 885 (error) ? "failed" : "success"); 886 if (!error) { 887 atadev->mode = ATA_UDMA2; 888 return; 889 } 890 } 891 if (wdmamode >= 2 && apiomode >= 4) { 892 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 893 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 894 if (bootverbose) 895 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 896 (error) ? "failed" : "success"); 897 if (!error) { 898 atadev->mode = ATA_WDMA2; 899 return; 900 } 901 } 902 break; 903 904 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 905 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 906 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 && 907 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){ 908 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 909 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 910 if (bootverbose) 911 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 912 (error) ? "failed" : "success"); 913 if (!error) { 914 promise_timing(ch, devno, ATA_UDMA5); 915 atadev->mode = ATA_UDMA5; 916 return; 917 } 918 } 919 /* FALLTHROUGH */ 920 921 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 922 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 && 923 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){ 924 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 925 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 926 if (bootverbose) 927 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 928 (error) ? "failed" : "success"); 929 if (!error) { 930 promise_timing(ch, devno, ATA_UDMA4); 931 atadev->mode = ATA_UDMA4; 932 return; 933 } 934 } 935 /* FALLTHROUGH */ 936 937 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 938 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) { 939 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 940 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 941 if (bootverbose) 942 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n", 943 (error) ? "failed" : "success"); 944 if (!error) { 945 promise_timing(ch, devno, ATA_UDMA2); 946 atadev->mode = ATA_UDMA2; 947 return; 948 } 949 } 950 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) { 951 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 952 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 953 if (bootverbose) 954 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 955 (error) ? "failed" : "success"); 956 if (!error) { 957 promise_timing(ch, devno, ATA_WDMA2); 958 atadev->mode = ATA_WDMA2; 959 return; 960 } 961 } 962 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 963 ATA_PIO0 + apiomode, 964 ATA_C_F_SETXFER, ATA_WAIT_READY); 965 if (bootverbose) 966 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n", 967 (error) ? "failed" : "success", 968 (apiomode >= 0) ? apiomode : 0); 969 promise_timing(ch, devno, ATA_PIO0 + apiomode); 970 atadev->mode = ATA_PIO0 + apiomode; 971 return; 972 973 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 974 case 0x00051103: /* HighPoint HPT372 controllers */ 975 case 0x00081103: /* HighPoint HPT374 controllers */ 976 if (!ATAPI_DEVICE(ch, device) && udmamode >= 6 && hpt_cable80(ch) && 977 ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) || 978 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) || 979 (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07))) { 980 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 981 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 982 if (bootverbose) 983 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n", 984 (error) ? "failed" : "success"); 985 if (!error) { 986 hpt_timing(ch, devno, ATA_UDMA6); 987 atadev->mode = ATA_UDMA6; 988 return; 989 } 990 } 991 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 && hpt_cable80(ch) && 992 ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) || 993 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) || 994 (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07))) { 995 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 996 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 997 if (bootverbose) 998 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n", 999 (error) ? "failed" : "success"); 1000 if (!error) { 1001 hpt_timing(ch, devno, ATA_UDMA5); 1002 atadev->mode = ATA_UDMA5; 1003 return; 1004 } 1005 } 1006 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 && hpt_cable80(ch)) { 1007 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1008 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1009 if (bootverbose) 1010 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n", 1011 (error) ? "failed" : "success"); 1012 if (!error) { 1013 hpt_timing(ch, devno, ATA_UDMA4); 1014 atadev->mode = ATA_UDMA4; 1015 return; 1016 } 1017 } 1018 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) { 1019 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1020 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1021 if (bootverbose) 1022 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n", 1023 (error) ? "failed" : "success"); 1024 if (!error) { 1025 hpt_timing(ch, devno, ATA_UDMA2); 1026 atadev->mode = ATA_UDMA2; 1027 return; 1028 } 1029 } 1030 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) { 1031 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1032 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1033 if (bootverbose) 1034 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n", 1035 (error) ? "failed" : "success"); 1036 if (!error) { 1037 hpt_timing(ch, devno, ATA_WDMA2); 1038 atadev->mode = ATA_WDMA2; 1039 return; 1040 } 1041 } 1042 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1043 ATA_PIO0 + apiomode, 1044 ATA_C_F_SETXFER, ATA_WAIT_READY); 1045 if (bootverbose) 1046 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n", 1047 (error) ? "failed" : "success", 1048 (apiomode >= 0) ? apiomode : 0); 1049 hpt_timing(ch, devno, ATA_PIO0 + apiomode); 1050 atadev->mode = ATA_PIO0 + apiomode; 1051 return; 1052 1053 case 0x000116ca: /* Cenatek Rocket Drive controller */ 1054 if (wdmamode >= 0 && 1055 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & 1056 ((device==ATA_MASTER)?ATA_BMSTAT_DMA_MASTER:ATA_BMSTAT_DMA_SLAVE))) 1057 atadev->mode = ATA_DMA; 1058 else 1059 atadev->mode = ATA_PIO; 1060 return; 1061 1062 default: /* unknown controller chip */ 1063 /* better not try generic DMA on ATAPI devices it almost never works */ 1064 if ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || 1065 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE)) 1066 break; 1067 1068 /* if controller says its setup for DMA take the easy way out */ 1069 /* the downside is we dont know what DMA mode we are in */ 1070 if ((udmamode >= 0 || wdmamode >= 2) && 1071 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & 1072 ((device==ATA_MASTER) ? 1073 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 1074 atadev->mode = ATA_DMA; 1075 return; 1076 } 1077 1078 /* well, we have no support for this, but try anyways */ 1079 if ((wdmamode >= 2 && apiomode >= 4) && ch->r_bmio) { 1080 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1081 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1082 if (bootverbose) 1083 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n", 1084 (error) ? "failed" : "success"); 1085 if (!error) { 1086 atadev->mode = ATA_WDMA2; 1087 return; 1088 } 1089 } 1090 } 1091 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 1092 ATA_C_F_SETXFER, ATA_WAIT_READY); 1093 if (bootverbose) 1094 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n", 1095 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 1096 if (!error) 1097 atadev->mode = ATA_PIO0 + apiomode; 1098 else { 1099 if (bootverbose) 1100 ata_prtdev(atadev, "using PIO mode set by BIOS\n"); 1101 atadev->mode = ATA_PIO; 1102 } 1103} 1104 1105int 1106ata_dmasetup(struct ata_channel *ch, int device, struct ata_dmaentry *dmatab, 1107 caddr_t data, int32_t count) 1108{ 1109 u_int32_t dma_count, dma_base; 1110 int i = 0; 1111 1112 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) { 1113 ata_printf(ch, device, "non aligned DMA transfer attempted\n"); 1114 return -1; 1115 } 1116 1117 if (!count) { 1118 ata_printf(ch, device, "zero length DMA transfer attempted\n"); 1119 return -1; 1120 } 1121 1122 dma_base = vtophys(data); 1123 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 1124 data += dma_count; 1125 count -= dma_count; 1126 1127 while (count) { 1128 dmatab[i].base = dma_base; 1129 dmatab[i].count = (dma_count & 0xffff); 1130 i++; 1131 if (i >= ATA_DMA_ENTRIES) { 1132 ata_printf(ch, device, "too many segments in DMA table\n"); 1133 return -1; 1134 } 1135 dma_base = vtophys(data); 1136 dma_count = imin(count, PAGE_SIZE); 1137 data += imin(count, PAGE_SIZE); 1138 count -= imin(count, PAGE_SIZE); 1139 } 1140 dmatab[i].base = dma_base; 1141 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 1142 return 0; 1143} 1144 1145void 1146ata_dmastart(struct ata_channel *ch, int device, 1147 struct ata_dmaentry *dmatab, int dir) 1148{ 1149 ch->flags |= ATA_DMA_ACTIVE; 1150 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 1151 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1152 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1153 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) | 1154 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1155 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1156 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1157} 1158 1159int 1160ata_dmadone(struct ata_channel *ch) 1161{ 1162 int error; 1163 1164 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1165 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1166 ch->flags &= ~ATA_DMA_ACTIVE; 1167 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT); 1168 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1169 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1170 return error & ATA_BMSTAT_MASK; 1171} 1172 1173int 1174ata_dmastatus(struct ata_channel *ch) 1175{ 1176 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1177} 1178 1179static void 1180cyrix_timing(struct ata_channel *ch, int devno, int mode) 1181{ 1182 u_int32_t reg20 = 0x0000e132; 1183 u_int32_t reg24 = 0x00017771; 1184 1185 switch (mode) { 1186 case ATA_PIO0: reg20 = 0x0000e132; break; 1187 case ATA_PIO1: reg20 = 0x00018121; break; 1188 case ATA_PIO2: reg20 = 0x00024020; break; 1189 case ATA_PIO3: reg20 = 0x00032010; break; 1190 case ATA_PIO4: reg20 = 0x00040010; break; 1191 case ATA_WDMA2: reg24 = 0x00002020; break; 1192 case ATA_UDMA2: reg24 = 0x00911030; break; 1193 } 1194 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x20, reg20); 1195 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x24, reg24); 1196} 1197 1198static void 1199promise_timing(struct ata_channel *ch, int devno, int mode) 1200{ 1201 u_int32_t timing = 0; 1202 struct promise_timing { 1203 u_int8_t pa:4; 1204 u_int8_t prefetch:1; 1205 u_int8_t iordy:1; 1206 u_int8_t errdy:1; 1207 u_int8_t syncin:1; 1208 u_int8_t pb:5; 1209 u_int8_t mb:3; 1210 u_int8_t mc:4; 1211 u_int8_t dmaw:1; 1212 u_int8_t dmar:1; 1213 u_int8_t iordyp:1; 1214 u_int8_t dmarqp:1; 1215 u_int8_t reserved:8; 1216 } *t = (struct promise_timing*)&timing; 1217 1218 t->iordy = 1; t->iordyp = 1; 1219 if (mode >= ATA_DMA) { 1220 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1221 } 1222 1223 switch (ch->chiptype) { 1224 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1225 switch (mode) { 1226 default: 1227 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1228 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1229 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1230 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1231 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1232 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1233 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1234 } 1235 break; 1236 1237 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1238 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1239 case 0x0d30105a: /* Promise OEM ATA 100 */ 1240 switch (mode) { 1241 default: 1242 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1243 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1244 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1245 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1246 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1247 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1248 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1249 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1250 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1251 } 1252 break; 1253 } 1254 pci_write_config(device_get_parent(ch->dev), 0x60 + (devno<<2), timing, 4); 1255} 1256 1257static void 1258hpt_timing(struct ata_channel *ch, int devno, int mode) 1259{ 1260 device_t parent = device_get_parent(ch->dev); 1261 u_int32_t timing; 1262 1263 if (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07) { 1264 switch (mode) { /* HPT374 */ 1265 case ATA_PIO0: timing = 0x0ac1f48a; break; 1266 case ATA_PIO1: timing = 0x0ac1f465; break; 1267 case ATA_PIO2: timing = 0x0a81f454; break; 1268 case ATA_PIO3: timing = 0x0a81f443; break; 1269 case ATA_PIO4: timing = 0x0a81f442; break; 1270 case ATA_WDMA2: timing = 0x22808242; break; 1271 case ATA_UDMA2: timing = 0x120c8242; break; 1272 case ATA_UDMA4: timing = 0x12ac8242; break; 1273 case ATA_UDMA5: timing = 0x12848242; break; 1274 case ATA_UDMA6: timing = 0x12808242; break; 1275 default: timing = 0x0d029d5e; 1276 } 1277 } 1278 else if ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) || 1279 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01)) { 1280 switch (mode) { /* HPT372 */ 1281 case ATA_PIO0: timing = 0x0d029d5e; break; 1282 case ATA_PIO1: timing = 0x0d029d26; break; 1283 case ATA_PIO2: timing = 0x0c829ca6; break; 1284 case ATA_PIO3: timing = 0x0c829c84; break; 1285 case ATA_PIO4: timing = 0x0c829c62; break; 1286 case ATA_WDMA2: timing = 0x2c829262; break; 1287 case ATA_UDMA2: timing = 0x1c91dc62; break; 1288 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1289 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1290 case ATA_UDMA6: timing = 0x1c81dc62; break; 1291 default: timing = 0x0d029d5e; 1292 } 1293 } 1294 else if (ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) { 1295 switch (mode) { /* HPT370 */ 1296 case ATA_PIO0: timing = 0x06914e57; break; 1297 case ATA_PIO1: timing = 0x06914e43; break; 1298 case ATA_PIO2: timing = 0x06514e33; break; 1299 case ATA_PIO3: timing = 0x06514e22; break; 1300 case ATA_PIO4: timing = 0x06514e21; break; 1301 case ATA_WDMA2: timing = 0x26514e21; break; 1302 case ATA_UDMA2: timing = 0x16494e31; break; 1303 case ATA_UDMA4: timing = 0x16454e31; break; 1304 case ATA_UDMA5: timing = 0x16454e31; break; 1305 default: timing = 0x06514e57; 1306 } 1307 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1308 } 1309 else { /* HPT36[68] */ 1310 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1311 case 0x85: /* 25Mhz */ 1312 switch (mode) { 1313 case ATA_PIO0: timing = 0x40d08585; break; 1314 case ATA_PIO1: timing = 0x40d08572; break; 1315 case ATA_PIO2: timing = 0x40ca8542; break; 1316 case ATA_PIO3: timing = 0x40ca8532; break; 1317 case ATA_PIO4: timing = 0x40ca8521; break; 1318 case ATA_WDMA2: timing = 0x20ca8521; break; 1319 case ATA_UDMA2: timing = 0x10cf8521; break; 1320 case ATA_UDMA4: timing = 0x10c98521; break; 1321 default: timing = 0x01208585; 1322 } 1323 break; 1324 default: 1325 case 0xa7: /* 33MHz */ 1326 switch (mode) { 1327 case ATA_PIO0: timing = 0x40d0a7aa; break; 1328 case ATA_PIO1: timing = 0x40d0a7a3; break; 1329 case ATA_PIO2: timing = 0x40d0a753; break; 1330 case ATA_PIO3: timing = 0x40c8a742; break; 1331 case ATA_PIO4: timing = 0x40c8a731; break; 1332 case ATA_WDMA2: timing = 0x20c8a731; break; 1333 case ATA_UDMA2: timing = 0x10caa731; break; 1334 case ATA_UDMA4: timing = 0x10c9a731; break; 1335 default: timing = 0x0120a7a7; 1336 } 1337 break; 1338 case 0xd9: /* 40Mhz */ 1339 switch (mode) { 1340 case ATA_PIO0: timing = 0x4018d9d9; break; 1341 case ATA_PIO1: timing = 0x4010d9c7; break; 1342 case ATA_PIO2: timing = 0x4010d997; break; 1343 case ATA_PIO3: timing = 0x4010d974; break; 1344 case ATA_PIO4: timing = 0x4008d963; break; 1345 case ATA_WDMA2: timing = 0x2008d943; break; 1346 case ATA_UDMA2: timing = 0x100bd943; break; 1347 case ATA_UDMA4: timing = 0x100fd943; break; 1348 default: timing = 0x0120d9d9; 1349 } 1350 } 1351 } 1352 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1353} 1354 1355static int 1356hpt_cable80(struct ata_channel *ch) 1357{ 1358 device_t parent = device_get_parent(ch->dev); 1359 u_int8_t reg, val, res; 1360 1361 if (ch->chiptype == 0x00081103 && pci_get_function(parent) == 1) { 1362 reg = ch->unit ? 0x57 : 0x53; 1363 val = pci_read_config(parent, reg, 1); 1364 pci_write_config(parent, reg, val | 0x80, 1); 1365 } 1366 else { 1367 reg = 0x5b; 1368 val = pci_read_config(parent, reg, 1); 1369 pci_write_config(parent, reg, val & 0xfe, 1); 1370 } 1371 res = pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01 : 0x02); 1372 pci_write_config(parent, reg, val, 1); 1373 return !res; 1374} 1375