ata-dma.c revision 85350
1/*- 2 * Copyright (c) 1998,1999,2000,2001 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 85350 2001-10-23 09:25:57Z sos $ 29 */ 30 31#include "pci.h" 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/ata.h> 35#include <sys/bio.h> 36#include <sys/malloc.h> 37#include <sys/bus.h> 38#include <sys/disk.h> 39#include <sys/devicestat.h> 40#include <vm/vm.h> 41#include <vm/pmap.h> 42#include <pci/pcivar.h> 43#include <machine/bus.h> 44#include <sys/rman.h> 45#include <dev/ata/ata-all.h> 46 47/* prototypes */ 48static void cyrix_timing(struct ata_softc *, int, int); 49static void promise_timing(struct ata_softc *, int, int); 50static void hpt_timing(struct ata_softc *, int, int); 51 52/* misc defines */ 53#ifdef __alpha__ 54#undef vtophys 55#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 56#endif 57#define ATAPI_DEVICE(scp, device) \ 58 ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || \ 59 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 60 61 62void * 63ata_dmaalloc(struct ata_softc *scp, int device) 64{ 65 void *dmatab; 66 67 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 68 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 69 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 70 ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 71 free(dmatab, M_DEVBUF); 72 dmatab = NULL; 73 } 74 } 75 return dmatab; 76} 77 78void 79ata_dmainit(struct ata_softc *scp, int device, 80 int apiomode, int wdmamode, int udmamode) 81{ 82 device_t parent = device_get_parent(scp->dev); 83 int devno = (scp->channel << 1) + ATA_DEV(device); 84 int error; 85 86 /* set our most pessimistic default mode */ 87 scp->mode[ATA_DEV(device)] = ATA_PIO; 88 89 if (!scp->r_bmio) 90 return; 91 92 /* if simplex controller, only allow DMA on primary channel */ 93 if (scp->channel == 1) { 94 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 95 ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 96 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 97 if (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 98 ata_printf(scp, device, "simplex device, DMA on primary only\n"); 99 return; 100 } 101 } 102 103 /* DMA engine address alignment is usually 1 word (2 bytes) */ 104 scp->alignment = 0x1; 105 106#if 1 107 if (udmamode > 2 && !ATA_PARAM(scp, device)->hwres_cblid) { 108 ata_printf(scp, device, 109 "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 110 udmamode = 2; 111 } 112#endif 113 switch (scp->chiptype) { 114 115 case 0x244a8086: /* Intel ICH2 mobile */ 116 case 0x244b8086: /* Intel ICH2 */ 117 if (udmamode >= 5) { 118 int32_t mask48, new48; 119 int16_t word54; 120 121 word54 = pci_read_config(parent, 0x54, 2); 122 if (word54 & (0x10 << devno)) { 123 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 124 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 125 if (bootverbose) 126 ata_printf(scp, device, 127 "%s setting UDMA5 on Intel chip\n", 128 (error) ? "failed" : "success"); 129 if (!error) { 130 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 131 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 132 pci_write_config(parent, 0x48, 133 (pci_read_config(parent, 0x48, 4) & 134 ~mask48) | new48, 4); 135 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 136 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 137 return; 138 } 139 } 140 } 141 /* make sure eventual ATA100 mode from the BIOS is disabled */ 142 pci_write_config(parent, 0x54, 143 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 144 /* FALLTHROUGH */ 145 146 case 0x24118086: /* Intel ICH */ 147 if (udmamode >= 4) { 148 int32_t mask48, new48; 149 int16_t word54; 150 151 word54 = pci_read_config(parent, 0x54, 2); 152 if (word54 & (0x10 << devno)) { 153 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 154 ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 155 if (bootverbose) 156 ata_printf(scp, device, 157 "%s setting UDMA4 on Intel chip\n", 158 (error) ? "failed" : "success"); 159 if (!error) { 160 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 161 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 162 pci_write_config(parent, 0x48, 163 (pci_read_config(parent, 0x48, 4) & 164 ~mask48) | new48, 4); 165 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 166 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 167 return; 168 } 169 } 170 } 171 /* make sure eventual ATA66 mode from the BIOS is disabled */ 172 pci_write_config(parent, 0x54, 173 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 174 /* FALLTHROUGH */ 175 176 case 0x71118086: /* Intel PIIX4 */ 177 case 0x71998086: /* Intel PIIX4e */ 178 case 0x24218086: /* Intel ICH0 */ 179 if (udmamode >= 2) { 180 int32_t mask48, new48; 181 182 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 183 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 184 if (bootverbose) 185 ata_printf(scp, device, "%s setting UDMA2 on Intel chip\n", 186 (error) ? "failed" : "success"); 187 if (!error) { 188 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 189 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 190 pci_write_config(parent, 0x48, 191 (pci_read_config(parent, 0x48, 4) & 192 ~mask48) | new48, 4); 193 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 194 return; 195 } 196 } 197 /* make sure eventual ATA33 mode from the BIOS is disabled */ 198 pci_write_config(parent, 0x48, 199 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 200 /* FALLTHROUGH */ 201 202 case 0x70108086: /* Intel PIIX3 */ 203 if (wdmamode >= 2 && apiomode >= 4) { 204 int32_t mask40, new40, mask44, new44; 205 206 /* if SITRE not set doit for both channels */ 207 if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 208 new40 = pci_read_config(parent, 0x40, 4); 209 new44 = pci_read_config(parent, 0x44, 4); 210 if (!(new40 & 0x00004000)) { 211 new44 &= ~0x0000000f; 212 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 213 } 214 if (!(new40 & 0x40000000)) { 215 new44 &= ~0x000000f0; 216 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 217 } 218 new40 |= 0x40004000; 219 pci_write_config(parent, 0x40, new40, 4); 220 pci_write_config(parent, 0x44, new44, 4); 221 } 222 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 223 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 224 if (bootverbose) 225 ata_printf(scp, device, "%s setting WDMA2 on Intel chip\n", 226 (error) ? "failed" : "success"); 227 if (!error) { 228 if (device == ATA_MASTER) { 229 mask40 = 0x0000330f; 230 new40 = 0x00002307; 231 mask44 = 0; 232 new44 = 0; 233 } 234 else { 235 mask40 = 0x000000f0; 236 new40 = 0x00000070; 237 mask44 = 0x0000000f; 238 new44 = 0x0000000b; 239 } 240 if (scp->channel) { 241 mask40 <<= 16; 242 new40 <<= 16; 243 mask44 <<= 4; 244 new44 <<= 4; 245 } 246 pci_write_config(parent, 0x40, 247 (pci_read_config(parent, 0x40, 4) & ~mask40)| 248 new40, 4); 249 pci_write_config(parent, 0x44, 250 (pci_read_config(parent, 0x44, 4) & ~mask44)| 251 new44, 4); 252 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 253 return; 254 } 255 } 256 /* we could set PIO mode timings, but we assume the BIOS did that */ 257 break; 258 259 case 0x12308086: /* Intel PIIX */ 260 if (wdmamode >= 2 && apiomode >= 4) { 261 int32_t word40; 262 263 word40 = pci_read_config(parent, 0x40, 4); 264 word40 >>= scp->channel * 16; 265 266 /* Check for timing config usable for DMA on controller */ 267 if (!((word40 & 0x3300) == 0x2300 && 268 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 269 break; 270 271 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 272 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 273 if (bootverbose) 274 ata_printf(scp, device, 275 "%s setting WDMA2 on Intel chip\n", 276 (error) ? "failed" : "success"); 277 if (!error) { 278 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 279 return; 280 } 281 } 282 break; 283 284 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 285 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 286 if (pci_get_revid(parent) < 0xC2 && 287 scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 288 ata_printf(scp, device, 289 "Aladdin: two atapi devices on this channel, no DMA\n"); 290 break; 291 } 292 if (udmamode >= 5 && pci_get_revid(parent) >= 0xC4) { 293 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 294 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 295 if (bootverbose) 296 ata_printf(scp, device, 297 "%s setting UDMA5 on Acer chip\n", 298 (error) ? "failed" : "success"); 299 if (!error) { 300 int32_t word54 = pci_read_config(parent, 0x54, 4); 301 302 pci_write_config(parent, 0x4b, 303 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 304 word54 &= ~(0x000f000f << (devno << 2)); 305 word54 |= (0x000f0005 << (devno << 2)); 306 pci_write_config(parent, 0x54, word54, 4); 307 pci_write_config(parent, 0x53, 308 pci_read_config(parent, 0x53, 1) | 0x03, 1); 309 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 310 return; 311 } 312 } 313 if (udmamode >= 4 && pci_get_revid(parent) >= 0xC2) { 314 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 315 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 316 if (bootverbose) 317 ata_printf(scp, device, 318 "%s setting UDMA4 on Acer chip\n", 319 (error) ? "failed" : "success"); 320 if (!error) { 321 int32_t word54 = pci_read_config(parent, 0x54, 4); 322 323 pci_write_config(parent, 0x4b, 324 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 325 word54 &= ~(0x000f000f << (devno << 2)); 326 word54 |= (0x00080005 << (devno << 2)); 327 pci_write_config(parent, 0x54, word54, 4); 328 pci_write_config(parent, 0x53, 329 pci_read_config(parent, 0x53, 1) | 0x03, 1); 330 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 331 return; 332 } 333 } 334 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) { 335 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 336 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 337 if (bootverbose) 338 ata_printf(scp, device, 339 "%s setting UDMA2 on Acer chip\n", 340 (error) ? "failed" : "success"); 341 if (!error) { 342 int32_t word54 = pci_read_config(parent, 0x54, 4); 343 344 word54 &= ~(0x000f000f << (devno << 2)); 345 word54 |= (0x000a0005 << (devno << 2)); 346 pci_write_config(parent, 0x54, word54, 4); 347 pci_write_config(parent, 0x53, 348 pci_read_config(parent, 0x53, 1) | 0x03, 1); 349 scp->flags |= ATA_ATAPI_DMA_RO; 350 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 351 return; 352 } 353 } 354 355 /* make sure eventual UDMA mode from the BIOS is disabled */ 356 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 357 ~(0x0008 << (devno << 2)), 2); 358 359 if (wdmamode >= 2 && apiomode >= 4) { 360 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 361 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 362 if (bootverbose) 363 ata_printf(scp, device, 364 "%s setting WDMA2 on Acer chip\n", 365 (error) ? "failed" : "success"); 366 if (!error) { 367 pci_write_config(parent, 0x53, 368 pci_read_config(parent, 0x53, 1) | 0x03, 1); 369 scp->flags |= ATA_ATAPI_DMA_RO; 370 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 371 return; 372 } 373 } 374 pci_write_config(parent, 0x53, 375 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 376 /* we could set PIO mode timings, but we assume the BIOS did that */ 377 break; 378 379 case 0x74111022: /* AMD 766 */ 380 if (udmamode >= 5) { 381 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 382 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 383 if (bootverbose) 384 ata_printf(scp, device, 385 "%s setting UDMA5 on AMD chip\n", 386 (error) ? "failed" : "success"); 387 if (!error) { 388 pci_write_config(parent, 0x53 - devno, 0xc6, 1); 389 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 390 return; 391 } 392 } 393 /* FALLTHROUGH */ 394 395 case 0x74091022: /* AMD 756 */ 396 if (udmamode >= 4) { 397 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 398 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 399 if (bootverbose) 400 ata_printf(scp, device, 401 "%s setting UDMA4 on AMD chip\n", 402 (error) ? "failed" : "success"); 403 if (!error) { 404 pci_write_config(parent, 0x53 - devno, 0xc5, 1); 405 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 406 return; 407 } 408 } 409 goto via_82c586; 410 411 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 412 if (ata_find_dev(parent, 0x06861106, 0x40) || 413 ata_find_dev(parent, 0x30741106, 0)) { /* 82C686b */ 414 if (udmamode >= 5) { 415 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 416 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 417 if (bootverbose) 418 ata_printf(scp, device, 419 "%s setting UDMA5 on VIA chip\n", 420 (error) ? "failed" : "success"); 421 if (!error) { 422 pci_write_config(parent, 0x53 - devno, 0xf0, 1); 423 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 424 return; 425 } 426 } 427 if (udmamode >= 4) { 428 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 429 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 430 if (bootverbose) 431 ata_printf(scp, device, 432 "%s setting UDMA4 on VIA chip\n", 433 (error) ? "failed" : "success"); 434 if (!error) { 435 pci_write_config(parent, 0x53 - devno, 0xf1, 1); 436 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 437 return; 438 } 439 } 440 if (udmamode >= 2) { 441 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 442 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 443 if (bootverbose) 444 ata_printf(scp, device, 445 "%s setting UDMA2 on VIA chip\n", 446 (error) ? "failed" : "success"); 447 if (!error) { 448 pci_write_config(parent, 0x53 - devno, 0xf4, 1); 449 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 450 return; 451 } 452 } 453 } 454 else if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 455 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 456 if (udmamode >= 4) { 457 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 458 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 459 if (bootverbose) 460 ata_printf(scp, device, 461 "%s setting UDMA4 on VIA chip\n", 462 (error) ? "failed" : "success"); 463 if (!error) { 464 pci_write_config(parent, 0x53 - devno, 0xe8, 1); 465 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 466 return; 467 } 468 } 469 if (udmamode >= 2) { 470 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 471 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 472 if (bootverbose) 473 ata_printf(scp, device, 474 "%s setting UDMA2 on VIA chip\n", 475 (error) ? "failed" : "success"); 476 if (!error) { 477 pci_write_config(parent, 0x53 - devno, 0xea, 1); 478 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 479 return; 480 } 481 } 482 } 483 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 484 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 485via_82c586: 486 if (udmamode >= 2) { 487 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 488 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 489 if (bootverbose) 490 ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 491 (error) ? "failed" : "success", 492 ((scp->chiptype == 0x74091022) || 493 (scp->chiptype == 0x74111022)) ? "AMD" : "VIA"); 494 if (!error) { 495 pci_write_config(parent, 0x53 - devno, 0xc0, 1); 496 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 497 return; 498 } 499 } 500 } 501 if (wdmamode >= 2 && apiomode >= 4) { 502 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 503 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 504 if (bootverbose) 505 ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 506 (error) ? "failed" : "success", 507 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 508 if (!error) { 509 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 510 pci_write_config(parent, 0x4b - devno, 0x31, 1); 511 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 512 return; 513 } 514 } 515 /* we could set PIO mode timings, but we assume the BIOS did that */ 516 break; 517 518 case 0x55131039: /* SiS 5591 */ 519 if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 520 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 521 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 522 if (bootverbose) 523 ata_printf(scp, device, 524 "%s setting UDMA2 on SiS chip\n", 525 (error) ? "failed" : "success"); 526 if (!error) { 527 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 528 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 529 return; 530 } 531 } 532 if (wdmamode >=2 && apiomode >= 4) { 533 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 534 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 535 if (bootverbose) 536 ata_printf(scp, device, 537 "%s setting WDMA2 on SiS chip\n", 538 (error) ? "failed" : "success"); 539 if (!error) { 540 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 541 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 542 return; 543 } 544 } 545 /* we could set PIO mode timings, but we assume the BIOS did that */ 546 break; 547 548 case 0x06491095: /* CMD 649 ATA100 controller */ 549 if (udmamode >= 5) { 550 u_int8_t umode; 551 552 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 553 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 554 if (bootverbose) 555 ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 556 (error) ? "failed" : "success"); 557 if (!error) { 558 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 559 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 560 umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 561 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 562 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 563 return; 564 } 565 } 566 /* FALLTHROUGH */ 567 568 case 0x06481095: /* CMD 648 ATA66 controller */ 569 if (udmamode >= 4) { 570 u_int8_t umode; 571 572 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 573 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 574 if (bootverbose) 575 ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 576 (error) ? "failed" : "success"); 577 if (!error) { 578 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 579 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 580 umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 581 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 582 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 583 return; 584 } 585 } 586 if (udmamode >= 2) { 587 u_int8_t umode; 588 589 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 590 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 591 if (bootverbose) 592 ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 593 (error) ? "failed" : "success"); 594 if (!error) { 595 umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 596 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 597 umode |= (device == ATA_MASTER ? 0x11 : 0x42); 598 pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 599 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 600 return; 601 } 602 } 603 /* make sure eventual UDMA mode from the BIOS is disabled */ 604 pci_write_config(parent, scp->channel ? 0x7b : 0x73, 605 pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 606 ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 607 /* FALLTHROUGH */ 608 609 case 0x06461095: /* CMD 646 ATA controller */ 610 if (wdmamode >= 2 && apiomode >= 4) { 611 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 612 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 613 if (bootverbose) 614 ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 615 error ? "failed" : "success"); 616 if (!error) { 617 int32_t offset = (devno < 3) ? (devno << 1) : 7; 618 619 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 620 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 621 return; 622 } 623 } 624 /* we could set PIO mode timings, but we assume the BIOS did that */ 625 break; 626 627 case 0xc6931080: /* Cypress 82c693 ATA controller */ 628 if (wdmamode >= 2 && apiomode >= 4) { 629 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 630 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 631 if (bootverbose) 632 ata_printf(scp, device, 633 "%s setting WDMA2 on Cypress chip\n", 634 error ? "failed" : "success"); 635 if (!error) { 636 pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 637 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 638 return; 639 } 640 } 641 /* we could set PIO mode timings, but we assume the BIOS did that */ 642 break; 643 644 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 645 scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 646 if (udmamode >= 2) { 647 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 648 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 649 if (bootverbose) 650 ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 651 (error) ? "failed" : "success"); 652 if (!error) { 653 cyrix_timing(scp, devno, ATA_UDMA2); 654 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 655 return; 656 } 657 } 658 if (wdmamode >= 2 && apiomode >= 4) { 659 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 660 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 661 if (bootverbose) 662 ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 663 (error) ? "failed" : "success"); 664 if (!error) { 665 cyrix_timing(scp, devno, ATA_WDMA2); 666 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 667 return; 668 } 669 } 670 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 671 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 672 ATA_WAIT_READY); 673 if (bootverbose) 674 ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 675 (error) ? "failed" : "success", 676 ata_mode2str(ATA_PIO0 + apiomode)); 677 cyrix_timing(scp, devno, ATA_PIO0 + apiomode); 678 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 679 return; 680 681 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 682 if (udmamode >= 2) { 683 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 684 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 685 if (bootverbose) 686 ata_printf(scp, device, 687 "%s setting UDMA2 on ServerWorks chip\n", 688 (error) ? "failed" : "success"); 689 if (!error) { 690 u_int16_t reg56; 691 692 pci_write_config(parent, 0x54, 693 pci_read_config(parent, 0x54, 1) | 694 (0x01 << devno), 1); 695 reg56 = pci_read_config(parent, 0x56, 2); 696 reg56 &= ~(0xf << (devno * 4)); 697 reg56 |= (0x2 << (devno * 4)); 698 pci_write_config(parent, 0x56, reg56, 2); 699 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 700 return; 701 } 702 } 703 if (wdmamode >= 2 && apiomode >= 4) { 704 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 705 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 706 if (bootverbose) 707 ata_printf(scp, device, 708 "%s setting WDMA2 on ServerWorks chip\n", 709 (error) ? "failed" : "success"); 710 if (!error) { 711 int offset = (scp->channel * 2) + (device == ATA_MASTER); 712 int word44 = pci_read_config(parent, 0x44, 4); 713 714 pci_write_config(parent, 0x54, 715 pci_read_config(parent, 0x54, 1) & 716 ~(0x01 << devno), 1); 717 word44 &= ~(0xff << (offset << 8)); 718 word44 |= (0x20 << (offset << 8)); 719 pci_write_config(parent, 0x44, 0x20, 4); 720 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 721 return; 722 } 723 } 724 /* we could set PIO mode timings, but we assume the BIOS did that */ 725 break; 726 727 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 728 case 0x6268105a: /* Promise TX2v2 ATA100 controllers */ 729 case 0x4d69105a: /* Promise ATA133 controllers */ 730 ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 731 if (udmamode >= 4 && !(ATA_INB(scp->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 732 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 733 ATA_UDMA + udmamode, ATA_C_F_SETXFER, 734 ATA_WAIT_READY); 735 if (bootverbose) 736 ata_printf(scp, device, "%s setting %s on Promise chip\n", 737 (error) ? "failed" : "success", 738 ata_mode2str(ATA_UDMA + udmamode)); 739 if (!error) { 740 scp->mode[ATA_DEV(device)] = ATA_UDMA + udmamode; 741 return; 742 } 743 } 744 if (udmamode >= 2) { 745 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 746 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 747 if (bootverbose) 748 ata_printf(scp, device, "%s setting %s on Promise chip\n", 749 (error) ? "failed" : "success", "UDMA2"); 750 if (!error) { 751 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 752 return; 753 } 754 } 755 if (wdmamode >= 2 && apiomode >= 4) { 756 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 757 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 758 if (bootverbose) 759 ata_printf(scp, device, "%s setting %s on Promise chip\n", 760 (error) ? "failed" : "success", "WDMA2"); 761 if (!error) { 762 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 763 return; 764 } 765 } 766 break; 767 768 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 769 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 770 if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 && 771 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 772 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 773 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 774 if (bootverbose) 775 ata_printf(scp, device, 776 "%s setting UDMA5 on Promise chip\n", 777 (error) ? "failed" : "success"); 778 if (!error) { 779 promise_timing(scp, devno, ATA_UDMA5); 780 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 781 return; 782 } 783 } 784 /* FALLTHROUGH */ 785 786 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 787 if (!ATAPI_DEVICE(scp, device) && udmamode >= 4 && 788 !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 789 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 790 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 791 if (bootverbose) 792 ata_printf(scp, device, 793 "%s setting UDMA4 on Promise chip\n", 794 (error) ? "failed" : "success"); 795 if (!error) { 796 promise_timing(scp, devno, ATA_UDMA4); 797 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 798 return; 799 } 800 } 801 /* FALLTHROUGH */ 802 803 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 804 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 805 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 806 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 807 if (bootverbose) 808 ata_printf(scp, device, 809 "%s setting UDMA2 on Promise chip\n", 810 (error) ? "failed" : "success"); 811 if (!error) { 812 promise_timing(scp, devno, ATA_UDMA2); 813 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 814 return; 815 } 816 } 817 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 818 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 819 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 820 if (bootverbose) 821 ata_printf(scp, device, 822 "%s setting WDMA2 on Promise chip\n", 823 (error) ? "failed" : "success"); 824 if (!error) { 825 promise_timing(scp, devno, ATA_WDMA2); 826 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 827 return; 828 } 829 } 830 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 831 ATA_PIO0 + apiomode, 832 ATA_C_F_SETXFER, ATA_WAIT_READY); 833 if (bootverbose) 834 ata_printf(scp, device, 835 "%s setting PIO%d on Promise chip\n", 836 (error) ? "failed" : "success", 837 (apiomode >= 0) ? apiomode : 0); 838 promise_timing(scp, devno, ATA_PIO0 + apiomode); 839 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 840 return; 841 842 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 843 if (!ATAPI_DEVICE(scp, device) && 844 udmamode >= 6 && pci_get_revid(parent) >= 0x05 && 845 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 846 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 847 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 848 if (bootverbose) 849 ata_printf(scp, device, 850 "%s setting UDMA6 on HighPoint chip\n", 851 (error) ? "failed" : "success"); 852 if (!error) { 853 hpt_timing(scp, devno, ATA_UDMA6); 854 scp->mode[ATA_DEV(device)] = ATA_UDMA6; 855 return; 856 } 857 } 858 if (!ATAPI_DEVICE(scp, device) && 859 udmamode >=5 && pci_get_revid(parent) >= 0x03 && 860 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 861 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 862 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 863 if (bootverbose) 864 ata_printf(scp, device, 865 "%s setting UDMA5 on HighPoint chip\n", 866 (error) ? "failed" : "success"); 867 if (!error) { 868 hpt_timing(scp, devno, ATA_UDMA5); 869 scp->mode[ATA_DEV(device)] = ATA_UDMA5; 870 return; 871 } 872 } 873 if (!ATAPI_DEVICE(scp, device) && udmamode >=4 && 874 !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 875 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 876 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 877 if (bootverbose) 878 ata_printf(scp, device, 879 "%s setting UDMA4 on HighPoint chip\n", 880 (error) ? "failed" : "success"); 881 if (!error) { 882 hpt_timing(scp, devno, ATA_UDMA4); 883 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 884 return; 885 } 886 } 887 if (!ATAPI_DEVICE(scp, device) && udmamode >= 2) { 888 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 889 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 890 if (bootverbose) 891 ata_printf(scp, device, 892 "%s setting UDMA2 on HighPoint chip\n", 893 (error) ? "failed" : "success"); 894 if (!error) { 895 hpt_timing(scp, devno, ATA_UDMA2); 896 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 897 return; 898 } 899 } 900 if (!ATAPI_DEVICE(scp, device) && wdmamode >= 2 && apiomode >= 4) { 901 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 902 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 903 if (bootverbose) 904 ata_printf(scp, device, 905 "%s setting WDMA2 on HighPoint chip\n", 906 (error) ? "failed" : "success"); 907 if (!error) { 908 hpt_timing(scp, devno, ATA_WDMA2); 909 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 910 return; 911 } 912 } 913 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 914 ATA_PIO0 + apiomode, 915 ATA_C_F_SETXFER, ATA_WAIT_READY); 916 if (bootverbose) 917 ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 918 (error) ? "failed" : "success", 919 (apiomode >= 0) ? apiomode : 0); 920 hpt_timing(scp, devno, ATA_PIO0 + apiomode); 921 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 922 return; 923 924 default: /* unknown controller chip */ 925 /* better not try generic DMA on ATAPI devices it almost never works */ 926 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 927 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 928 break; 929 930 /* if controller says its setup for DMA take the easy way out */ 931 /* the downside is we dont know what DMA mode we are in */ 932 if ((udmamode >= 0 || wdmamode > 1) && 933 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & 934 ((device==ATA_MASTER) ? 935 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 936 scp->mode[ATA_DEV(device)] = ATA_DMA; 937 return; 938 } 939 940 /* well, we have no support for this, but try anyways */ 941 if ((wdmamode >= 2 && apiomode >= 4) && scp->r_bmio) { 942 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 943 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 944 if (bootverbose) 945 ata_printf(scp, device, 946 "%s setting WDMA2 on generic chip\n", 947 (error) ? "failed" : "success"); 948 if (!error) { 949 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 950 return; 951 } 952 } 953 } 954 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 955 ATA_C_F_SETXFER,ATA_WAIT_READY); 956 if (bootverbose) 957 ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 958 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 959 if (!error) 960 scp->mode[ATA_DEV(device)] = ATA_PIO0 + apiomode; 961 else { 962 if (bootverbose) 963 ata_printf(scp, device, "using PIO mode set by BIOS\n"); 964 scp->mode[ATA_DEV(device)] = ATA_PIO; 965 } 966} 967 968int 969ata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 970 caddr_t data, int32_t count) 971{ 972 u_int32_t dma_count, dma_base; 973 int i = 0; 974 975 if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 976 ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 977 return -1; 978 } 979 980 if (!count) { 981 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 982 return -1; 983 } 984 985 dma_base = vtophys(data); 986 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 987 data += dma_count; 988 count -= dma_count; 989 990 while (count) { 991 dmatab[i].base = dma_base; 992 dmatab[i].count = (dma_count & 0xffff); 993 i++; 994 if (i >= ATA_DMA_ENTRIES) { 995 ata_printf(scp, device, "too many segments in DMA table\n"); 996 return -1; 997 } 998 dma_base = vtophys(data); 999 dma_count = min(count, PAGE_SIZE); 1000 data += min(count, PAGE_SIZE); 1001 count -= min(count, PAGE_SIZE); 1002 } 1003 dmatab[i].base = dma_base; 1004 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 1005 return 0; 1006} 1007 1008void 1009ata_dmastart(struct ata_softc *scp, int device, 1010 struct ata_dmaentry *dmatab, int dir) 1011{ 1012 scp->flags |= ATA_DMA_ACTIVE; 1013 ATA_OUTL(scp->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab)); 1014 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1015 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1016 (ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) | 1017 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1018 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1019 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1020} 1021 1022int 1023ata_dmadone(struct ata_softc *scp) 1024{ 1025 int error; 1026 1027 ATA_OUTB(scp->r_bmio, ATA_BMCMD_PORT, 1028 ATA_INB(scp->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1029 scp->flags &= ~ATA_DMA_ACTIVE; 1030 error = ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT); 1031 ATA_OUTB(scp->r_bmio, ATA_BMSTAT_PORT, 1032 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1033 return error & ATA_BMSTAT_MASK; 1034} 1035 1036int 1037ata_dmastatus(struct ata_softc *scp) 1038{ 1039 return ATA_INB(scp->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1040} 1041 1042static void 1043cyrix_timing(struct ata_softc *scp, int devno, int mode) 1044{ 1045 u_int32_t reg20 = 0x0000e132; 1046 u_int32_t reg24 = 0x00017771; 1047 1048 switch (mode) { 1049 case ATA_PIO0: reg20 = 0x0000e132; break; 1050 case ATA_PIO1: reg20 = 0x00018121; break; 1051 case ATA_PIO2: reg20 = 0x00024020; break; 1052 case ATA_PIO3: reg20 = 0x00032010; break; 1053 case ATA_PIO4: reg20 = 0x00040010; break; 1054 case ATA_WDMA2: reg24 = 0x00002020; break; 1055 case ATA_UDMA2: reg24 = 0x00911030; break; 1056 } 1057 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x20, reg20); 1058 ATA_OUTL(scp->r_bmio, (devno << 3) + 0x24, reg24); 1059} 1060 1061static void 1062promise_timing(struct ata_softc *scp, int devno, int mode) 1063{ 1064 u_int32_t timing = 0; 1065 struct promise_timing { 1066 u_int8_t pa:4; 1067 u_int8_t prefetch:1; 1068 u_int8_t iordy:1; 1069 u_int8_t errdy:1; 1070 u_int8_t syncin:1; 1071 u_int8_t pb:5; 1072 u_int8_t mb:3; 1073 u_int8_t mc:4; 1074 u_int8_t dmaw:1; 1075 u_int8_t dmar:1; 1076 u_int8_t iordyp:1; 1077 u_int8_t dmarqp:1; 1078 u_int8_t reserved:8; 1079 } *t = (struct promise_timing*)&timing; 1080 1081 t->iordy = 1; t->iordyp = 1; 1082 if (mode >= ATA_DMA) { 1083 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1084 } 1085 1086 switch (scp->chiptype) { 1087 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1088 switch (mode) { 1089 default: 1090 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1091 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1092 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1093 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1094 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1095 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1096 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1097 } 1098 break; 1099 1100 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1101 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1102 case 0x0d30105a: /* Promise OEM ATA 100 */ 1103 switch (mode) { 1104 default: 1105 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1106 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1107 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1108 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1109 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1110 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1111 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1112 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1113 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1114 } 1115 break; 1116 } 1117 pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 1118} 1119 1120static void 1121hpt_timing(struct ata_softc *scp, int devno, int mode) 1122{ 1123 device_t parent = device_get_parent(scp->dev); 1124 u_int32_t timing; 1125 if (pci_get_revid(parent) >= 0x05) { /* HPT372 */ 1126 switch (mode) { 1127 case ATA_PIO0: timing = 0x0d029d5e; break; 1128 case ATA_PIO1: timing = 0x0d029d26; break; 1129 case ATA_PIO2: timing = 0x0c829ca6; break; 1130 case ATA_PIO3: timing = 0x0c829c84; break; 1131 case ATA_PIO4: timing = 0x0c829c62; break; 1132 case ATA_WDMA2: timing = 0x2c829262; break; 1133 case ATA_UDMA2: timing = 0x1c91dc62; break; 1134 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1135 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1136 case ATA_UDMA6: timing = 0x1c81dc62; break; 1137 default: timing = 0x0d029d5e; 1138 } 1139 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1140 pci_write_config(parent, 0x5b, 0x20, 1); 1141 } 1142 else if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 1143 switch (mode) { 1144 case ATA_PIO0: timing = 0x06914e57; break; 1145 case ATA_PIO1: timing = 0x06914e43; break; 1146 case ATA_PIO2: timing = 0x06514e33; break; 1147 case ATA_PIO3: timing = 0x06514e22; break; 1148 case ATA_PIO4: timing = 0x06514e21; break; 1149 case ATA_WDMA2: timing = 0x26514e21; break; 1150 case ATA_UDMA2: timing = 0x16494e31; break; 1151 case ATA_UDMA4: timing = 0x16454e31; break; 1152 case ATA_UDMA5: timing = 0x16454e31; break; 1153 default: timing = 0x06514e57; 1154 } 1155 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1156 pci_write_config(parent, 0x5b, 0x22, 1); 1157 } 1158 else { /* HPT36[68] */ 1159 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1160 case 0x85: /* 25Mhz */ 1161 switch (mode) { 1162 case ATA_PIO0: timing = 0xc0d08585; break; 1163 case ATA_PIO1: timing = 0xc0d08572; break; 1164 case ATA_PIO2: timing = 0xc0ca8542; break; 1165 case ATA_PIO3: timing = 0xc0ca8532; break; 1166 case ATA_PIO4: timing = 0xc0ca8521; break; 1167 case ATA_WDMA2: timing = 0xa0ca8521; break; 1168 case ATA_UDMA2: timing = 0x90cf8521; break; 1169 case ATA_UDMA4: timing = 0x90c98521; break; 1170 default: timing = 0x01208585; 1171 } 1172 break; 1173 default: 1174 case 0xa7: /* 33MHz */ 1175 switch (mode) { 1176 case ATA_PIO0: timing = 0xc0d0a7aa; break; 1177 case ATA_PIO1: timing = 0xc0d0a7a3; break; 1178 case ATA_PIO2: timing = 0xc0d0a753; break; 1179 case ATA_PIO3: timing = 0xc0c8a742; break; 1180 case ATA_PIO4: timing = 0xc0c8a731; break; 1181 case ATA_WDMA2: timing = 0xa0c8a731; break; 1182 case ATA_UDMA2: timing = 0x90caa731; break; 1183 case ATA_UDMA4: timing = 0x90c9a731; break; 1184 default: timing = 0x0120a7a7; 1185 } 1186 break; 1187 case 0xd9: /* 40Mhz */ 1188 switch (mode) { 1189 case ATA_PIO0: timing = 0xc018d9d9; break; 1190 case ATA_PIO1: timing = 0xc010d9c7; break; 1191 case ATA_PIO2: timing = 0xc010d997; break; 1192 case ATA_PIO3: timing = 0xc010d974; break; 1193 case ATA_PIO4: timing = 0xc008d963; break; 1194 case ATA_WDMA2: timing = 0xa008d943; break; 1195 case ATA_UDMA2: timing = 0x900bd943; break; 1196 case ATA_UDMA4: timing = 0x900fd943; break; 1197 default: timing = 0x0120d9d9; 1198 } 1199 } 1200 pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 1201 } 1202} 1203