ata-dma.c revision 70186
145095Ssos/*- 255333Ssos * Copyright (c) 1998,1999,2000 S�ren Schmidt 345095Ssos * All rights reserved. 445095Ssos * 545095Ssos * Redistribution and use in source and binary forms, with or without 645095Ssos * modification, are permitted provided that the following conditions 745095Ssos * are met: 845095Ssos * 1. Redistributions of source code must retain the above copyright 945095Ssos * notice, this list of conditions and the following disclaimer, 1045095Ssos * without modification, immediately at the beginning of the file. 1145095Ssos * 2. Redistributions in binary form must reproduce the above copyright 1245095Ssos * notice, this list of conditions and the following disclaimer in the 1345095Ssos * documentation and/or other materials provided with the distribution. 1445095Ssos * 3. The name of the author may not be used to endorse or promote products 1545095Ssos * derived from this software without specific prior written permission. 1645095Ssos * 1745095Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1845095Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1945095Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2045095Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2145095Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2245095Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2345095Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2445095Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2545095Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2645095Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2745095Ssos * 2850477Speter * $FreeBSD: head/sys/dev/ata/ata-dma.c 70186 2000-12-19 10:37:03Z sos $ 2945095Ssos */ 3045095Ssos 3145150Ssos#include "pci.h" 3245095Ssos#include <sys/param.h> 3345095Ssos#include <sys/systm.h> 3460041Sphk#include <sys/bio.h> 3545095Ssos#include <sys/malloc.h> 3645798Ssos#include <sys/bus.h> 3754270Ssos#include <sys/disk.h> 3854270Ssos#include <sys/devicestat.h> 3951520Ssos#include <vm/vm.h> 4045095Ssos#include <vm/pmap.h> 4147272Ssos#if NPCI > 0 4245095Ssos#include <pci/pcivar.h> 4347272Ssos#endif 4466106Ssos#include <machine/bus.h> 4545095Ssos#include <dev/ata/ata-all.h> 4645095Ssos 4756754Ssos#if NPCI > 0 4856754Ssos 4952067Ssos/* prototypes */ 5066070Ssosstatic void cyrix_timing(struct ata_softc *, int, int); 5166070Ssosstatic void promise_timing(struct ata_softc *, int, int); 5266070Ssosstatic void hpt_timing(struct ata_softc *, int, int); 5352067Ssos 5452067Ssos/* misc defines */ 5545720Speter#ifdef __alpha__ 5645720Speter#undef vtophys 5751520Ssos#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 5845720Speter#endif 5945720Speter 6066070Ssosvoid * 6166070Ssosata_dmaalloc(struct ata_softc *scp, int device) 6266070Ssos{ 6366070Ssos void *dmatab; 6466070Ssos 6566070Ssos if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 6666070Ssos if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 6766070Ssos (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 6866070Ssos ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 6966070Ssos free(dmatab, M_DEVBUF); 7066070Ssos dmatab = NULL; 7166070Ssos } 7266070Ssos } 7366070Ssos return dmatab; 7466070Ssos} 7566070Ssos 7656744Ssosvoid 7766070Ssosata_dmainit(struct ata_softc *scp, int device, 7866070Ssos int apiomode, int wdmamode, int udmamode) 7945095Ssos{ 8057325Ssos device_t parent = device_get_parent(scp->dev); 8167058Ssos int devno = (scp->channel << 1) + ATA_DEV(device); 8264307Ssos int error; 8345095Ssos 8456744Ssos /* set our most pessimistic default mode */ 8556744Ssos scp->mode[ATA_DEV(device)] = ATA_PIO; 8656744Ssos 8745095Ssos if (!scp->bmaddr) 8856744Ssos return; 8945095Ssos 9052067Ssos /* if simplex controller, only allow DMA on primary channel */ 9167058Ssos if (scp->channel == 1) { 9252067Ssos outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 9352067Ssos (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 9452067Ssos if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 9556558Ssos ata_printf(scp, device, "simplex device, DMA on primary only\n"); 9656744Ssos return; 9752067Ssos } 9852067Ssos } 9952067Ssos 10066070Ssos /* DMA engine address alignment is usually 1 word (2 bytes) */ 10166070Ssos scp->alignment = 0x1; 10245095Ssos 10360829Ssos if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 10460829Ssos ata_printf(scp, device, 10564027Ssteve "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 10660829Ssos udmamode = 2; 10760829Ssos } 10845095Ssos 10955333Ssos switch (scp->chiptype) { 11045095Ssos 11164307Ssos case 0x244b8086: /* Intel ICH2 */ 11264307Ssos if (udmamode >= 5) { 11364307Ssos int32_t mask48, new48; 11464307Ssos int16_t word54; 11564307Ssos 11664307Ssos word54 = pci_read_config(parent, 0x54, 2); 11764307Ssos if (word54 & (0x10 << devno)) { 11864307Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 11964307Ssos ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 12064307Ssos if (bootverbose) 12164307Ssos ata_printf(scp, device, 12264695Ssos "%s setting UDMA5 on ICH2 chip\n", 12364307Ssos (error) ? "failed" : "success"); 12464307Ssos if (!error) { 12564307Ssos mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 12664307Ssos new48 = (1 << devno) + (1 << (16 + (devno << 2))); 12764307Ssos pci_write_config(parent, 0x48, 12864307Ssos (pci_read_config(parent, 0x48, 4) & 12964307Ssos ~mask48) | new48, 4); 13064479Ssos pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 13164307Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 13264307Ssos return; 13364307Ssos } 13464307Ssos } 13564307Ssos } 13664479Ssos /* make sure eventual ATA100 mode from the BIOS is disabled */ 13764479Ssos pci_write_config(parent, 0x54, 13864479Ssos pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 13964307Ssos /* FALLTHROUGH */ 14064307Ssos 14157391Ssos case 0x24118086: /* Intel ICH */ 14257391Ssos if (udmamode >= 4) { 14357391Ssos int32_t mask48, new48; 14457391Ssos int16_t word54; 14557391Ssos 14657391Ssos word54 = pci_read_config(parent, 0x54, 2); 14757391Ssos if (word54 & (0x10 << devno)) { 14857391Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 14957391Ssos ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 15057391Ssos if (bootverbose) 15157391Ssos ata_printf(scp, device, 15264695Ssos "%s setting UDMA4 on ICH%s chip\n", 15364307Ssos (error) ? "failed" : "success", 15464307Ssos (scp->chiptype == 0x244b8086) ? "2" : ""); 15557391Ssos if (!error) { 15657391Ssos mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 15757391Ssos new48 = (1 << devno) + (2 << (16 + (devno << 2))); 15857391Ssos pci_write_config(parent, 0x48, 15957391Ssos (pci_read_config(parent, 0x48, 4) & 16057391Ssos ~mask48) | new48, 4); 16157391Ssos pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 16257391Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 16357391Ssos return; 16457391Ssos } 16557391Ssos } 16657391Ssos } 16764479Ssos /* make sure eventual ATA66 mode from the BIOS is disabled */ 16864479Ssos pci_write_config(parent, 0x54, 16964479Ssos pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 17057391Ssos /* FALLTHROUGH */ 17157391Ssos 17245095Ssos case 0x71118086: /* Intel PIIX4 */ 17356138Ssos case 0x71998086: /* Intel PIIX4e */ 17456138Ssos case 0x24218086: /* Intel ICH0 */ 17545095Ssos if (udmamode >= 2) { 17651520Ssos int32_t mask48, new48; 17745095Ssos 17845095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 17953029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 18051520Ssos if (bootverbose) 18164695Ssos ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 18256558Ssos (error) ? "failed" : "success", 18364307Ssos (scp->chiptype == 0x244b8086) ? "ICH2" : 18464307Ssos (scp->chiptype == 0x24118086) ? "ICH" : 18564307Ssos (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 18653681Ssos if (!error) { 18753681Ssos mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 18853681Ssos new48 = (1 << devno) + (2 << (16 + (devno << 2))); 18957325Ssos pci_write_config(parent, 0x48, 19057325Ssos (pci_read_config(parent, 0x48, 4) & 19153681Ssos ~mask48) | new48, 4); 19256558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 19356744Ssos return; 19453681Ssos } 19545095Ssos } 19664479Ssos /* make sure eventual ATA33 mode from the BIOS is disabled */ 19764479Ssos pci_write_config(parent, 0x48, 19864479Ssos pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 19945095Ssos /* FALLTHROUGH */ 20045095Ssos 20145095Ssos case 0x70108086: /* Intel PIIX3 */ 20245095Ssos if (wdmamode >= 2 && apiomode >= 4) { 20345095Ssos int32_t mask40, new40, mask44, new44; 20445095Ssos 20545095Ssos /* if SITRE not set doit for both channels */ 20667058Ssos if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 20757325Ssos new40 = pci_read_config(parent, 0x40, 4); 20857325Ssos new44 = pci_read_config(parent, 0x44, 4); 20951520Ssos if (!(new40 & 0x00004000)) { 21051520Ssos new44 &= ~0x0000000f; 21151520Ssos new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 21251520Ssos } 21351520Ssos if (!(new40 & 0x40000000)) { 21451520Ssos new44 &= ~0x000000f0; 21551520Ssos new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 21651520Ssos } 21751520Ssos new40 |= 0x40004000; 21857325Ssos pci_write_config(parent, 0x40, new40, 4); 21957325Ssos pci_write_config(parent, 0x44, new44, 4); 22045095Ssos } 22145095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 22253029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 22351520Ssos if (bootverbose) 22464695Ssos ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 22556558Ssos (error) ? "failed" : "success", 22664307Ssos (scp->chiptype == 0x244b8086) ? "ICH2" : 22756558Ssos (scp->chiptype == 0x24118086) ? "ICH" : 22864307Ssos (scp->chiptype == 0x24218086) ? "ICH0" : 22964307Ssos (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4"); 23053681Ssos if (!error) { 23153681Ssos if (device == ATA_MASTER) { 23253681Ssos mask40 = 0x0000330f; 23353681Ssos new40 = 0x00002307; 23453681Ssos mask44 = 0; 23553681Ssos new44 = 0; 23653681Ssos } 23753681Ssos else { 23853681Ssos mask40 = 0x000000f0; 23953681Ssos new40 = 0x00000070; 24053681Ssos mask44 = 0x0000000f; 24153681Ssos new44 = 0x0000000b; 24253681Ssos } 24367058Ssos if (scp->channel) { 24453681Ssos mask40 <<= 16; 24553681Ssos new40 <<= 16; 24653681Ssos mask44 <<= 4; 24753681Ssos new44 <<= 4; 24853681Ssos } 24957325Ssos pci_write_config(parent, 0x40, 25057325Ssos (pci_read_config(parent, 0x40, 4) & ~mask40)| 25153681Ssos new40, 4); 25257325Ssos pci_write_config(parent, 0x44, 25357325Ssos (pci_read_config(parent, 0x44, 4) & ~mask44)| 25453681Ssos new44, 4); 25556558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 25656744Ssos return; 25745095Ssos } 25851520Ssos } 25953681Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 26045095Ssos break; 26145095Ssos 26245095Ssos case 0x12308086: /* Intel PIIX */ 26354544Ssos if (wdmamode >= 2 && apiomode >= 4) { 26454544Ssos int32_t word40; 26554544Ssos 26657325Ssos word40 = pci_read_config(parent, 0x40, 4); 26767058Ssos word40 >>= scp->channel * 16; 26854544Ssos 26954544Ssos /* Check for timing config usable for DMA on controller */ 27054544Ssos if (!((word40 & 0x3300) == 0x2300 && 27154544Ssos ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 27254544Ssos break; 27354544Ssos 27454544Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 27554544Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 27654544Ssos if (bootverbose) 27756558Ssos ata_printf(scp, device, 27864695Ssos "%s setting WDMA2 on PIIX chip\n", 27956558Ssos (error) ? "failed" : "success"); 28054544Ssos if (!error) { 28156558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 28256744Ssos return; 28354544Ssos } 28454544Ssos } 28545095Ssos break; 28645095Ssos 28752067Ssos case 0x522910b9: /* AcerLabs Aladdin IV/V */ 28853029Ssos /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 28953029Ssos if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 29056558Ssos ata_printf(scp, device, 29156558Ssos "Aladdin: two atapi devices on this channel, no DMA\n"); 29253029Ssos break; 29352067Ssos } 29467057Ssos if (udmamode >= 2 && pci_get_revid(parent) > 0x20) { 29557325Ssos int32_t word54 = pci_read_config(parent, 0x54, 4); 29652067Ssos 29751520Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 29853029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 29951520Ssos if (bootverbose) 30056558Ssos ata_printf(scp, device, 30164695Ssos "%s setting UDMA2 on Aladdin chip\n", 30256558Ssos (error) ? "failed" : "success"); 30353681Ssos if (!error) { 30460829Ssos word54 &= ~(0x000f000f << (devno << 2)); 30560829Ssos word54 |= (0x000a0005 << (devno << 2)); 30657325Ssos pci_write_config(parent, 0x54, word54, 4); 30757325Ssos pci_write_config(parent, 0x53, 30857325Ssos pci_read_config(parent, 0x53, 1) | 0x03, 1); 30953681Ssos scp->flags |= ATA_ATAPI_DMA_RO; 31056558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 31156744Ssos return; 31253681Ssos } 31351520Ssos } 31470186Ssos 31570186Ssos /* make sure eventual UDMA mode from the BIOS is disabled */ 31670186Ssos pci_write_config(parent, 0x54, 31770186Ssos pci_read_config(parent, 0x54, 4) & ~0x88880000, 4); 31870186Ssos 31953681Ssos if (wdmamode >= 2 && apiomode >= 4) { 32052067Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 32153029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 32252067Ssos if (bootverbose) 32356558Ssos ata_printf(scp, device, 32464695Ssos "%s setting WDMA2 on Aladdin chip\n", 32556558Ssos (error) ? "failed" : "success"); 32653681Ssos if (!error) { 32757325Ssos pci_write_config(parent, 0x53, 32857325Ssos pci_read_config(parent, 0x53, 1) | 0x03, 1); 32953681Ssos scp->flags |= ATA_ATAPI_DMA_RO; 33056558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 33156744Ssos return; 33253681Ssos } 33352067Ssos } 33457771Ssos pci_write_config(parent, 0x53, 33557771Ssos (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 33653681Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 33752067Ssos break; 33852067Ssos 33959103Ssos case 0x74091022: /* AMD 756 */ 34059103Ssos if (udmamode >= 4) { 34159103Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 34259103Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 34359103Ssos if (bootverbose) 34459103Ssos ata_printf(scp, device, 34564695Ssos "%s setting UDMA4 on AMD chip\n", 34659103Ssos (error) ? "failed" : "success"); 34759103Ssos if (!error) { 34859103Ssos pci_write_config(parent, 0x53 - devno, 0xc3, 1); 34959103Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 35059103Ssos return; 35159103Ssos } 35259103Ssos } 35359103Ssos goto via_82c586; 35459103Ssos 35564695Ssos case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 35664695Ssos if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 35764695Ssos ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 35864695Ssos 35964695Ssos if (udmamode >= 4) { 36064695Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 36164695Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 36264695Ssos if (bootverbose) 36364695Ssos ata_printf(scp, device, 36464695Ssos "%s setting UDMA4 on VIA chip\n", 36564695Ssos (error) ? "failed" : "success"); 36664695Ssos if (!error) { 36764695Ssos pci_write_config(parent, 0x53 - devno, 0xe8, 1); 36864695Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 36964695Ssos return; 37064695Ssos } 37156138Ssos } 37264695Ssos if (udmamode >= 2) { 37364695Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 37464695Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 37564695Ssos if (bootverbose) 37664695Ssos ata_printf(scp, device, 37764695Ssos "%s setting UDMA2 on VIA chip\n", 37864695Ssos (error) ? "failed" : "success"); 37964695Ssos if (!error) { 38064695Ssos pci_write_config(parent, 0x53 - devno, 0xea, 1); 38164695Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 38264695Ssos return; 38364695Ssos } 38456138Ssos } 38556138Ssos } 38664695Ssos else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 38764695Ssos ata_find_dev(parent, 0x05861106, 0x02)) { /* 82C586b */ 38859103Ssosvia_82c586: 38964695Ssos if (udmamode >= 2) { 39064695Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 39164695Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 39264695Ssos if (bootverbose) 39364695Ssos ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 39464695Ssos (error) ? "failed" : "success", 39564695Ssos (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 39664695Ssos if (!error) { 39764695Ssos pci_write_config(parent, 0x53 - devno, 0xc0, 1); 39864695Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 39964695Ssos return; 40064695Ssos } 40153681Ssos } 40253681Ssos } 40353681Ssos if (wdmamode >= 2 && apiomode >= 4) { 40453681Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 40553681Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 40653681Ssos if (bootverbose) 40764695Ssos ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 40856558Ssos (error) ? "failed" : "success", 40956558Ssos (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 41053681Ssos if (!error) { 41157325Ssos pci_write_config(parent, 0x53 - devno, 0x82, 1); 41257325Ssos pci_write_config(parent, 0x4b - devno, 0x31, 1); 41356558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 41456744Ssos return; 41553681Ssos } 41653681Ssos } 41753681Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 41853681Ssos break; 41953681Ssos 42054544Ssos case 0x55131039: /* SiS 5591 */ 42167057Ssos if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 42254544Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 42354544Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 42454544Ssos if (bootverbose) 42556558Ssos ata_printf(scp, device, 42664695Ssos "%s setting UDMA2 on SiS chip\n", 42756558Ssos (error) ? "failed" : "success"); 42854544Ssos if (!error) { 42957325Ssos pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 43056558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 43156744Ssos return; 43254544Ssos } 43354544Ssos } 43454544Ssos if (wdmamode >=2 && apiomode >= 4) { 43554544Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 43654544Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 43754544Ssos if (bootverbose) 43856558Ssos ata_printf(scp, device, 43964695Ssos "%s setting WDMA2 on SiS chip\n", 44056558Ssos (error) ? "failed" : "success"); 44154544Ssos if (!error) { 44257325Ssos pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 44356558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 44456744Ssos return; 44554544Ssos } 44654544Ssos } 44754544Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 44854544Ssos break; 44954544Ssos 45066583Ssos case 0x06491095: /* CMD 649 ATA100 controller */ 45166583Ssos if (udmamode >= 5) { 45266583Ssos u_int8_t umode; 45366583Ssos 45466583Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 45566583Ssos ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 45666583Ssos if (bootverbose) 45766583Ssos ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 45866583Ssos (error) ? "failed" : "success"); 45966583Ssos if (!error) { 46067058Ssos umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 46166583Ssos umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 46266583Ssos umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 46367058Ssos pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 46466583Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 46566583Ssos return; 46666583Ssos } 46766583Ssos } 46866583Ssos /* FALLTHROUGH */ 46966583Ssos 47066583Ssos case 0x06481095: /* CMD 648 ATA66 controller */ 47166583Ssos if (udmamode >= 4) { 47266583Ssos u_int8_t umode; 47366583Ssos 47466583Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 47566583Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 47666583Ssos if (bootverbose) 47766583Ssos ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 47866583Ssos (error) ? "failed" : "success"); 47966583Ssos if (!error) { 48067058Ssos umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 48166583Ssos umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 48266583Ssos umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 48367058Ssos pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 48466583Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 48566583Ssos return; 48666583Ssos } 48766583Ssos } 48866583Ssos if (udmamode >= 2) { 48966583Ssos u_int8_t umode; 49066583Ssos 49166583Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 49266583Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 49366583Ssos if (bootverbose) 49466583Ssos ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 49566583Ssos (error) ? "failed" : "success"); 49666583Ssos if (!error) { 49767058Ssos umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 49866583Ssos umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 49966583Ssos umode |= (device == ATA_MASTER ? 0x11 : 0x42); 50067058Ssos pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 50166583Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 50266583Ssos return; 50366583Ssos } 50466583Ssos } 50566583Ssos /* make sure eventual UDMA mode from the BIOS is disabled */ 50667058Ssos pci_write_config(parent, scp->channel ? 0x7b : 0x73, 50767067Ssos pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 50866583Ssos ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 50966583Ssos /* FALLTHROUGH */ 51066583Ssos 51157325Ssos case 0x06461095: /* CMD 646 ATA controller */ 51257325Ssos if (wdmamode >= 2 && apiomode >= 4) { 51357325Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 51457325Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 51557325Ssos if (bootverbose) 51666583Ssos ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 51757325Ssos error ? "failed" : "success"); 51857325Ssos if (!error) { 51957325Ssos int32_t offset = (devno < 3) ? (devno << 1) : 7; 52057325Ssos 52157325Ssos pci_write_config(parent, 0x54 + offset, 0x3f, 1); 52257325Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 52357325Ssos return; 52457325Ssos } 52557325Ssos } 52657325Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 52757325Ssos break; 52857325Ssos 52957477Ssos case 0xc6931080: /* Cypress 82c693 ATA controller */ 53057477Ssos if (wdmamode >= 2 && apiomode >= 4) { 53157477Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 53257477Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 53357477Ssos if (bootverbose) 53457477Ssos ata_printf(scp, device, 53564695Ssos "%s setting WDMA2 on Cypress chip\n", 53657477Ssos error ? "failed" : "success"); 53757477Ssos if (!error) { 53867058Ssos pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 53957477Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 54057477Ssos return; 54157477Ssos } 54257477Ssos } 54357477Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 54457477Ssos break; 54557477Ssos 54666583Ssos case 0x01021078: /* Cyrix 5530 ATA33 controller */ 54766070Ssos scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 54866070Ssos if (udmamode >= 2) { 54966070Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 55066070Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 55166070Ssos if (bootverbose) 55266583Ssos ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 55366070Ssos (error) ? "failed" : "success"); 55466070Ssos if (!error) { 55566070Ssos cyrix_timing(scp, devno, ATA_UDMA2); 55666070Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 55766070Ssos return; 55866070Ssos } 55966070Ssos } 56066070Ssos if (wdmamode >= 2 && apiomode >= 4) { 56166070Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 56266070Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 56366070Ssos if (bootverbose) 56466070Ssos ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 56566070Ssos (error) ? "failed" : "success"); 56666070Ssos if (!error) { 56766070Ssos cyrix_timing(scp, devno, ATA_WDMA2); 56866070Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 56966070Ssos return; 57066070Ssos } 57166070Ssos } 57266070Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 57366070Ssos ata_pio2mode(apiomode), ATA_C_F_SETXFER, 57466070Ssos ATA_WAIT_READY); 57566070Ssos if (bootverbose) 57666070Ssos ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 57766070Ssos (error) ? "failed" : "success", 57866070Ssos ata_mode2str(ata_pio2mode(apiomode))); 57966070Ssos cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 58066070Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 58166070Ssos return; 58266070Ssos 58366583Ssos case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 58466583Ssos if (udmamode >= 2) { 58566583Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 58666583Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 58766583Ssos if (bootverbose) 58866583Ssos ata_printf(scp, device, 58966583Ssos "%s setting UDMA2 on ServerWorks chip\n", 59066583Ssos (error) ? "failed" : "success"); 59166583Ssos if (!error) { 59270186Ssos u_int16_t reg56; 59370186Ssos 59466583Ssos pci_write_config(parent, 0x54, 59566583Ssos pci_read_config(parent, 0x54, 1) | 59666583Ssos (0x01 << devno), 1); 59766583Ssos reg56 = pci_read_config(parent, 0x56, 2); 59866583Ssos reg56 &= ~(0xf << (devno * 4)); 59966583Ssos reg56 |= (0x2 << (devno * 4)); 60066583Ssos pci_write_config(parent, 0x56, reg56, 2); 60166583Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 60266583Ssos return; 60366583Ssos } 60466583Ssos } 60566583Ssos if (wdmamode >= 2 && apiomode >= 4) { 60666583Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 60766583Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 60866583Ssos if (bootverbose) 60966583Ssos ata_printf(scp, device, 61066583Ssos "%s setting WDMA2 on ServerWorks chip\n", 61166583Ssos (error) ? "failed" : "success"); 61266583Ssos if (!error) { 61367058Ssos int offset = (scp->channel * 2) + (device == ATA_MASTER); 61466583Ssos int word44 = pci_read_config(parent, 0x44, 4); 61566583Ssos 61666583Ssos pci_write_config(parent, 0x54, 61766583Ssos pci_read_config(parent, 0x54, 1) & 61866583Ssos ~(0x01 << devno), 1); 61966583Ssos word44 &= ~(0xff << (offset << 8)); 62066583Ssos word44 |= (0x20 << (offset << 8)); 62166583Ssos pci_write_config(parent, 0x44, 0x20, 4); 62266583Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 62366583Ssos return; 62466583Ssos } 62566583Ssos } 62666583Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 62766583Ssos break; 62866583Ssos 62966070Ssos case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 63066070Ssos case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 63166070Ssos case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 63266070Ssos case 0x0d30105a: /* Promise OEM ATA100 controllers */ 63352067Ssos /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 63452067Ssos if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 63552067Ssos (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 63652067Ssos break; 63752067Ssos 63866326Ssos if (udmamode >= 5 && 63966070Ssos (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 64067058Ssos !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 64152918Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 64264307Ssos ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 64364307Ssos if (bootverbose) 64464307Ssos ata_printf(scp, device, 64564695Ssos "%s setting UDMA5 on Promise chip\n", 64664307Ssos (error) ? "failed" : "success"); 64764307Ssos if (!error) { 64864307Ssos promise_timing(scp, devno, ATA_UDMA5); 64964307Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 65064307Ssos return; 65164307Ssos } 65264307Ssos } 65366326Ssos if (udmamode >= 4 && (scp->chiptype == 0x4d38105a || 65466070Ssos scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 65567058Ssos !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 65664307Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 65753029Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 65852918Ssos if (bootverbose) 65956558Ssos ata_printf(scp, device, 66064695Ssos "%s setting UDMA4 on Promise chip\n", 66156558Ssos (error) ? "failed" : "success"); 66253681Ssos if (!error) { 66355333Ssos promise_timing(scp, devno, ATA_UDMA4); 66456558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 66556744Ssos return; 66653681Ssos } 66752918Ssos } 66853681Ssos if (udmamode >= 2) { 66945095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 67053029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 67151520Ssos if (bootverbose) 67256558Ssos ata_printf(scp, device, 67364695Ssos "%s setting UDMA2 on Promise chip\n", 67456558Ssos (error) ? "failed" : "success"); 67553681Ssos if (!error) { 67655333Ssos promise_timing(scp, devno, ATA_UDMA2); 67756558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 67856744Ssos return; 67953681Ssos } 68045095Ssos } 68153681Ssos if (wdmamode >= 2 && apiomode >= 4) { 68245095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 68353029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 68451520Ssos if (bootverbose) 68556558Ssos ata_printf(scp, device, 68664695Ssos "%s setting WDMA2 on Promise chip\n", 68756558Ssos (error) ? "failed" : "success"); 68853681Ssos if (!error) { 68955333Ssos promise_timing(scp, devno, ATA_WDMA2); 69056558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 69156744Ssos return; 69253681Ssos } 69351520Ssos } 69455333Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 69555333Ssos ata_pio2mode(apiomode), 69655333Ssos ATA_C_F_SETXFER, ATA_WAIT_READY); 69753681Ssos if (bootverbose) 69856558Ssos ata_printf(scp, device, 69964695Ssos "%s setting PIO%d on Promise chip\n", 70056558Ssos (error) ? "failed" : "success", 70156558Ssos (apiomode >= 0) ? apiomode : 0); 70256686Ssos promise_timing(scp, devno, ata_pio2mode(apiomode)); 70356686Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 70456744Ssos return; 70545095Ssos 70664307Ssos case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 70753681Ssos /* no ATAPI devices for now */ 70851520Ssos if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 70952067Ssos (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 71052067Ssos break; 71151520Ssos 71264307Ssos if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 71367058Ssos !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 71452067Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 71564307Ssos ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 71664307Ssos if (bootverbose) 71764307Ssos ata_printf(scp, device, 71867057Ssos "%s setting UDMA5 on HighPoint chip\n", 71964307Ssos (error) ? "failed" : "success"); 72064307Ssos if (!error) { 72164307Ssos hpt_timing(scp, devno, ATA_UDMA5); 72264307Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 72364307Ssos return; 72464307Ssos } 72564307Ssos } 72664307Ssos if (udmamode >=4 && 72767058Ssos !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 72864307Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 72953029Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 73052067Ssos if (bootverbose) 73156558Ssos ata_printf(scp, device, 73267057Ssos "%s setting UDMA4 on HighPoint chip\n", 73356558Ssos (error) ? "failed" : "success"); 73453681Ssos if (!error) { 73564307Ssos hpt_timing(scp, devno, ATA_UDMA4); 73656558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 73756744Ssos return; 73853681Ssos } 73951520Ssos } 74053681Ssos if (udmamode >= 2) { 74152067Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 74253029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 74351520Ssos if (bootverbose) 74456558Ssos ata_printf(scp, device, 74567057Ssos "%s setting UDMA2 on HighPoint chip\n", 74656558Ssos (error) ? "failed" : "success"); 74753681Ssos if (!error) { 74864307Ssos hpt_timing(scp, devno, ATA_UDMA2); 74956558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 75056744Ssos return; 75153681Ssos } 75245095Ssos } 75353681Ssos if (wdmamode >= 2 && apiomode >= 4) { 75445095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 75553029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 75651520Ssos if (bootverbose) 75756558Ssos ata_printf(scp, device, 75867057Ssos "%s setting WDMA2 on HighPoint chip\n", 75956558Ssos (error) ? "failed" : "success"); 76053681Ssos if (!error) { 76164307Ssos hpt_timing(scp, devno, ATA_WDMA2); 76256558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 76356744Ssos return; 76453681Ssos } 76545095Ssos } 76655333Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 76755333Ssos ata_pio2mode(apiomode), 76855333Ssos ATA_C_F_SETXFER, ATA_WAIT_READY); 76953681Ssos if (bootverbose) 77067057Ssos ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 77156558Ssos (error) ? "failed" : "success", 77256558Ssos (apiomode >= 0) ? apiomode : 0); 77364307Ssos hpt_timing(scp, devno, ata_pio2mode(apiomode)); 77456686Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 77556744Ssos return; 77645095Ssos 77751548Ssos default: /* unknown controller chip */ 77851548Ssos /* better not try generic DMA on ATAPI devices it almost never works */ 77951548Ssos if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 78051548Ssos (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 78151548Ssos break; 78251548Ssos 78356744Ssos /* if controller says its setup for DMA take the easy way out */ 78456744Ssos /* the downside is we dont know what DMA mode we are in */ 78556744Ssos if ((udmamode >= 0 || wdmamode > 1) && 78656744Ssos (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 78756744Ssos ((device==ATA_MASTER) ? 78856744Ssos ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 78956744Ssos scp->mode[ATA_DEV(device)] = ATA_DMA; 79056744Ssos return; 79156744Ssos } 79256744Ssos 79351548Ssos /* well, we have no support for this, but try anyways */ 79454594Ssos if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 79545095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 79653029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 79751520Ssos if (bootverbose) 79856558Ssos ata_printf(scp, device, 79964695Ssos "%s setting WDMA2 on generic chip\n", 80056558Ssos (error) ? "failed" : "success"); 80153681Ssos if (!error) { 80256558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 80356744Ssos return; 80453681Ssos } 80545095Ssos } 80645095Ssos } 80756988Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 80856988Ssos ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 80955333Ssos if (bootverbose) 81064695Ssos ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 81156988Ssos (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 81256988Ssos if (!error) 81356988Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 81457771Ssos else { 81556988Ssos if (bootverbose) 81656988Ssos ata_printf(scp, device, "using PIO mode set by BIOS\n"); 81757771Ssos scp->mode[ATA_DEV(device)] = ATA_PIO; 81857771Ssos } 81945095Ssos} 82045095Ssos 82166070Ssosint 82266070Ssosata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 82366070Ssos caddr_t data, int32_t count) 82445095Ssos{ 82545095Ssos u_int32_t dma_count, dma_base; 82664307Ssos int i = 0; 82745095Ssos 82866070Ssos if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 82966070Ssos ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 83045095Ssos return -1; 83166070Ssos } 83245095Ssos 83345095Ssos if (!count) { 83456558Ssos ata_printf(scp, device, "zero length DMA transfer attempted\n"); 83545095Ssos return -1; 83645095Ssos } 83745095Ssos 83845095Ssos dma_base = vtophys(data); 83956558Ssos dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 84045095Ssos data += dma_count; 84145095Ssos count -= dma_count; 84245095Ssos 84345095Ssos while (count) { 84445095Ssos dmatab[i].base = dma_base; 84545095Ssos dmatab[i].count = (dma_count & 0xffff); 84645095Ssos i++; 84745095Ssos if (i >= ATA_DMA_ENTRIES) { 84856558Ssos ata_printf(scp, device, "too many segments in DMA table\n"); 84945095Ssos return -1; 85045095Ssos } 85145095Ssos dma_base = vtophys(data); 85256558Ssos dma_count = min(count, PAGE_SIZE); 85356558Ssos data += min(count, PAGE_SIZE); 85456558Ssos count -= min(count, PAGE_SIZE); 85545095Ssos } 85645095Ssos dmatab[i].base = dma_base; 85745095Ssos dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 85845095Ssos return 0; 85945095Ssos} 86045095Ssos 86145095Ssosvoid 86266070Ssosata_dmastart(struct ata_softc *scp, int device, 86366070Ssos struct ata_dmaentry *dmatab, int dir) 86445095Ssos{ 86552067Ssos scp->flags |= ATA_DMA_ACTIVE; 86666070Ssos outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 86766070Ssos outb(scp->bmaddr + ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 86866070Ssos outb(scp->bmaddr + ATA_BMSTAT_PORT, 86966070Ssos (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 87066070Ssos (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 87145095Ssos outb(scp->bmaddr + ATA_BMCMD_PORT, 87245095Ssos inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 87345095Ssos} 87445095Ssos 87566070Ssosint 87652067Ssosata_dmadone(struct ata_softc *scp) 87745095Ssos{ 87845095Ssos outb(scp->bmaddr + ATA_BMCMD_PORT, 87945095Ssos inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 88052067Ssos scp->flags &= ~ATA_DMA_ACTIVE; 88145095Ssos return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 88245095Ssos} 88345095Ssos 88466070Ssosint 88552067Ssosata_dmastatus(struct ata_softc *scp) 88645095Ssos{ 88745095Ssos return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 88845095Ssos} 88945095Ssos 89052067Ssosstatic void 89166070Ssoscyrix_timing(struct ata_softc *scp, int devno, int mode) 89252067Ssos{ 89366070Ssos u_int32_t reg20 = 0x0000e132; 89466070Ssos u_int32_t reg24 = 0x00017771; 89566070Ssos 89666070Ssos switch (mode) { 89766070Ssos case ATA_PIO0: reg20 = 0x0000e132; break; 89866070Ssos case ATA_PIO1: reg20 = 0x00018121; break; 89966070Ssos case ATA_PIO2: reg20 = 0x00024020; break; 90066070Ssos case ATA_PIO3: reg20 = 0x00032010; break; 90166070Ssos case ATA_PIO4: reg20 = 0x00040010; break; 90266070Ssos case ATA_WDMA2: reg24 = 0x00002020; break; 90366070Ssos case ATA_UDMA2: reg24 = 0x00911030; break; 90466070Ssos } 90570186Ssos outl(scp->bmaddr + (devno << 3) + 0x20, reg20); 90670186Ssos outl(scp->bmaddr + (devno << 3) + 0x24, reg24); 90766070Ssos} 90866070Ssos 90966070Ssosstatic void 91066070Ssospromise_timing(struct ata_softc *scp, int devno, int mode) 91166070Ssos{ 91256988Ssos u_int32_t timing = 0; 91356988Ssos struct promise_timing { 91456988Ssos u_int8_t pa:4; 91556988Ssos u_int8_t prefetch:1; 91656988Ssos u_int8_t iordy:1; 91756988Ssos u_int8_t errdy:1; 91856988Ssos u_int8_t syncin:1; 91956988Ssos u_int8_t pb:5; 92056988Ssos u_int8_t mb:3; 92156988Ssos u_int8_t mc:4; 92256988Ssos u_int8_t dmaw:1; 92356988Ssos u_int8_t dmar:1; 92456988Ssos u_int8_t iordyp:1; 92556988Ssos u_int8_t dmarqp:1; 92656988Ssos u_int8_t reserved:8; 92756988Ssos } *t = (struct promise_timing*)&timing; 92856988Ssos 92956988Ssos t->iordy = 1; t->iordyp = 1; 93056988Ssos if (mode >= ATA_DMA) { 93156988Ssos t->prefetch = 1; t->errdy = 1; t->syncin = 1; 93255333Ssos } 93356988Ssos 93456988Ssos switch (scp->chiptype) { 93566070Ssos case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 93656988Ssos switch (mode) { 93756988Ssos default: 93856988Ssos case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 93956988Ssos case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 94056988Ssos case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 94156988Ssos case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 94256988Ssos case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 94356988Ssos case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 94456988Ssos case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 94556988Ssos } 94656988Ssos break; 94756988Ssos 94866070Ssos case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 94966070Ssos case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 95066070Ssos case 0x0d30105a: /* Promise OEM ATA 100 */ 95156988Ssos switch (mode) { 95256988Ssos default: 95356988Ssos case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 95456988Ssos case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 95556988Ssos case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 95656988Ssos case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 95756988Ssos case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 95856988Ssos case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 95956988Ssos case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 96056988Ssos case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 96164307Ssos case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 96256988Ssos } 96356988Ssos break; 96456988Ssos } 96557325Ssos pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 96655333Ssos} 96752067Ssos 96855333Ssosstatic void 96966070Ssoshpt_timing(struct ata_softc *scp, int devno, int mode) 97055333Ssos{ 97157325Ssos device_t parent = device_get_parent(scp->dev); 97255333Ssos u_int32_t timing; 97355333Ssos 97464307Ssos if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 97552067Ssos switch (mode) { 97664307Ssos case ATA_PIO0: timing = 0x06914e57; break; 97764307Ssos case ATA_PIO1: timing = 0x06914e43; break; 97864307Ssos case ATA_PIO2: timing = 0x06514e33; break; 97964307Ssos case ATA_PIO3: timing = 0x06514e22; break; 98064307Ssos case ATA_PIO4: timing = 0x06514e21; break; 98164307Ssos case ATA_WDMA2: timing = 0x26514e21; break; 98264307Ssos case ATA_UDMA2: timing = 0x16494e31; break; 98364307Ssos case ATA_UDMA4: timing = 0x16454e31; break; 98464307Ssos case ATA_UDMA5: timing = 0x16454e31; break; 98564307Ssos default: timing = 0x06514e57; 98652067Ssos } 98764307Ssos pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 98864307Ssos pci_write_config(parent, 0x5b, 0x22, 1); 98964307Ssos } 99064307Ssos else { /* HPT36[68] */ 99164307Ssos switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 99264307Ssos case 0x85: /* 25Mhz */ 99364307Ssos switch (mode) { 99464307Ssos case ATA_PIO0: timing = 0xc0d08585; break; 99564307Ssos case ATA_PIO1: timing = 0xc0d08572; break; 99664307Ssos case ATA_PIO2: timing = 0xc0ca8542; break; 99764307Ssos case ATA_PIO3: timing = 0xc0ca8532; break; 99864307Ssos case ATA_PIO4: timing = 0xc0ca8521; break; 99964307Ssos case ATA_WDMA2: timing = 0xa0ca8521; break; 100064307Ssos case ATA_UDMA2: timing = 0x90cf8521; break; 100164307Ssos case ATA_UDMA4: timing = 0x90c98521; break; 100264307Ssos default: timing = 0x01208585; 100364307Ssos } 100464307Ssos break; 100564307Ssos default: 100664307Ssos case 0xa7: /* 33MHz */ 100764307Ssos switch (mode) { 100864307Ssos case ATA_PIO0: timing = 0xc0d0a7aa; break; 100964307Ssos case ATA_PIO1: timing = 0xc0d0a7a3; break; 101064307Ssos case ATA_PIO2: timing = 0xc0d0a753; break; 101164307Ssos case ATA_PIO3: timing = 0xc0c8a742; break; 101264307Ssos case ATA_PIO4: timing = 0xc0c8a731; break; 101364307Ssos case ATA_WDMA2: timing = 0xa0c8a731; break; 101464307Ssos case ATA_UDMA2: timing = 0x90caa731; break; 101564307Ssos case ATA_UDMA4: timing = 0x90c9a731; break; 101664307Ssos default: timing = 0x0120a7a7; 101764307Ssos } 101864307Ssos break; 101964307Ssos case 0xd9: /* 40Mhz */ 102064307Ssos switch (mode) { 102164307Ssos case ATA_PIO0: timing = 0xc018d9d9; break; 102264307Ssos case ATA_PIO1: timing = 0xc010d9c7; break; 102364307Ssos case ATA_PIO2: timing = 0xc010d997; break; 102464307Ssos case ATA_PIO3: timing = 0xc010d974; break; 102564307Ssos case ATA_PIO4: timing = 0xc008d963; break; 102664307Ssos case ATA_WDMA2: timing = 0xa008d943; break; 102764307Ssos case ATA_UDMA2: timing = 0x900bd943; break; 102864307Ssos case ATA_UDMA4: timing = 0x900fd943; break; 102964307Ssos default: timing = 0x0120d9d9; 103064307Ssos } 103152067Ssos } 103264307Ssos pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 103352067Ssos } 103452067Ssos} 103552067Ssos 103645095Ssos#else /* NPCI > 0 */ 103745095Ssos 103867067Ssosvoid * 103967067Ssosata_dmaalloc(struct ata_softc *scp, int device) 104067067Ssos{ 104167435Ssos return 0; 104267067Ssos} 104367067Ssos 104456754Ssosvoid 104566070Ssosata_dmainit(struct ata_softc *scp, int device, 104666070Ssos int piomode, int wdmamode, int udmamode) 104745095Ssos{ 104845095Ssos} 104945095Ssos 105066070Ssosint 105167067Ssosata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 105267067Ssos caddr_t data, int32_t count) 105345095Ssos{ 105445095Ssos return -1; 105545095Ssos} 105645095Ssos 105767067Ssosvoid 105867067Ssosata_dmastart(struct ata_softc *scp, int device, 105967067Ssos struct ata_dmaentry *dmatab, int dir) 106045095Ssos{ 106145095Ssos} 106245095Ssos 106366070Ssosint 106452067Ssosata_dmadone(struct ata_softc *scp) 106545095Ssos{ 106645095Ssos return -1; 106745095Ssos} 106845095Ssos 106966070Ssosint 107052067Ssosata_dmastatus(struct ata_softc *scp) 107145095Ssos{ 107245095Ssos return -1; 107345095Ssos} 107445095Ssos 107545095Ssos#endif /* NPCI > 0 */ 1076