ata-dma.c revision 67435
145095Ssos/*- 255333Ssos * Copyright (c) 1998,1999,2000 S�ren Schmidt 345095Ssos * All rights reserved. 445095Ssos * 545095Ssos * Redistribution and use in source and binary forms, with or without 645095Ssos * modification, are permitted provided that the following conditions 745095Ssos * are met: 845095Ssos * 1. Redistributions of source code must retain the above copyright 945095Ssos * notice, this list of conditions and the following disclaimer, 1045095Ssos * without modification, immediately at the beginning of the file. 1145095Ssos * 2. Redistributions in binary form must reproduce the above copyright 1245095Ssos * notice, this list of conditions and the following disclaimer in the 1345095Ssos * documentation and/or other materials provided with the distribution. 1445095Ssos * 3. The name of the author may not be used to endorse or promote products 1545095Ssos * derived from this software without specific prior written permission. 1645095Ssos * 1745095Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1845095Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1945095Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2045095Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2145095Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2245095Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2345095Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2445095Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2545095Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2645095Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2745095Ssos * 2850477Speter * $FreeBSD: head/sys/dev/ata/ata-dma.c 67435 2000-10-22 12:17:38Z sos $ 2945095Ssos */ 3045095Ssos 3145150Ssos#include "pci.h" 3245095Ssos#include <sys/param.h> 3345095Ssos#include <sys/systm.h> 3460041Sphk#include <sys/bio.h> 3545095Ssos#include <sys/malloc.h> 3645798Ssos#include <sys/bus.h> 3754270Ssos#include <sys/disk.h> 3854270Ssos#include <sys/devicestat.h> 3951520Ssos#include <vm/vm.h> 4045095Ssos#include <vm/pmap.h> 4147272Ssos#if NPCI > 0 4245095Ssos#include <pci/pcivar.h> 4347272Ssos#endif 4466106Ssos#include <machine/bus.h> 4545095Ssos#include <dev/ata/ata-all.h> 4645095Ssos 4756754Ssos#if NPCI > 0 4856754Ssos 4952067Ssos/* prototypes */ 5066070Ssosstatic void cyrix_timing(struct ata_softc *, int, int); 5166070Ssosstatic void promise_timing(struct ata_softc *, int, int); 5266070Ssosstatic void hpt_timing(struct ata_softc *, int, int); 5352067Ssos 5452067Ssos/* misc defines */ 5545720Speter#ifdef __alpha__ 5645720Speter#undef vtophys 5751520Ssos#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 5845720Speter#endif 5945720Speter 6066070Ssosvoid * 6166070Ssosata_dmaalloc(struct ata_softc *scp, int device) 6266070Ssos{ 6366070Ssos void *dmatab; 6466070Ssos 6566070Ssos if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 6666070Ssos if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 6766070Ssos (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 6866070Ssos ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 6966070Ssos free(dmatab, M_DEVBUF); 7066070Ssos dmatab = NULL; 7166070Ssos } 7266070Ssos } 7366070Ssos return dmatab; 7466070Ssos} 7566070Ssos 7656744Ssosvoid 7766070Ssosata_dmainit(struct ata_softc *scp, int device, 7866070Ssos int apiomode, int wdmamode, int udmamode) 7945095Ssos{ 8057325Ssos device_t parent = device_get_parent(scp->dev); 8167058Ssos int devno = (scp->channel << 1) + ATA_DEV(device); 8264307Ssos int error; 8345095Ssos 8456744Ssos /* set our most pessimistic default mode */ 8556744Ssos scp->mode[ATA_DEV(device)] = ATA_PIO; 8656744Ssos 8745095Ssos if (!scp->bmaddr) 8856744Ssos return; 8945095Ssos 9052067Ssos /* if simplex controller, only allow DMA on primary channel */ 9167058Ssos if (scp->channel == 1) { 9252067Ssos outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 9352067Ssos (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 9452067Ssos if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 9556558Ssos ata_printf(scp, device, "simplex device, DMA on primary only\n"); 9656744Ssos return; 9752067Ssos } 9852067Ssos } 9952067Ssos 10066070Ssos /* DMA engine address alignment is usually 1 word (2 bytes) */ 10166070Ssos scp->alignment = 0x1; 10245095Ssos 10360829Ssos if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 10460829Ssos ata_printf(scp, device, 10564027Ssteve "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 10660829Ssos udmamode = 2; 10760829Ssos } 10845095Ssos 10955333Ssos switch (scp->chiptype) { 11045095Ssos 11164307Ssos case 0x244b8086: /* Intel ICH2 */ 11264307Ssos if (udmamode >= 5) { 11364307Ssos int32_t mask48, new48; 11464307Ssos int16_t word54; 11564307Ssos 11664307Ssos word54 = pci_read_config(parent, 0x54, 2); 11764307Ssos if (word54 & (0x10 << devno)) { 11864307Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 11964307Ssos ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 12064307Ssos if (bootverbose) 12164307Ssos ata_printf(scp, device, 12264695Ssos "%s setting UDMA5 on ICH2 chip\n", 12364307Ssos (error) ? "failed" : "success"); 12464307Ssos if (!error) { 12564307Ssos mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 12664307Ssos new48 = (1 << devno) + (1 << (16 + (devno << 2))); 12764307Ssos pci_write_config(parent, 0x48, 12864307Ssos (pci_read_config(parent, 0x48, 4) & 12964307Ssos ~mask48) | new48, 4); 13064479Ssos pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 13164307Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 13264307Ssos return; 13364307Ssos } 13464307Ssos } 13564307Ssos } 13664479Ssos /* make sure eventual ATA100 mode from the BIOS is disabled */ 13764479Ssos pci_write_config(parent, 0x54, 13864479Ssos pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 13964307Ssos /* FALLTHROUGH */ 14064307Ssos 14157391Ssos case 0x24118086: /* Intel ICH */ 14257391Ssos if (udmamode >= 4) { 14357391Ssos int32_t mask48, new48; 14457391Ssos int16_t word54; 14557391Ssos 14657391Ssos word54 = pci_read_config(parent, 0x54, 2); 14757391Ssos if (word54 & (0x10 << devno)) { 14857391Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 14957391Ssos ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 15057391Ssos if (bootverbose) 15157391Ssos ata_printf(scp, device, 15264695Ssos "%s setting UDMA4 on ICH%s chip\n", 15364307Ssos (error) ? "failed" : "success", 15464307Ssos (scp->chiptype == 0x244b8086) ? "2" : ""); 15557391Ssos if (!error) { 15657391Ssos mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 15757391Ssos new48 = (1 << devno) + (2 << (16 + (devno << 2))); 15857391Ssos pci_write_config(parent, 0x48, 15957391Ssos (pci_read_config(parent, 0x48, 4) & 16057391Ssos ~mask48) | new48, 4); 16157391Ssos pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 16257391Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 16357391Ssos return; 16457391Ssos } 16557391Ssos } 16657391Ssos } 16764479Ssos /* make sure eventual ATA66 mode from the BIOS is disabled */ 16864479Ssos pci_write_config(parent, 0x54, 16964479Ssos pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 17057391Ssos /* FALLTHROUGH */ 17157391Ssos 17245095Ssos case 0x71118086: /* Intel PIIX4 */ 17356138Ssos case 0x71998086: /* Intel PIIX4e */ 17456138Ssos case 0x24218086: /* Intel ICH0 */ 17545095Ssos if (udmamode >= 2) { 17651520Ssos int32_t mask48, new48; 17745095Ssos 17845095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 17953029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 18051520Ssos if (bootverbose) 18164695Ssos ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 18256558Ssos (error) ? "failed" : "success", 18364307Ssos (scp->chiptype == 0x244b8086) ? "ICH2" : 18464307Ssos (scp->chiptype == 0x24118086) ? "ICH" : 18564307Ssos (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 18653681Ssos if (!error) { 18753681Ssos mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 18853681Ssos new48 = (1 << devno) + (2 << (16 + (devno << 2))); 18957325Ssos pci_write_config(parent, 0x48, 19057325Ssos (pci_read_config(parent, 0x48, 4) & 19153681Ssos ~mask48) | new48, 4); 19256558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 19356744Ssos return; 19453681Ssos } 19545095Ssos } 19664479Ssos /* make sure eventual ATA33 mode from the BIOS is disabled */ 19764479Ssos pci_write_config(parent, 0x48, 19864479Ssos pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 19945095Ssos /* FALLTHROUGH */ 20045095Ssos 20145095Ssos case 0x70108086: /* Intel PIIX3 */ 20245095Ssos if (wdmamode >= 2 && apiomode >= 4) { 20345095Ssos int32_t mask40, new40, mask44, new44; 20445095Ssos 20545095Ssos /* if SITRE not set doit for both channels */ 20667058Ssos if (!((pci_read_config(parent,0x40,4)>>(scp->channel<<8))&0x4000)) { 20757325Ssos new40 = pci_read_config(parent, 0x40, 4); 20857325Ssos new44 = pci_read_config(parent, 0x44, 4); 20951520Ssos if (!(new40 & 0x00004000)) { 21051520Ssos new44 &= ~0x0000000f; 21151520Ssos new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 21251520Ssos } 21351520Ssos if (!(new40 & 0x40000000)) { 21451520Ssos new44 &= ~0x000000f0; 21551520Ssos new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 21651520Ssos } 21751520Ssos new40 |= 0x40004000; 21857325Ssos pci_write_config(parent, 0x40, new40, 4); 21957325Ssos pci_write_config(parent, 0x44, new44, 4); 22045095Ssos } 22145095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 22253029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 22351520Ssos if (bootverbose) 22464695Ssos ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 22556558Ssos (error) ? "failed" : "success", 22664307Ssos (scp->chiptype == 0x244b8086) ? "ICH2" : 22756558Ssos (scp->chiptype == 0x24118086) ? "ICH" : 22864307Ssos (scp->chiptype == 0x24218086) ? "ICH0" : 22964307Ssos (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4"); 23053681Ssos if (!error) { 23153681Ssos if (device == ATA_MASTER) { 23253681Ssos mask40 = 0x0000330f; 23353681Ssos new40 = 0x00002307; 23453681Ssos mask44 = 0; 23553681Ssos new44 = 0; 23653681Ssos } 23753681Ssos else { 23853681Ssos mask40 = 0x000000f0; 23953681Ssos new40 = 0x00000070; 24053681Ssos mask44 = 0x0000000f; 24153681Ssos new44 = 0x0000000b; 24253681Ssos } 24367058Ssos if (scp->channel) { 24453681Ssos mask40 <<= 16; 24553681Ssos new40 <<= 16; 24653681Ssos mask44 <<= 4; 24753681Ssos new44 <<= 4; 24853681Ssos } 24957325Ssos pci_write_config(parent, 0x40, 25057325Ssos (pci_read_config(parent, 0x40, 4) & ~mask40)| 25153681Ssos new40, 4); 25257325Ssos pci_write_config(parent, 0x44, 25357325Ssos (pci_read_config(parent, 0x44, 4) & ~mask44)| 25453681Ssos new44, 4); 25556558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 25656744Ssos return; 25745095Ssos } 25851520Ssos } 25953681Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 26045095Ssos break; 26145095Ssos 26245095Ssos case 0x12308086: /* Intel PIIX */ 26354544Ssos if (wdmamode >= 2 && apiomode >= 4) { 26454544Ssos int32_t word40; 26554544Ssos 26657325Ssos word40 = pci_read_config(parent, 0x40, 4); 26767058Ssos word40 >>= scp->channel * 16; 26854544Ssos 26954544Ssos /* Check for timing config usable for DMA on controller */ 27054544Ssos if (!((word40 & 0x3300) == 0x2300 && 27154544Ssos ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 27254544Ssos break; 27354544Ssos 27454544Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 27554544Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 27654544Ssos if (bootverbose) 27756558Ssos ata_printf(scp, device, 27864695Ssos "%s setting WDMA2 on PIIX chip\n", 27956558Ssos (error) ? "failed" : "success"); 28054544Ssos if (!error) { 28156558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 28256744Ssos return; 28354544Ssos } 28454544Ssos } 28545095Ssos break; 28645095Ssos 28752067Ssos case 0x522910b9: /* AcerLabs Aladdin IV/V */ 28853029Ssos /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 28953029Ssos if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 29056558Ssos ata_printf(scp, device, 29156558Ssos "Aladdin: two atapi devices on this channel, no DMA\n"); 29253029Ssos break; 29352067Ssos } 29467057Ssos if (udmamode >= 2 && pci_get_revid(parent) > 0x20) { 29557325Ssos int32_t word54 = pci_read_config(parent, 0x54, 4); 29652067Ssos 29751520Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 29853029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 29951520Ssos if (bootverbose) 30056558Ssos ata_printf(scp, device, 30164695Ssos "%s setting UDMA2 on Aladdin chip\n", 30256558Ssos (error) ? "failed" : "success"); 30353681Ssos if (!error) { 30460829Ssos word54 &= ~(0x000f000f << (devno << 2)); 30560829Ssos word54 |= (0x000a0005 << (devno << 2)); 30657325Ssos pci_write_config(parent, 0x54, word54, 4); 30757325Ssos pci_write_config(parent, 0x53, 30857325Ssos pci_read_config(parent, 0x53, 1) | 0x03, 1); 30953681Ssos scp->flags |= ATA_ATAPI_DMA_RO; 31056558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 31156744Ssos return; 31253681Ssos } 31351520Ssos } 31453681Ssos if (wdmamode >= 2 && apiomode >= 4) { 31552067Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 31653029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 31752067Ssos if (bootverbose) 31856558Ssos ata_printf(scp, device, 31964695Ssos "%s setting WDMA2 on Aladdin chip\n", 32056558Ssos (error) ? "failed" : "success"); 32153681Ssos if (!error) { 32257325Ssos pci_write_config(parent, 0x53, 32357325Ssos pci_read_config(parent, 0x53, 1) | 0x03, 1); 32453681Ssos scp->flags |= ATA_ATAPI_DMA_RO; 32556558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 32656744Ssos return; 32753681Ssos } 32852067Ssos } 32957771Ssos pci_write_config(parent, 0x53, 33057771Ssos (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 33153681Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 33252067Ssos break; 33352067Ssos 33459103Ssos case 0x74091022: /* AMD 756 */ 33559103Ssos if (udmamode >= 4) { 33659103Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 33759103Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 33859103Ssos if (bootverbose) 33959103Ssos ata_printf(scp, device, 34064695Ssos "%s setting UDMA4 on AMD chip\n", 34159103Ssos (error) ? "failed" : "success"); 34259103Ssos if (!error) { 34359103Ssos pci_write_config(parent, 0x53 - devno, 0xc3, 1); 34459103Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 34559103Ssos return; 34659103Ssos } 34759103Ssos } 34859103Ssos goto via_82c586; 34959103Ssos 35064695Ssos case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 35164695Ssos if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 35264695Ssos ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 35364695Ssos 35464695Ssos if (udmamode >= 4) { 35564695Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 35664695Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 35764695Ssos if (bootverbose) 35864695Ssos ata_printf(scp, device, 35964695Ssos "%s setting UDMA4 on VIA chip\n", 36064695Ssos (error) ? "failed" : "success"); 36164695Ssos if (!error) { 36264695Ssos pci_write_config(parent, 0x53 - devno, 0xe8, 1); 36364695Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 36464695Ssos return; 36564695Ssos } 36656138Ssos } 36764695Ssos if (udmamode >= 2) { 36864695Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 36964695Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 37064695Ssos if (bootverbose) 37164695Ssos ata_printf(scp, device, 37264695Ssos "%s setting UDMA2 on VIA chip\n", 37364695Ssos (error) ? "failed" : "success"); 37464695Ssos if (!error) { 37564695Ssos pci_write_config(parent, 0x53 - devno, 0xea, 1); 37664695Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 37764695Ssos return; 37864695Ssos } 37956138Ssos } 38056138Ssos } 38164695Ssos else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 38264695Ssos ata_find_dev(parent, 0x05861106, 0x02)) { /* 82C586b */ 38359103Ssosvia_82c586: 38464695Ssos if (udmamode >= 2) { 38564695Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 38664695Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 38764695Ssos if (bootverbose) 38864695Ssos ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 38964695Ssos (error) ? "failed" : "success", 39064695Ssos (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 39164695Ssos if (!error) { 39264695Ssos pci_write_config(parent, 0x53 - devno, 0xc0, 1); 39364695Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 39464695Ssos return; 39564695Ssos } 39653681Ssos } 39753681Ssos } 39853681Ssos if (wdmamode >= 2 && apiomode >= 4) { 39953681Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 40053681Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 40153681Ssos if (bootverbose) 40264695Ssos ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 40356558Ssos (error) ? "failed" : "success", 40456558Ssos (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 40553681Ssos if (!error) { 40657325Ssos pci_write_config(parent, 0x53 - devno, 0x82, 1); 40757325Ssos pci_write_config(parent, 0x4b - devno, 0x31, 1); 40856558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 40956744Ssos return; 41053681Ssos } 41153681Ssos } 41253681Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 41353681Ssos break; 41453681Ssos 41554544Ssos case 0x55131039: /* SiS 5591 */ 41667057Ssos if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) { 41754544Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 41854544Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 41954544Ssos if (bootverbose) 42056558Ssos ata_printf(scp, device, 42164695Ssos "%s setting UDMA2 on SiS chip\n", 42256558Ssos (error) ? "failed" : "success"); 42354544Ssos if (!error) { 42457325Ssos pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 42556558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 42656744Ssos return; 42754544Ssos } 42854544Ssos } 42954544Ssos if (wdmamode >=2 && apiomode >= 4) { 43054544Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 43154544Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 43254544Ssos if (bootverbose) 43356558Ssos ata_printf(scp, device, 43464695Ssos "%s setting WDMA2 on SiS chip\n", 43556558Ssos (error) ? "failed" : "success"); 43654544Ssos if (!error) { 43757325Ssos pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 43856558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 43956744Ssos return; 44054544Ssos } 44154544Ssos } 44254544Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 44354544Ssos break; 44454544Ssos 44566583Ssos case 0x06491095: /* CMD 649 ATA100 controller */ 44666583Ssos if (udmamode >= 5) { 44766583Ssos u_int8_t umode; 44866583Ssos 44966583Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 45066583Ssos ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 45166583Ssos if (bootverbose) 45266583Ssos ata_printf(scp, device, "%s setting UDMA5 on CMD chip\n", 45366583Ssos (error) ? "failed" : "success"); 45466583Ssos if (!error) { 45567058Ssos umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 45666583Ssos umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 45766583Ssos umode |= (device == ATA_MASTER ? 0x05 : 0x0a); 45867058Ssos pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 45966583Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 46066583Ssos return; 46166583Ssos } 46266583Ssos } 46366583Ssos /* FALLTHROUGH */ 46466583Ssos 46566583Ssos case 0x06481095: /* CMD 648 ATA66 controller */ 46666583Ssos if (udmamode >= 4) { 46766583Ssos u_int8_t umode; 46866583Ssos 46966583Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 47066583Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 47166583Ssos if (bootverbose) 47266583Ssos ata_printf(scp, device, "%s setting UDMA4 on CMD chip\n", 47366583Ssos (error) ? "failed" : "success"); 47466583Ssos if (!error) { 47567058Ssos umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 47666583Ssos umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 47766583Ssos umode |= (device == ATA_MASTER ? 0x15 : 0x4a); 47867058Ssos pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 47966583Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 48066583Ssos return; 48166583Ssos } 48266583Ssos } 48366583Ssos if (udmamode >= 2) { 48466583Ssos u_int8_t umode; 48566583Ssos 48666583Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 48766583Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 48866583Ssos if (bootverbose) 48966583Ssos ata_printf(scp, device, "%s setting UDMA2 on CMD chip\n", 49066583Ssos (error) ? "failed" : "success"); 49166583Ssos if (!error) { 49267058Ssos umode = pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1); 49366583Ssos umode &= ~(device == ATA_MASTER ? 0x35 : 0xca); 49466583Ssos umode |= (device == ATA_MASTER ? 0x11 : 0x42); 49567058Ssos pci_write_config(parent, scp->channel ? 0x7b : 0x73, umode, 1); 49666583Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 49766583Ssos return; 49866583Ssos } 49966583Ssos } 50066583Ssos /* make sure eventual UDMA mode from the BIOS is disabled */ 50167058Ssos pci_write_config(parent, scp->channel ? 0x7b : 0x73, 50267067Ssos pci_read_config(parent, scp->channel ? 0x7b : 0x73, 1)& 50366583Ssos ~(device == ATA_MASTER ? 0x35 : 0xca), 1); 50466583Ssos /* FALLTHROUGH */ 50566583Ssos 50657325Ssos case 0x06461095: /* CMD 646 ATA controller */ 50757325Ssos if (wdmamode >= 2 && apiomode >= 4) { 50857325Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 50957325Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 51057325Ssos if (bootverbose) 51166583Ssos ata_printf(scp, device, "%s setting WDMA2 on CMD chip\n", 51257325Ssos error ? "failed" : "success"); 51357325Ssos if (!error) { 51457325Ssos int32_t offset = (devno < 3) ? (devno << 1) : 7; 51557325Ssos 51657325Ssos pci_write_config(parent, 0x54 + offset, 0x3f, 1); 51757325Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 51857325Ssos return; 51957325Ssos } 52057325Ssos } 52157325Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 52257325Ssos break; 52357325Ssos 52457477Ssos case 0xc6931080: /* Cypress 82c693 ATA controller */ 52557477Ssos if (wdmamode >= 2 && apiomode >= 4) { 52657477Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 52757477Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 52857477Ssos if (bootverbose) 52957477Ssos ata_printf(scp, device, 53064695Ssos "%s setting WDMA2 on Cypress chip\n", 53157477Ssos error ? "failed" : "success"); 53257477Ssos if (!error) { 53367058Ssos pci_write_config(scp->dev, scp->channel ? 0x4e:0x4c, 0x2020, 2); 53457477Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 53557477Ssos return; 53657477Ssos } 53757477Ssos } 53857477Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 53957477Ssos break; 54057477Ssos 54166583Ssos case 0x01021078: /* Cyrix 5530 ATA33 controller */ 54266070Ssos scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 54366070Ssos if (udmamode >= 2) { 54466070Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 54566070Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 54666070Ssos if (bootverbose) 54766583Ssos ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 54866070Ssos (error) ? "failed" : "success"); 54966070Ssos if (!error) { 55066070Ssos cyrix_timing(scp, devno, ATA_UDMA2); 55166070Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 55266070Ssos return; 55366070Ssos } 55466070Ssos } 55566070Ssos if (wdmamode >= 2 && apiomode >= 4) { 55666070Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 55766070Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 55866070Ssos if (bootverbose) 55966070Ssos ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 56066070Ssos (error) ? "failed" : "success"); 56166070Ssos if (!error) { 56266070Ssos cyrix_timing(scp, devno, ATA_WDMA2); 56366070Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 56466070Ssos return; 56566070Ssos } 56666070Ssos } 56766070Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 56866070Ssos ata_pio2mode(apiomode), ATA_C_F_SETXFER, 56966070Ssos ATA_WAIT_READY); 57066070Ssos if (bootverbose) 57166070Ssos ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 57266070Ssos (error) ? "failed" : "success", 57366070Ssos ata_mode2str(ata_pio2mode(apiomode))); 57466070Ssos cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 57566070Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 57666070Ssos return; 57766070Ssos 57866583Ssos case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 57966583Ssos if (udmamode >= 2) { 58066583Ssos u_int16_t reg56; 58166583Ssos 58266583Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 58366583Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 58466583Ssos if (bootverbose) 58566583Ssos ata_printf(scp, device, 58666583Ssos "%s setting UDMA2 on ServerWorks chip\n", 58766583Ssos (error) ? "failed" : "success"); 58866583Ssos if (!error) { 58966583Ssos pci_write_config(parent, 0x54, 59066583Ssos pci_read_config(parent, 0x54, 1) | 59166583Ssos (0x01 << devno), 1); 59266583Ssos reg56 = pci_read_config(parent, 0x56, 2); 59366583Ssos reg56 &= ~(0xf << (devno * 4)); 59466583Ssos reg56 |= (0x2 << (devno * 4)); 59566583Ssos pci_write_config(parent, 0x56, reg56, 2); 59666583Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 59766583Ssos return; 59866583Ssos } 59966583Ssos } 60066583Ssos if (wdmamode >= 2 && apiomode >= 4) { 60166583Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 60266583Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 60366583Ssos if (bootverbose) 60466583Ssos ata_printf(scp, device, 60566583Ssos "%s setting WDMA2 on ServerWorks chip\n", 60666583Ssos (error) ? "failed" : "success"); 60766583Ssos if (!error) { 60867058Ssos int offset = (scp->channel * 2) + (device == ATA_MASTER); 60966583Ssos int word44 = pci_read_config(parent, 0x44, 4); 61066583Ssos 61166583Ssos pci_write_config(parent, 0x54, 61266583Ssos pci_read_config(parent, 0x54, 1) & 61366583Ssos ~(0x01 << devno), 1); 61466583Ssos word44 &= ~(0xff << (offset << 8)); 61566583Ssos word44 |= (0x20 << (offset << 8)); 61666583Ssos pci_write_config(parent, 0x44, 0x20, 4); 61766583Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 61866583Ssos return; 61966583Ssos } 62066583Ssos } 62166583Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 62266583Ssos break; 62366583Ssos 62466070Ssos case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 62566070Ssos case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 62666070Ssos case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 62766070Ssos case 0x0d30105a: /* Promise OEM ATA100 controllers */ 62852067Ssos /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 62952067Ssos if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 63052067Ssos (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 63152067Ssos break; 63252067Ssos 63366326Ssos if (udmamode >= 5 && 63466070Ssos (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 63567058Ssos !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 63652918Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 63764307Ssos ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 63864307Ssos if (bootverbose) 63964307Ssos ata_printf(scp, device, 64064695Ssos "%s setting UDMA5 on Promise chip\n", 64164307Ssos (error) ? "failed" : "success"); 64264307Ssos if (!error) { 64364307Ssos promise_timing(scp, devno, ATA_UDMA5); 64464307Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 64564307Ssos return; 64664307Ssos } 64764307Ssos } 64866326Ssos if (udmamode >= 4 && (scp->chiptype == 0x4d38105a || 64966070Ssos scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 65067058Ssos !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){ 65164307Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 65253029Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 65352918Ssos if (bootverbose) 65456558Ssos ata_printf(scp, device, 65564695Ssos "%s setting UDMA4 on Promise chip\n", 65656558Ssos (error) ? "failed" : "success"); 65753681Ssos if (!error) { 65855333Ssos promise_timing(scp, devno, ATA_UDMA4); 65956558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 66056744Ssos return; 66153681Ssos } 66252918Ssos } 66353681Ssos if (udmamode >= 2) { 66445095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 66553029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 66651520Ssos if (bootverbose) 66756558Ssos ata_printf(scp, device, 66864695Ssos "%s setting UDMA2 on Promise chip\n", 66956558Ssos (error) ? "failed" : "success"); 67053681Ssos if (!error) { 67155333Ssos promise_timing(scp, devno, ATA_UDMA2); 67256558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 67356744Ssos return; 67453681Ssos } 67545095Ssos } 67653681Ssos if (wdmamode >= 2 && apiomode >= 4) { 67745095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 67853029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 67951520Ssos if (bootverbose) 68056558Ssos ata_printf(scp, device, 68164695Ssos "%s setting WDMA2 on Promise chip\n", 68256558Ssos (error) ? "failed" : "success"); 68353681Ssos if (!error) { 68455333Ssos promise_timing(scp, devno, ATA_WDMA2); 68556558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 68656744Ssos return; 68753681Ssos } 68851520Ssos } 68955333Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 69055333Ssos ata_pio2mode(apiomode), 69155333Ssos ATA_C_F_SETXFER, ATA_WAIT_READY); 69253681Ssos if (bootverbose) 69356558Ssos ata_printf(scp, device, 69464695Ssos "%s setting PIO%d on Promise chip\n", 69556558Ssos (error) ? "failed" : "success", 69656558Ssos (apiomode >= 0) ? apiomode : 0); 69756686Ssos promise_timing(scp, devno, ata_pio2mode(apiomode)); 69856686Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 69956744Ssos return; 70045095Ssos 70164307Ssos case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 70253681Ssos /* no ATAPI devices for now */ 70351520Ssos if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 70452067Ssos (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 70552067Ssos break; 70651520Ssos 70764307Ssos if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 70867058Ssos !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 70952067Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 71064307Ssos ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 71164307Ssos if (bootverbose) 71264307Ssos ata_printf(scp, device, 71367057Ssos "%s setting UDMA5 on HighPoint chip\n", 71464307Ssos (error) ? "failed" : "success"); 71564307Ssos if (!error) { 71664307Ssos hpt_timing(scp, devno, ATA_UDMA5); 71764307Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 71864307Ssos return; 71964307Ssos } 72064307Ssos } 72164307Ssos if (udmamode >=4 && 72267058Ssos !(pci_read_config(parent, 0x5a, 1) & (scp->channel ? 0x01:0x02))) { 72364307Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 72453029Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 72552067Ssos if (bootverbose) 72656558Ssos ata_printf(scp, device, 72767057Ssos "%s setting UDMA4 on HighPoint chip\n", 72856558Ssos (error) ? "failed" : "success"); 72953681Ssos if (!error) { 73064307Ssos hpt_timing(scp, devno, ATA_UDMA4); 73156558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 73256744Ssos return; 73353681Ssos } 73451520Ssos } 73553681Ssos if (udmamode >= 2) { 73652067Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 73753029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 73851520Ssos if (bootverbose) 73956558Ssos ata_printf(scp, device, 74067057Ssos "%s setting UDMA2 on HighPoint chip\n", 74156558Ssos (error) ? "failed" : "success"); 74253681Ssos if (!error) { 74364307Ssos hpt_timing(scp, devno, ATA_UDMA2); 74456558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 74556744Ssos return; 74653681Ssos } 74745095Ssos } 74853681Ssos if (wdmamode >= 2 && apiomode >= 4) { 74945095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 75053029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 75151520Ssos if (bootverbose) 75256558Ssos ata_printf(scp, device, 75367057Ssos "%s setting WDMA2 on HighPoint chip\n", 75456558Ssos (error) ? "failed" : "success"); 75553681Ssos if (!error) { 75664307Ssos hpt_timing(scp, devno, ATA_WDMA2); 75756558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 75856744Ssos return; 75953681Ssos } 76045095Ssos } 76155333Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 76255333Ssos ata_pio2mode(apiomode), 76355333Ssos ATA_C_F_SETXFER, ATA_WAIT_READY); 76453681Ssos if (bootverbose) 76567057Ssos ata_printf(scp, device, "%s setting PIO%d on HighPoint chip\n", 76656558Ssos (error) ? "failed" : "success", 76756558Ssos (apiomode >= 0) ? apiomode : 0); 76864307Ssos hpt_timing(scp, devno, ata_pio2mode(apiomode)); 76956686Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 77056744Ssos return; 77145095Ssos 77251548Ssos default: /* unknown controller chip */ 77351548Ssos /* better not try generic DMA on ATAPI devices it almost never works */ 77451548Ssos if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 77551548Ssos (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 77651548Ssos break; 77751548Ssos 77856744Ssos /* if controller says its setup for DMA take the easy way out */ 77956744Ssos /* the downside is we dont know what DMA mode we are in */ 78056744Ssos if ((udmamode >= 0 || wdmamode > 1) && 78156744Ssos (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 78256744Ssos ((device==ATA_MASTER) ? 78356744Ssos ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 78456744Ssos scp->mode[ATA_DEV(device)] = ATA_DMA; 78556744Ssos return; 78656744Ssos } 78756744Ssos 78851548Ssos /* well, we have no support for this, but try anyways */ 78954594Ssos if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 79045095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 79153029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 79251520Ssos if (bootverbose) 79356558Ssos ata_printf(scp, device, 79464695Ssos "%s setting WDMA2 on generic chip\n", 79556558Ssos (error) ? "failed" : "success"); 79653681Ssos if (!error) { 79756558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 79856744Ssos return; 79953681Ssos } 80045095Ssos } 80145095Ssos } 80256988Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 80356988Ssos ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 80455333Ssos if (bootverbose) 80564695Ssos ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 80656988Ssos (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 80756988Ssos if (!error) 80856988Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 80957771Ssos else { 81056988Ssos if (bootverbose) 81156988Ssos ata_printf(scp, device, "using PIO mode set by BIOS\n"); 81257771Ssos scp->mode[ATA_DEV(device)] = ATA_PIO; 81357771Ssos } 81445095Ssos} 81545095Ssos 81666070Ssosint 81766070Ssosata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 81866070Ssos caddr_t data, int32_t count) 81945095Ssos{ 82045095Ssos u_int32_t dma_count, dma_base; 82164307Ssos int i = 0; 82245095Ssos 82366070Ssos if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 82466070Ssos ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 82545095Ssos return -1; 82666070Ssos } 82745095Ssos 82845095Ssos if (!count) { 82956558Ssos ata_printf(scp, device, "zero length DMA transfer attempted\n"); 83045095Ssos return -1; 83145095Ssos } 83245095Ssos 83345095Ssos dma_base = vtophys(data); 83456558Ssos dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 83545095Ssos data += dma_count; 83645095Ssos count -= dma_count; 83745095Ssos 83845095Ssos while (count) { 83945095Ssos dmatab[i].base = dma_base; 84045095Ssos dmatab[i].count = (dma_count & 0xffff); 84145095Ssos i++; 84245095Ssos if (i >= ATA_DMA_ENTRIES) { 84356558Ssos ata_printf(scp, device, "too many segments in DMA table\n"); 84445095Ssos return -1; 84545095Ssos } 84645095Ssos dma_base = vtophys(data); 84756558Ssos dma_count = min(count, PAGE_SIZE); 84856558Ssos data += min(count, PAGE_SIZE); 84956558Ssos count -= min(count, PAGE_SIZE); 85045095Ssos } 85145095Ssos dmatab[i].base = dma_base; 85245095Ssos dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 85345095Ssos return 0; 85445095Ssos} 85545095Ssos 85645095Ssosvoid 85766070Ssosata_dmastart(struct ata_softc *scp, int device, 85866070Ssos struct ata_dmaentry *dmatab, int dir) 85945095Ssos{ 86052067Ssos scp->flags |= ATA_DMA_ACTIVE; 86166070Ssos outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 86266070Ssos outb(scp->bmaddr + ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 86366070Ssos outb(scp->bmaddr + ATA_BMSTAT_PORT, 86466070Ssos (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 86566070Ssos (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 86645095Ssos outb(scp->bmaddr + ATA_BMCMD_PORT, 86745095Ssos inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 86845095Ssos} 86945095Ssos 87066070Ssosint 87152067Ssosata_dmadone(struct ata_softc *scp) 87245095Ssos{ 87345095Ssos outb(scp->bmaddr + ATA_BMCMD_PORT, 87445095Ssos inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 87552067Ssos scp->flags &= ~ATA_DMA_ACTIVE; 87645095Ssos return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 87745095Ssos} 87845095Ssos 87966070Ssosint 88052067Ssosata_dmastatus(struct ata_softc *scp) 88145095Ssos{ 88245095Ssos return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 88345095Ssos} 88445095Ssos 88552067Ssosstatic void 88666070Ssoscyrix_timing(struct ata_softc *scp, int devno, int mode) 88752067Ssos{ 88866070Ssos u_int32_t reg20 = 0x0000e132; 88966070Ssos u_int32_t reg24 = 0x00017771; 89066070Ssos 89166070Ssos switch (mode) { 89266070Ssos case ATA_PIO0: reg20 = 0x0000e132; break; 89366070Ssos case ATA_PIO1: reg20 = 0x00018121; break; 89466070Ssos case ATA_PIO2: reg20 = 0x00024020; break; 89566070Ssos case ATA_PIO3: reg20 = 0x00032010; break; 89666070Ssos case ATA_PIO4: reg20 = 0x00040010; break; 89766070Ssos case ATA_WDMA2: reg24 = 0x00002020; break; 89866070Ssos case ATA_UDMA2: reg24 = 0x00911030; break; 89966070Ssos } 90066070Ssos outl(scp->bmaddr + (devno * 8) + 0x20, reg20); 90166070Ssos outl(scp->bmaddr + (devno * 8) + 0x24, reg24); 90266070Ssos} 90366070Ssos 90466070Ssosstatic void 90566070Ssospromise_timing(struct ata_softc *scp, int devno, int mode) 90666070Ssos{ 90756988Ssos u_int32_t timing = 0; 90856988Ssos struct promise_timing { 90956988Ssos u_int8_t pa:4; 91056988Ssos u_int8_t prefetch:1; 91156988Ssos u_int8_t iordy:1; 91256988Ssos u_int8_t errdy:1; 91356988Ssos u_int8_t syncin:1; 91456988Ssos u_int8_t pb:5; 91556988Ssos u_int8_t mb:3; 91656988Ssos u_int8_t mc:4; 91756988Ssos u_int8_t dmaw:1; 91856988Ssos u_int8_t dmar:1; 91956988Ssos u_int8_t iordyp:1; 92056988Ssos u_int8_t dmarqp:1; 92156988Ssos u_int8_t reserved:8; 92256988Ssos } *t = (struct promise_timing*)&timing; 92356988Ssos 92456988Ssos t->iordy = 1; t->iordyp = 1; 92556988Ssos if (mode >= ATA_DMA) { 92656988Ssos t->prefetch = 1; t->errdy = 1; t->syncin = 1; 92755333Ssos } 92856988Ssos 92956988Ssos switch (scp->chiptype) { 93066070Ssos case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 93156988Ssos switch (mode) { 93256988Ssos default: 93356988Ssos case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 93456988Ssos case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 93556988Ssos case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 93656988Ssos case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 93756988Ssos case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 93856988Ssos case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 93956988Ssos case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 94056988Ssos } 94156988Ssos break; 94256988Ssos 94366070Ssos case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 94466070Ssos case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 94566070Ssos case 0x0d30105a: /* Promise OEM ATA 100 */ 94656988Ssos switch (mode) { 94756988Ssos default: 94856988Ssos case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 94956988Ssos case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 95056988Ssos case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 95156988Ssos case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 95256988Ssos case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 95356988Ssos case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 95456988Ssos case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 95556988Ssos case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 95664307Ssos case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 95756988Ssos } 95856988Ssos break; 95956988Ssos } 96057325Ssos pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 96155333Ssos} 96252067Ssos 96355333Ssosstatic void 96466070Ssoshpt_timing(struct ata_softc *scp, int devno, int mode) 96555333Ssos{ 96657325Ssos device_t parent = device_get_parent(scp->dev); 96755333Ssos u_int32_t timing; 96855333Ssos 96964307Ssos if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 97052067Ssos switch (mode) { 97164307Ssos case ATA_PIO0: timing = 0x06914e57; break; 97264307Ssos case ATA_PIO1: timing = 0x06914e43; break; 97364307Ssos case ATA_PIO2: timing = 0x06514e33; break; 97464307Ssos case ATA_PIO3: timing = 0x06514e22; break; 97564307Ssos case ATA_PIO4: timing = 0x06514e21; break; 97664307Ssos case ATA_WDMA2: timing = 0x26514e21; break; 97764307Ssos case ATA_UDMA2: timing = 0x16494e31; break; 97864307Ssos case ATA_UDMA4: timing = 0x16454e31; break; 97964307Ssos case ATA_UDMA5: timing = 0x16454e31; break; 98064307Ssos default: timing = 0x06514e57; 98152067Ssos } 98264307Ssos pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 98364307Ssos pci_write_config(parent, 0x5b, 0x22, 1); 98464307Ssos } 98564307Ssos else { /* HPT36[68] */ 98664307Ssos switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 98764307Ssos case 0x85: /* 25Mhz */ 98864307Ssos switch (mode) { 98964307Ssos case ATA_PIO0: timing = 0xc0d08585; break; 99064307Ssos case ATA_PIO1: timing = 0xc0d08572; break; 99164307Ssos case ATA_PIO2: timing = 0xc0ca8542; break; 99264307Ssos case ATA_PIO3: timing = 0xc0ca8532; break; 99364307Ssos case ATA_PIO4: timing = 0xc0ca8521; break; 99464307Ssos case ATA_WDMA2: timing = 0xa0ca8521; break; 99564307Ssos case ATA_UDMA2: timing = 0x90cf8521; break; 99664307Ssos case ATA_UDMA4: timing = 0x90c98521; break; 99764307Ssos default: timing = 0x01208585; 99864307Ssos } 99964307Ssos break; 100064307Ssos default: 100164307Ssos case 0xa7: /* 33MHz */ 100264307Ssos switch (mode) { 100364307Ssos case ATA_PIO0: timing = 0xc0d0a7aa; break; 100464307Ssos case ATA_PIO1: timing = 0xc0d0a7a3; break; 100564307Ssos case ATA_PIO2: timing = 0xc0d0a753; break; 100664307Ssos case ATA_PIO3: timing = 0xc0c8a742; break; 100764307Ssos case ATA_PIO4: timing = 0xc0c8a731; break; 100864307Ssos case ATA_WDMA2: timing = 0xa0c8a731; break; 100964307Ssos case ATA_UDMA2: timing = 0x90caa731; break; 101064307Ssos case ATA_UDMA4: timing = 0x90c9a731; break; 101164307Ssos default: timing = 0x0120a7a7; 101264307Ssos } 101364307Ssos break; 101464307Ssos case 0xd9: /* 40Mhz */ 101564307Ssos switch (mode) { 101664307Ssos case ATA_PIO0: timing = 0xc018d9d9; break; 101764307Ssos case ATA_PIO1: timing = 0xc010d9c7; break; 101864307Ssos case ATA_PIO2: timing = 0xc010d997; break; 101964307Ssos case ATA_PIO3: timing = 0xc010d974; break; 102064307Ssos case ATA_PIO4: timing = 0xc008d963; break; 102164307Ssos case ATA_WDMA2: timing = 0xa008d943; break; 102264307Ssos case ATA_UDMA2: timing = 0x900bd943; break; 102364307Ssos case ATA_UDMA4: timing = 0x900fd943; break; 102464307Ssos default: timing = 0x0120d9d9; 102564307Ssos } 102652067Ssos } 102764307Ssos pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 102852067Ssos } 102952067Ssos} 103052067Ssos 103145095Ssos#else /* NPCI > 0 */ 103245095Ssos 103367067Ssosvoid * 103467067Ssosata_dmaalloc(struct ata_softc *scp, int device) 103567067Ssos{ 103667435Ssos return 0; 103767067Ssos} 103867067Ssos 103956754Ssosvoid 104066070Ssosata_dmainit(struct ata_softc *scp, int device, 104166070Ssos int piomode, int wdmamode, int udmamode) 104245095Ssos{ 104345095Ssos} 104445095Ssos 104566070Ssosint 104667067Ssosata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 104767067Ssos caddr_t data, int32_t count) 104845095Ssos{ 104945095Ssos return -1; 105045095Ssos} 105145095Ssos 105267067Ssosvoid 105367067Ssosata_dmastart(struct ata_softc *scp, int device, 105467067Ssos struct ata_dmaentry *dmatab, int dir) 105545095Ssos{ 105645095Ssos} 105745095Ssos 105866070Ssosint 105952067Ssosata_dmadone(struct ata_softc *scp) 106045095Ssos{ 106145095Ssos return -1; 106245095Ssos} 106345095Ssos 106466070Ssosint 106552067Ssosata_dmastatus(struct ata_softc *scp) 106645095Ssos{ 106745095Ssos return -1; 106845095Ssos} 106945095Ssos 107045095Ssos#endif /* NPCI > 0 */ 1071