ata-dma.c revision 66326
145095Ssos/*- 255333Ssos * Copyright (c) 1998,1999,2000 S�ren Schmidt 345095Ssos * All rights reserved. 445095Ssos * 545095Ssos * Redistribution and use in source and binary forms, with or without 645095Ssos * modification, are permitted provided that the following conditions 745095Ssos * are met: 845095Ssos * 1. Redistributions of source code must retain the above copyright 945095Ssos * notice, this list of conditions and the following disclaimer, 1045095Ssos * without modification, immediately at the beginning of the file. 1145095Ssos * 2. Redistributions in binary form must reproduce the above copyright 1245095Ssos * notice, this list of conditions and the following disclaimer in the 1345095Ssos * documentation and/or other materials provided with the distribution. 1445095Ssos * 3. The name of the author may not be used to endorse or promote products 1545095Ssos * derived from this software without specific prior written permission. 1645095Ssos * 1745095Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1845095Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1945095Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2045095Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2145095Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2245095Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2345095Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2445095Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2545095Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2645095Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2745095Ssos * 2850477Speter * $FreeBSD: head/sys/dev/ata/ata-dma.c 66326 2000-09-24 18:19:43Z sos $ 2945095Ssos */ 3045095Ssos 3145150Ssos#include "pci.h" 3245095Ssos#include <sys/param.h> 3345095Ssos#include <sys/systm.h> 3460041Sphk#include <sys/bio.h> 3545095Ssos#include <sys/malloc.h> 3645798Ssos#include <sys/bus.h> 3754270Ssos#include <sys/disk.h> 3854270Ssos#include <sys/devicestat.h> 3951520Ssos#include <vm/vm.h> 4045095Ssos#include <vm/pmap.h> 4147272Ssos#if NPCI > 0 4245095Ssos#include <pci/pcivar.h> 4347272Ssos#endif 4466106Ssos#include <machine/bus.h> 4545095Ssos#include <dev/ata/ata-all.h> 4645095Ssos 4756754Ssos#if NPCI > 0 4856754Ssos 4952067Ssos/* prototypes */ 5066070Ssosstatic void cyrix_timing(struct ata_softc *, int, int); 5166070Ssosstatic void promise_timing(struct ata_softc *, int, int); 5266070Ssosstatic void hpt_timing(struct ata_softc *, int, int); 5352067Ssos 5452067Ssos/* misc defines */ 5545720Speter#ifdef __alpha__ 5645720Speter#undef vtophys 5751520Ssos#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 5845720Speter#endif 5945720Speter 6066070Ssosvoid * 6166070Ssosata_dmaalloc(struct ata_softc *scp, int device) 6266070Ssos{ 6366070Ssos void *dmatab; 6466070Ssos 6566070Ssos if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) { 6666070Ssos if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 6766070Ssos (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 6866070Ssos ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 6966070Ssos free(dmatab, M_DEVBUF); 7066070Ssos dmatab = NULL; 7166070Ssos } 7266070Ssos } 7366070Ssos return dmatab; 7466070Ssos} 7566070Ssos 7656744Ssosvoid 7766070Ssosata_dmainit(struct ata_softc *scp, int device, 7866070Ssos int apiomode, int wdmamode, int udmamode) 7945095Ssos{ 8057325Ssos device_t parent = device_get_parent(scp->dev); 8164307Ssos int devno = (scp->unit << 1) + ATA_DEV(device); 8264307Ssos int error; 8345095Ssos 8456744Ssos /* set our most pessimistic default mode */ 8556744Ssos scp->mode[ATA_DEV(device)] = ATA_PIO; 8656744Ssos 8745095Ssos if (!scp->bmaddr) 8856744Ssos return; 8945095Ssos 9052067Ssos /* if simplex controller, only allow DMA on primary channel */ 9152067Ssos if (scp->unit == 1) { 9252067Ssos outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 9352067Ssos (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 9452067Ssos if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 9556558Ssos ata_printf(scp, device, "simplex device, DMA on primary only\n"); 9656744Ssos return; 9752067Ssos } 9852067Ssos } 9952067Ssos 10066070Ssos /* DMA engine address alignment is usually 1 word (2 bytes) */ 10166070Ssos scp->alignment = 0x1; 10245095Ssos 10360829Ssos if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 10460829Ssos ata_printf(scp, device, 10564027Ssteve "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 10660829Ssos udmamode = 2; 10760829Ssos } 10845095Ssos 10955333Ssos switch (scp->chiptype) { 11045095Ssos 11164307Ssos case 0x244b8086: /* Intel ICH2 */ 11264307Ssos if (udmamode >= 5) { 11364307Ssos int32_t mask48, new48; 11464307Ssos int16_t word54; 11564307Ssos 11664307Ssos word54 = pci_read_config(parent, 0x54, 2); 11764307Ssos if (word54 & (0x10 << devno)) { 11864307Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 11964307Ssos ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 12064307Ssos if (bootverbose) 12164307Ssos ata_printf(scp, device, 12264695Ssos "%s setting UDMA5 on ICH2 chip\n", 12364307Ssos (error) ? "failed" : "success"); 12464307Ssos if (!error) { 12564307Ssos mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 12664307Ssos new48 = (1 << devno) + (1 << (16 + (devno << 2))); 12764307Ssos pci_write_config(parent, 0x48, 12864307Ssos (pci_read_config(parent, 0x48, 4) & 12964307Ssos ~mask48) | new48, 4); 13064479Ssos pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 13164307Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 13264307Ssos return; 13364307Ssos } 13464307Ssos } 13564307Ssos } 13664479Ssos /* make sure eventual ATA100 mode from the BIOS is disabled */ 13764479Ssos pci_write_config(parent, 0x54, 13864479Ssos pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 13964307Ssos /* FALLTHROUGH */ 14064307Ssos 14157391Ssos case 0x24118086: /* Intel ICH */ 14257391Ssos if (udmamode >= 4) { 14357391Ssos int32_t mask48, new48; 14457391Ssos int16_t word54; 14557391Ssos 14657391Ssos word54 = pci_read_config(parent, 0x54, 2); 14757391Ssos if (word54 & (0x10 << devno)) { 14857391Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 14957391Ssos ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 15057391Ssos if (bootverbose) 15157391Ssos ata_printf(scp, device, 15264695Ssos "%s setting UDMA4 on ICH%s chip\n", 15364307Ssos (error) ? "failed" : "success", 15464307Ssos (scp->chiptype == 0x244b8086) ? "2" : ""); 15557391Ssos if (!error) { 15657391Ssos mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 15757391Ssos new48 = (1 << devno) + (2 << (16 + (devno << 2))); 15857391Ssos pci_write_config(parent, 0x48, 15957391Ssos (pci_read_config(parent, 0x48, 4) & 16057391Ssos ~mask48) | new48, 4); 16157391Ssos pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 16257391Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 16357391Ssos return; 16457391Ssos } 16557391Ssos } 16657391Ssos } 16764479Ssos /* make sure eventual ATA66 mode from the BIOS is disabled */ 16864479Ssos pci_write_config(parent, 0x54, 16964479Ssos pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 17057391Ssos /* FALLTHROUGH */ 17157391Ssos 17245095Ssos case 0x71118086: /* Intel PIIX4 */ 17356138Ssos case 0x71998086: /* Intel PIIX4e */ 17456138Ssos case 0x24218086: /* Intel ICH0 */ 17545095Ssos if (udmamode >= 2) { 17651520Ssos int32_t mask48, new48; 17745095Ssos 17845095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 17953029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 18051520Ssos if (bootverbose) 18164695Ssos ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 18256558Ssos (error) ? "failed" : "success", 18364307Ssos (scp->chiptype == 0x244b8086) ? "ICH2" : 18464307Ssos (scp->chiptype == 0x24118086) ? "ICH" : 18564307Ssos (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 18653681Ssos if (!error) { 18753681Ssos mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 18853681Ssos new48 = (1 << devno) + (2 << (16 + (devno << 2))); 18957325Ssos pci_write_config(parent, 0x48, 19057325Ssos (pci_read_config(parent, 0x48, 4) & 19153681Ssos ~mask48) | new48, 4); 19256558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 19356744Ssos return; 19453681Ssos } 19545095Ssos } 19664479Ssos /* make sure eventual ATA33 mode from the BIOS is disabled */ 19764479Ssos pci_write_config(parent, 0x48, 19864479Ssos pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 19945095Ssos /* FALLTHROUGH */ 20045095Ssos 20145095Ssos case 0x70108086: /* Intel PIIX3 */ 20245095Ssos if (wdmamode >= 2 && apiomode >= 4) { 20345095Ssos int32_t mask40, new40, mask44, new44; 20445095Ssos 20545095Ssos /* if SITRE not set doit for both channels */ 20657325Ssos if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 20757325Ssos new40 = pci_read_config(parent, 0x40, 4); 20857325Ssos new44 = pci_read_config(parent, 0x44, 4); 20951520Ssos if (!(new40 & 0x00004000)) { 21051520Ssos new44 &= ~0x0000000f; 21151520Ssos new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 21251520Ssos } 21351520Ssos if (!(new40 & 0x40000000)) { 21451520Ssos new44 &= ~0x000000f0; 21551520Ssos new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 21651520Ssos } 21751520Ssos new40 |= 0x40004000; 21857325Ssos pci_write_config(parent, 0x40, new40, 4); 21957325Ssos pci_write_config(parent, 0x44, new44, 4); 22045095Ssos } 22145095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 22253029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 22351520Ssos if (bootverbose) 22464695Ssos ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 22556558Ssos (error) ? "failed" : "success", 22664307Ssos (scp->chiptype == 0x244b8086) ? "ICH2" : 22756558Ssos (scp->chiptype == 0x24118086) ? "ICH" : 22864307Ssos (scp->chiptype == 0x24218086) ? "ICH0" : 22964307Ssos (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4"); 23053681Ssos if (!error) { 23153681Ssos if (device == ATA_MASTER) { 23253681Ssos mask40 = 0x0000330f; 23353681Ssos new40 = 0x00002307; 23453681Ssos mask44 = 0; 23553681Ssos new44 = 0; 23653681Ssos } 23753681Ssos else { 23853681Ssos mask40 = 0x000000f0; 23953681Ssos new40 = 0x00000070; 24053681Ssos mask44 = 0x0000000f; 24153681Ssos new44 = 0x0000000b; 24253681Ssos } 24353681Ssos if (scp->unit) { 24453681Ssos mask40 <<= 16; 24553681Ssos new40 <<= 16; 24653681Ssos mask44 <<= 4; 24753681Ssos new44 <<= 4; 24853681Ssos } 24957325Ssos pci_write_config(parent, 0x40, 25057325Ssos (pci_read_config(parent, 0x40, 4) & ~mask40)| 25153681Ssos new40, 4); 25257325Ssos pci_write_config(parent, 0x44, 25357325Ssos (pci_read_config(parent, 0x44, 4) & ~mask44)| 25453681Ssos new44, 4); 25556558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 25656744Ssos return; 25745095Ssos } 25851520Ssos } 25953681Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 26045095Ssos break; 26145095Ssos 26245095Ssos case 0x12308086: /* Intel PIIX */ 26354544Ssos if (wdmamode >= 2 && apiomode >= 4) { 26454544Ssos int32_t word40; 26554544Ssos 26657325Ssos word40 = pci_read_config(parent, 0x40, 4); 26754544Ssos word40 >>= scp->unit * 16; 26854544Ssos 26954544Ssos /* Check for timing config usable for DMA on controller */ 27054544Ssos if (!((word40 & 0x3300) == 0x2300 && 27154544Ssos ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 27254544Ssos break; 27354544Ssos 27454544Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 27554544Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 27654544Ssos if (bootverbose) 27756558Ssos ata_printf(scp, device, 27864695Ssos "%s setting WDMA2 on PIIX chip\n", 27956558Ssos (error) ? "failed" : "success"); 28054544Ssos if (!error) { 28156558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 28256744Ssos return; 28354544Ssos } 28454544Ssos } 28545095Ssos break; 28645095Ssos 28752067Ssos case 0x522910b9: /* AcerLabs Aladdin IV/V */ 28853029Ssos /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 28953029Ssos if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 29056558Ssos ata_printf(scp, device, 29156558Ssos "Aladdin: two atapi devices on this channel, no DMA\n"); 29253029Ssos break; 29352067Ssos } 29466070Ssos if (udmamode >= 2 && pci_read_config(parent, 0x08, 1) > 0x20) { 29557325Ssos int32_t word54 = pci_read_config(parent, 0x54, 4); 29652067Ssos 29751520Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 29853029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 29951520Ssos if (bootverbose) 30056558Ssos ata_printf(scp, device, 30164695Ssos "%s setting UDMA2 on Aladdin chip\n", 30256558Ssos (error) ? "failed" : "success"); 30353681Ssos if (!error) { 30460829Ssos word54 &= ~(0x000f000f << (devno << 2)); 30560829Ssos word54 |= (0x000a0005 << (devno << 2)); 30657325Ssos pci_write_config(parent, 0x54, word54, 4); 30757325Ssos pci_write_config(parent, 0x53, 30857325Ssos pci_read_config(parent, 0x53, 1) | 0x03, 1); 30953681Ssos scp->flags |= ATA_ATAPI_DMA_RO; 31056558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 31156744Ssos return; 31253681Ssos } 31351520Ssos } 31453681Ssos if (wdmamode >= 2 && apiomode >= 4) { 31552067Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 31653029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 31752067Ssos if (bootverbose) 31856558Ssos ata_printf(scp, device, 31964695Ssos "%s setting WDMA2 on Aladdin chip\n", 32056558Ssos (error) ? "failed" : "success"); 32153681Ssos if (!error) { 32257325Ssos pci_write_config(parent, 0x53, 32357325Ssos pci_read_config(parent, 0x53, 1) | 0x03, 1); 32453681Ssos scp->flags |= ATA_ATAPI_DMA_RO; 32556558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 32656744Ssos return; 32753681Ssos } 32852067Ssos } 32957771Ssos pci_write_config(parent, 0x53, 33057771Ssos (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 33153681Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 33252067Ssos break; 33352067Ssos 33459103Ssos case 0x74091022: /* AMD 756 */ 33559103Ssos if (udmamode >= 4) { 33659103Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 33759103Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 33859103Ssos if (bootverbose) 33959103Ssos ata_printf(scp, device, 34064695Ssos "%s setting UDMA4 on AMD chip\n", 34159103Ssos (error) ? "failed" : "success"); 34259103Ssos if (!error) { 34359103Ssos pci_write_config(parent, 0x53 - devno, 0xc3, 1); 34459103Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 34559103Ssos return; 34659103Ssos } 34759103Ssos } 34859103Ssos goto via_82c586; 34959103Ssos 35064695Ssos case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 */ 35164695Ssos if (ata_find_dev(parent, 0x06861106, 0) || /* 82C686a */ 35264695Ssos ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 35364695Ssos 35464695Ssos if (udmamode >= 4) { 35564695Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 35664695Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 35764695Ssos if (bootverbose) 35864695Ssos ata_printf(scp, device, 35964695Ssos "%s setting UDMA4 on VIA chip\n", 36064695Ssos (error) ? "failed" : "success"); 36164695Ssos if (!error) { 36264695Ssos pci_write_config(parent, 0x53 - devno, 0xe8, 1); 36364695Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 36464695Ssos return; 36564695Ssos } 36656138Ssos } 36764695Ssos if (udmamode >= 2) { 36864695Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 36964695Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 37064695Ssos if (bootverbose) 37164695Ssos ata_printf(scp, device, 37264695Ssos "%s setting UDMA2 on VIA chip\n", 37364695Ssos (error) ? "failed" : "success"); 37464695Ssos if (!error) { 37564695Ssos pci_write_config(parent, 0x53 - devno, 0xea, 1); 37664695Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 37764695Ssos return; 37864695Ssos } 37956138Ssos } 38056138Ssos } 38164695Ssos else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 38264695Ssos ata_find_dev(parent, 0x05861106, 0x02)) { /* 82C586b */ 38359103Ssosvia_82c586: 38464695Ssos if (udmamode >= 2) { 38564695Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 38664695Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 38764695Ssos if (bootverbose) 38864695Ssos ata_printf(scp, device, "%s setting UDMA2 on %s chip\n", 38964695Ssos (error) ? "failed" : "success", 39064695Ssos (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 39164695Ssos if (!error) { 39264695Ssos pci_write_config(parent, 0x53 - devno, 0xc0, 1); 39364695Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 39464695Ssos return; 39564695Ssos } 39653681Ssos } 39753681Ssos } 39853681Ssos if (wdmamode >= 2 && apiomode >= 4) { 39953681Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 40053681Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 40153681Ssos if (bootverbose) 40264695Ssos ata_printf(scp, device, "%s setting WDMA2 on %s chip\n", 40356558Ssos (error) ? "failed" : "success", 40456558Ssos (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 40553681Ssos if (!error) { 40657325Ssos pci_write_config(parent, 0x53 - devno, 0x82, 1); 40757325Ssos pci_write_config(parent, 0x4b - devno, 0x31, 1); 40856558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 40956744Ssos return; 41053681Ssos } 41153681Ssos } 41253681Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 41353681Ssos break; 41453681Ssos 41554544Ssos case 0x55131039: /* SiS 5591 */ 41654544Ssos if (udmamode >= 2) { 41754544Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 41854544Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 41954544Ssos if (bootverbose) 42056558Ssos ata_printf(scp, device, 42164695Ssos "%s setting UDMA2 on SiS chip\n", 42256558Ssos (error) ? "failed" : "success"); 42354544Ssos if (!error) { 42457325Ssos pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 42556558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 42656744Ssos return; 42754544Ssos } 42854544Ssos } 42954544Ssos if (wdmamode >=2 && apiomode >= 4) { 43054544Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 43154544Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 43254544Ssos if (bootverbose) 43356558Ssos ata_printf(scp, device, 43464695Ssos "%s setting WDMA2 on SiS chip\n", 43556558Ssos (error) ? "failed" : "success"); 43654544Ssos if (!error) { 43757325Ssos pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 43856558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 43956744Ssos return; 44054544Ssos } 44154544Ssos } 44254544Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 44354544Ssos break; 44454544Ssos 44557325Ssos case 0x06461095: /* CMD 646 ATA controller */ 44657325Ssos if (wdmamode >= 2 && apiomode >= 4) { 44757325Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 44857325Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 44957325Ssos if (bootverbose) 45057325Ssos ata_printf(scp, device, 45164695Ssos "%s setting WDMA2 on CMD646 chip\n", 45257325Ssos error ? "failed" : "success"); 45357325Ssos if (!error) { 45457325Ssos int32_t offset = (devno < 3) ? (devno << 1) : 7; 45557325Ssos 45657325Ssos pci_write_config(parent, 0x54 + offset, 0x3f, 1); 45757325Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 45857325Ssos return; 45957325Ssos } 46057325Ssos } 46157325Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 46257325Ssos break; 46357325Ssos 46457477Ssos case 0xc6931080: /* Cypress 82c693 ATA controller */ 46557477Ssos if (wdmamode >= 2 && apiomode >= 4) { 46657477Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 46757477Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 46857477Ssos if (bootverbose) 46957477Ssos ata_printf(scp, device, 47064695Ssos "%s setting WDMA2 on Cypress chip\n", 47157477Ssos error ? "failed" : "success"); 47257477Ssos if (!error) { 47357477Ssos pci_write_config(scp->dev, scp->unit ? 0x4e : 0x4c, 0x2020, 2); 47457477Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 47557477Ssos return; 47657477Ssos } 47757477Ssos } 47857477Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 47957477Ssos break; 48057477Ssos 48166070Ssos case 0x01021078: 48266070Ssos scp->alignment = 0xf; /* DMA engine requires 16 byte alignment */ 48366070Ssos if (udmamode >= 2) { 48466070Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 48566070Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 48666070Ssos if (bootverbose) 48766070Ssos ata_printf(scp, device, "%s setting UDMA2 on Cyrix chip\n", 48866070Ssos (error) ? "failed" : "success"); 48966070Ssos if (!error) { 49066070Ssos cyrix_timing(scp, devno, ATA_UDMA2); 49166070Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 49266070Ssos return; 49366070Ssos } 49466070Ssos } 49566070Ssos if (wdmamode >= 2 && apiomode >= 4) { 49666070Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 49766070Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 49866070Ssos if (bootverbose) 49966070Ssos ata_printf(scp, device, "%s setting WDMA2 on Cyrix chip\n", 50066070Ssos (error) ? "failed" : "success"); 50166070Ssos if (!error) { 50266070Ssos cyrix_timing(scp, devno, ATA_WDMA2); 50366070Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 50466070Ssos return; 50566070Ssos } 50666070Ssos } 50766070Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 50866070Ssos ata_pio2mode(apiomode), ATA_C_F_SETXFER, 50966070Ssos ATA_WAIT_READY); 51066070Ssos if (bootverbose) 51166070Ssos ata_printf(scp, device, "%s setting %s on Cyrix chip\n", 51266070Ssos (error) ? "failed" : "success", 51366070Ssos ata_mode2str(ata_pio2mode(apiomode))); 51466070Ssos cyrix_timing(scp, devno, ata_pio2mode(apiomode)); 51566070Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 51666070Ssos return; 51766070Ssos 51866070Ssos case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 51966070Ssos case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 52066070Ssos case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 52166070Ssos case 0x0d30105a: /* Promise OEM ATA100 controllers */ 52252067Ssos /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 52352067Ssos if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 52452067Ssos (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 52552067Ssos break; 52652067Ssos 52766326Ssos if (udmamode >= 5 && 52866070Ssos (scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 52957325Ssos !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 53052918Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 53164307Ssos ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 53264307Ssos if (bootverbose) 53364307Ssos ata_printf(scp, device, 53464695Ssos "%s setting UDMA5 on Promise chip\n", 53564307Ssos (error) ? "failed" : "success"); 53664307Ssos if (!error) { 53764307Ssos promise_timing(scp, devno, ATA_UDMA5); 53864307Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 53964307Ssos return; 54064307Ssos } 54164307Ssos } 54266326Ssos if (udmamode >= 4 && (scp->chiptype == 0x4d38105a || 54366070Ssos scp->chiptype == 0x4d30105a || scp->chiptype == 0x0d30105a) && 54464307Ssos !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 54564307Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 54653029Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 54752918Ssos if (bootverbose) 54856558Ssos ata_printf(scp, device, 54964695Ssos "%s setting UDMA4 on Promise chip\n", 55056558Ssos (error) ? "failed" : "success"); 55153681Ssos if (!error) { 55255333Ssos promise_timing(scp, devno, ATA_UDMA4); 55356558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 55456744Ssos return; 55553681Ssos } 55652918Ssos } 55753681Ssos if (udmamode >= 2) { 55845095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 55953029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 56051520Ssos if (bootverbose) 56156558Ssos ata_printf(scp, device, 56264695Ssos "%s setting UDMA2 on Promise chip\n", 56356558Ssos (error) ? "failed" : "success"); 56453681Ssos if (!error) { 56555333Ssos promise_timing(scp, devno, ATA_UDMA2); 56656558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 56756744Ssos return; 56853681Ssos } 56945095Ssos } 57053681Ssos if (wdmamode >= 2 && apiomode >= 4) { 57145095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 57253029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 57351520Ssos if (bootverbose) 57456558Ssos ata_printf(scp, device, 57564695Ssos "%s setting WDMA2 on Promise chip\n", 57656558Ssos (error) ? "failed" : "success"); 57753681Ssos if (!error) { 57855333Ssos promise_timing(scp, devno, ATA_WDMA2); 57956558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 58056744Ssos return; 58153681Ssos } 58251520Ssos } 58355333Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 58455333Ssos ata_pio2mode(apiomode), 58555333Ssos ATA_C_F_SETXFER, ATA_WAIT_READY); 58653681Ssos if (bootverbose) 58756558Ssos ata_printf(scp, device, 58864695Ssos "%s setting PIO%d on Promise chip\n", 58956558Ssos (error) ? "failed" : "success", 59056558Ssos (apiomode >= 0) ? apiomode : 0); 59156686Ssos promise_timing(scp, devno, ata_pio2mode(apiomode)); 59256686Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 59356744Ssos return; 59445095Ssos 59564307Ssos case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 59653681Ssos /* no ATAPI devices for now */ 59751520Ssos if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 59852067Ssos (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 59952067Ssos break; 60051520Ssos 60164307Ssos if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 60264307Ssos !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) { 60352067Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 60464307Ssos ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 60564307Ssos if (bootverbose) 60664307Ssos ata_printf(scp, device, 60764695Ssos "%s setting UDMA5 on HPT370 chip\n", 60864307Ssos (error) ? "failed" : "success"); 60964307Ssos if (!error) { 61064307Ssos hpt_timing(scp, devno, ATA_UDMA5); 61164307Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 61264307Ssos return; 61364307Ssos } 61464307Ssos } 61564307Ssos 61664307Ssos if (udmamode >=4 && 61764307Ssos !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) { 61864307Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 61953029Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 62052067Ssos if (bootverbose) 62156558Ssos ata_printf(scp, device, 62264695Ssos "%s setting UDMA4 on HPT366 chip\n", 62356558Ssos (error) ? "failed" : "success"); 62453681Ssos if (!error) { 62564307Ssos hpt_timing(scp, devno, ATA_UDMA4); 62656558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 62756744Ssos return; 62853681Ssos } 62951520Ssos } 63053681Ssos if (udmamode >= 2) { 63152067Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 63253029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 63351520Ssos if (bootverbose) 63456558Ssos ata_printf(scp, device, 63564695Ssos "%s setting UDMA2 on HPT366 chip\n", 63656558Ssos (error) ? "failed" : "success"); 63753681Ssos if (!error) { 63864307Ssos hpt_timing(scp, devno, ATA_UDMA2); 63956558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 64056744Ssos return; 64153681Ssos } 64245095Ssos } 64353681Ssos if (wdmamode >= 2 && apiomode >= 4) { 64445095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 64553029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 64651520Ssos if (bootverbose) 64756558Ssos ata_printf(scp, device, 64864695Ssos "%s setting WDMA2 on HPT366 chip\n", 64956558Ssos (error) ? "failed" : "success"); 65053681Ssos if (!error) { 65164307Ssos hpt_timing(scp, devno, ATA_WDMA2); 65256558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 65356744Ssos return; 65453681Ssos } 65545095Ssos } 65655333Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 65755333Ssos ata_pio2mode(apiomode), 65855333Ssos ATA_C_F_SETXFER, ATA_WAIT_READY); 65953681Ssos if (bootverbose) 66064695Ssos ata_printf(scp, device, "%s setting PIO%d on HPT366 chip\n", 66156558Ssos (error) ? "failed" : "success", 66256558Ssos (apiomode >= 0) ? apiomode : 0); 66364307Ssos hpt_timing(scp, devno, ata_pio2mode(apiomode)); 66456686Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 66556744Ssos return; 66645095Ssos 66751548Ssos default: /* unknown controller chip */ 66851548Ssos /* better not try generic DMA on ATAPI devices it almost never works */ 66951548Ssos if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 67051548Ssos (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 67151548Ssos break; 67251548Ssos 67356744Ssos /* if controller says its setup for DMA take the easy way out */ 67456744Ssos /* the downside is we dont know what DMA mode we are in */ 67556744Ssos if ((udmamode >= 0 || wdmamode > 1) && 67656744Ssos (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 67756744Ssos ((device==ATA_MASTER) ? 67856744Ssos ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 67956744Ssos scp->mode[ATA_DEV(device)] = ATA_DMA; 68056744Ssos return; 68156744Ssos } 68256744Ssos 68351548Ssos /* well, we have no support for this, but try anyways */ 68454594Ssos if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 68545095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 68653029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 68751520Ssos if (bootverbose) 68856558Ssos ata_printf(scp, device, 68964695Ssos "%s setting WDMA2 on generic chip\n", 69056558Ssos (error) ? "failed" : "success"); 69153681Ssos if (!error) { 69256558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 69356744Ssos return; 69453681Ssos } 69545095Ssos } 69645095Ssos } 69756988Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 69856988Ssos ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 69955333Ssos if (bootverbose) 70064695Ssos ata_printf(scp, device, "%s setting PIO%d on generic chip\n", 70156988Ssos (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 70256988Ssos if (!error) 70356988Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 70457771Ssos else { 70556988Ssos if (bootverbose) 70656988Ssos ata_printf(scp, device, "using PIO mode set by BIOS\n"); 70757771Ssos scp->mode[ATA_DEV(device)] = ATA_PIO; 70857771Ssos } 70945095Ssos} 71045095Ssos 71166070Ssosint 71266070Ssosata_dmasetup(struct ata_softc *scp, int device, struct ata_dmaentry *dmatab, 71366070Ssos caddr_t data, int32_t count) 71445095Ssos{ 71545095Ssos u_int32_t dma_count, dma_base; 71664307Ssos int i = 0; 71745095Ssos 71866070Ssos if (((uintptr_t)data & scp->alignment) || (count & scp->alignment)) { 71966070Ssos ata_printf(scp, device, "non aligned DMA transfer attempted\n"); 72045095Ssos return -1; 72166070Ssos } 72245095Ssos 72345095Ssos if (!count) { 72456558Ssos ata_printf(scp, device, "zero length DMA transfer attempted\n"); 72545095Ssos return -1; 72645095Ssos } 72745095Ssos 72845095Ssos dma_base = vtophys(data); 72956558Ssos dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 73045095Ssos data += dma_count; 73145095Ssos count -= dma_count; 73245095Ssos 73345095Ssos while (count) { 73445095Ssos dmatab[i].base = dma_base; 73545095Ssos dmatab[i].count = (dma_count & 0xffff); 73645095Ssos i++; 73745095Ssos if (i >= ATA_DMA_ENTRIES) { 73856558Ssos ata_printf(scp, device, "too many segments in DMA table\n"); 73945095Ssos return -1; 74045095Ssos } 74145095Ssos dma_base = vtophys(data); 74256558Ssos dma_count = min(count, PAGE_SIZE); 74356558Ssos data += min(count, PAGE_SIZE); 74456558Ssos count -= min(count, PAGE_SIZE); 74545095Ssos } 74645095Ssos dmatab[i].base = dma_base; 74745095Ssos dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 74845095Ssos return 0; 74945095Ssos} 75045095Ssos 75145095Ssosvoid 75266070Ssosata_dmastart(struct ata_softc *scp, int device, 75366070Ssos struct ata_dmaentry *dmatab, int dir) 75445095Ssos{ 75552067Ssos scp->flags |= ATA_DMA_ACTIVE; 75666070Ssos outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 75766070Ssos outb(scp->bmaddr + ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 75866070Ssos outb(scp->bmaddr + ATA_BMSTAT_PORT, 75966070Ssos (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 76066070Ssos (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 76145095Ssos outb(scp->bmaddr + ATA_BMCMD_PORT, 76245095Ssos inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 76345095Ssos} 76445095Ssos 76566070Ssosint 76652067Ssosata_dmadone(struct ata_softc *scp) 76745095Ssos{ 76845095Ssos outb(scp->bmaddr + ATA_BMCMD_PORT, 76945095Ssos inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 77052067Ssos scp->flags &= ~ATA_DMA_ACTIVE; 77145095Ssos return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 77245095Ssos} 77345095Ssos 77466070Ssosint 77552067Ssosata_dmastatus(struct ata_softc *scp) 77645095Ssos{ 77745095Ssos return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 77845095Ssos} 77945095Ssos 78052067Ssosstatic void 78166070Ssoscyrix_timing(struct ata_softc *scp, int devno, int mode) 78252067Ssos{ 78366070Ssos u_int32_t reg20 = 0x0000e132; 78466070Ssos u_int32_t reg24 = 0x00017771; 78566070Ssos 78666070Ssos switch (mode) { 78766070Ssos case ATA_PIO0: reg20 = 0x0000e132; break; 78866070Ssos case ATA_PIO1: reg20 = 0x00018121; break; 78966070Ssos case ATA_PIO2: reg20 = 0x00024020; break; 79066070Ssos case ATA_PIO3: reg20 = 0x00032010; break; 79166070Ssos case ATA_PIO4: reg20 = 0x00040010; break; 79266070Ssos case ATA_WDMA2: reg24 = 0x00002020; break; 79366070Ssos case ATA_UDMA2: reg24 = 0x00911030; break; 79466070Ssos } 79566070Ssos outl(scp->bmaddr + (devno * 8) + 0x20, reg20); 79666070Ssos outl(scp->bmaddr + (devno * 8) + 0x24, reg24); 79766070Ssos} 79866070Ssos 79966070Ssosstatic void 80066070Ssospromise_timing(struct ata_softc *scp, int devno, int mode) 80166070Ssos{ 80256988Ssos u_int32_t timing = 0; 80356988Ssos struct promise_timing { 80456988Ssos u_int8_t pa:4; 80556988Ssos u_int8_t prefetch:1; 80656988Ssos u_int8_t iordy:1; 80756988Ssos u_int8_t errdy:1; 80856988Ssos u_int8_t syncin:1; 80956988Ssos u_int8_t pb:5; 81056988Ssos u_int8_t mb:3; 81156988Ssos u_int8_t mc:4; 81256988Ssos u_int8_t dmaw:1; 81356988Ssos u_int8_t dmar:1; 81456988Ssos u_int8_t iordyp:1; 81556988Ssos u_int8_t dmarqp:1; 81656988Ssos u_int8_t reserved:8; 81756988Ssos } *t = (struct promise_timing*)&timing; 81856988Ssos 81956988Ssos t->iordy = 1; t->iordyp = 1; 82056988Ssos if (mode >= ATA_DMA) { 82156988Ssos t->prefetch = 1; t->errdy = 1; t->syncin = 1; 82255333Ssos } 82356988Ssos 82456988Ssos switch (scp->chiptype) { 82566070Ssos case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 82656988Ssos switch (mode) { 82756988Ssos default: 82856988Ssos case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 82956988Ssos case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 83056988Ssos case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 83156988Ssos case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 83256988Ssos case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 83356988Ssos case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 83456988Ssos case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 83556988Ssos } 83656988Ssos break; 83756988Ssos 83866070Ssos case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 83966070Ssos case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 84066070Ssos case 0x0d30105a: /* Promise OEM ATA 100 */ 84156988Ssos switch (mode) { 84256988Ssos default: 84356988Ssos case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 84456988Ssos case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 84556988Ssos case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 84656988Ssos case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 84756988Ssos case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 84856988Ssos case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 84956988Ssos case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 85056988Ssos case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 85164307Ssos case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 85256988Ssos } 85356988Ssos break; 85456988Ssos } 85557325Ssos pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 85655333Ssos} 85752067Ssos 85855333Ssosstatic void 85966070Ssoshpt_timing(struct ata_softc *scp, int devno, int mode) 86055333Ssos{ 86157325Ssos device_t parent = device_get_parent(scp->dev); 86255333Ssos u_int32_t timing; 86355333Ssos 86464307Ssos if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 86552067Ssos switch (mode) { 86664307Ssos case ATA_PIO0: timing = 0x06914e57; break; 86764307Ssos case ATA_PIO1: timing = 0x06914e43; break; 86864307Ssos case ATA_PIO2: timing = 0x06514e33; break; 86964307Ssos case ATA_PIO3: timing = 0x06514e22; break; 87064307Ssos case ATA_PIO4: timing = 0x06514e21; break; 87164307Ssos case ATA_WDMA2: timing = 0x26514e21; break; 87264307Ssos case ATA_UDMA2: timing = 0x16494e31; break; 87364307Ssos case ATA_UDMA4: timing = 0x16454e31; break; 87464307Ssos case ATA_UDMA5: timing = 0x16454e31; break; 87564307Ssos default: timing = 0x06514e57; 87652067Ssos } 87764307Ssos pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 87864307Ssos pci_write_config(parent, 0x5b, 0x22, 1); 87964307Ssos } 88064307Ssos else { /* HPT36[68] */ 88164307Ssos switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 88264307Ssos case 0x85: /* 25Mhz */ 88364307Ssos switch (mode) { 88464307Ssos case ATA_PIO0: timing = 0xc0d08585; break; 88564307Ssos case ATA_PIO1: timing = 0xc0d08572; break; 88664307Ssos case ATA_PIO2: timing = 0xc0ca8542; break; 88764307Ssos case ATA_PIO3: timing = 0xc0ca8532; break; 88864307Ssos case ATA_PIO4: timing = 0xc0ca8521; break; 88964307Ssos case ATA_WDMA2: timing = 0xa0ca8521; break; 89064307Ssos case ATA_UDMA2: timing = 0x90cf8521; break; 89164307Ssos case ATA_UDMA4: timing = 0x90c98521; break; 89264307Ssos default: timing = 0x01208585; 89364307Ssos } 89464307Ssos break; 89564307Ssos default: 89664307Ssos case 0xa7: /* 33MHz */ 89764307Ssos switch (mode) { 89864307Ssos case ATA_PIO0: timing = 0xc0d0a7aa; break; 89964307Ssos case ATA_PIO1: timing = 0xc0d0a7a3; break; 90064307Ssos case ATA_PIO2: timing = 0xc0d0a753; break; 90164307Ssos case ATA_PIO3: timing = 0xc0c8a742; break; 90264307Ssos case ATA_PIO4: timing = 0xc0c8a731; break; 90364307Ssos case ATA_WDMA2: timing = 0xa0c8a731; break; 90464307Ssos case ATA_UDMA2: timing = 0x90caa731; break; 90564307Ssos case ATA_UDMA4: timing = 0x90c9a731; break; 90664307Ssos default: timing = 0x0120a7a7; 90764307Ssos } 90864307Ssos break; 90964307Ssos case 0xd9: /* 40Mhz */ 91064307Ssos switch (mode) { 91164307Ssos case ATA_PIO0: timing = 0xc018d9d9; break; 91264307Ssos case ATA_PIO1: timing = 0xc010d9c7; break; 91364307Ssos case ATA_PIO2: timing = 0xc010d997; break; 91464307Ssos case ATA_PIO3: timing = 0xc010d974; break; 91564307Ssos case ATA_PIO4: timing = 0xc008d963; break; 91664307Ssos case ATA_WDMA2: timing = 0xa008d943; break; 91764307Ssos case ATA_UDMA2: timing = 0x900bd943; break; 91864307Ssos case ATA_UDMA4: timing = 0x900fd943; break; 91964307Ssos default: timing = 0x0120d9d9; 92064307Ssos } 92152067Ssos } 92264307Ssos pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 92352067Ssos } 92452067Ssos} 92552067Ssos 92645095Ssos#else /* NPCI > 0 */ 92745095Ssos 92856754Ssosvoid 92966070Ssosata_dmainit(struct ata_softc *scp, int device, 93066070Ssos int piomode, int wdmamode, int udmamode) 93145095Ssos{ 93245095Ssos} 93345095Ssos 93466070Ssosint 93566070Ssosata_dmasetup(struct ata_softc *scp, int device, 93666070Ssos int8_t *data, int32_t count, int flags) 93745095Ssos{ 93845095Ssos return -1; 93945095Ssos} 94045095Ssos 94145095Ssosvoid 94252067Ssosata_dmastart(struct ata_softc *scp) 94345095Ssos{ 94445095Ssos} 94545095Ssos 94666070Ssosint 94752067Ssosata_dmadone(struct ata_softc *scp) 94845095Ssos{ 94945095Ssos return -1; 95045095Ssos} 95145095Ssos 95266070Ssosint 95352067Ssosata_dmastatus(struct ata_softc *scp) 95445095Ssos{ 95545095Ssos return -1; 95645095Ssos} 95745095Ssos 95845095Ssos#endif /* NPCI > 0 */ 959