ata-dma.c revision 64479
145095Ssos/*- 255333Ssos * Copyright (c) 1998,1999,2000 S�ren Schmidt 345095Ssos * All rights reserved. 445095Ssos * 545095Ssos * Redistribution and use in source and binary forms, with or without 645095Ssos * modification, are permitted provided that the following conditions 745095Ssos * are met: 845095Ssos * 1. Redistributions of source code must retain the above copyright 945095Ssos * notice, this list of conditions and the following disclaimer, 1045095Ssos * without modification, immediately at the beginning of the file. 1145095Ssos * 2. Redistributions in binary form must reproduce the above copyright 1245095Ssos * notice, this list of conditions and the following disclaimer in the 1345095Ssos * documentation and/or other materials provided with the distribution. 1445095Ssos * 3. The name of the author may not be used to endorse or promote products 1545095Ssos * derived from this software without specific prior written permission. 1645095Ssos * 1745095Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1845095Ssos * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1945095Ssos * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2045095Ssos * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2145095Ssos * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2245095Ssos * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2345095Ssos * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2445095Ssos * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2545095Ssos * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2645095Ssos * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2745095Ssos * 2850477Speter * $FreeBSD: head/sys/dev/ata/ata-dma.c 64479 2000-08-10 07:34:49Z sos $ 2945095Ssos */ 3045095Ssos 3145150Ssos#include "pci.h" 3245095Ssos#include <sys/param.h> 3345095Ssos#include <sys/systm.h> 3460041Sphk#include <sys/bio.h> 3545095Ssos#include <sys/malloc.h> 3645798Ssos#include <sys/bus.h> 3754270Ssos#include <sys/disk.h> 3854270Ssos#include <sys/devicestat.h> 3951520Ssos#include <vm/vm.h> 4045095Ssos#include <vm/pmap.h> 4147272Ssos#if NPCI > 0 4245095Ssos#include <pci/pcivar.h> 4347272Ssos#endif 4445095Ssos#include <dev/ata/ata-all.h> 4554270Ssos#include <dev/ata/ata-disk.h> 4645095Ssos 4756754Ssos#if NPCI > 0 4856754Ssos 4952067Ssos/* prototypes */ 5055333Ssosstatic void promise_timing(struct ata_softc *, int32_t, int32_t); 5164307Ssosstatic void hpt_timing(struct ata_softc *, int32_t, int32_t); 5252067Ssos 5352067Ssos/* misc defines */ 5445720Speter#ifdef __alpha__ 5545720Speter#undef vtophys 5651520Ssos#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 5745720Speter#endif 5845720Speter 5956744Ssosvoid 6045095Ssosata_dmainit(struct ata_softc *scp, int32_t device, 6145095Ssos int32_t apiomode, int32_t wdmamode, int32_t udmamode) 6245095Ssos{ 6357325Ssos device_t parent = device_get_parent(scp->dev); 6464307Ssos int devno = (scp->unit << 1) + ATA_DEV(device); 6564307Ssos int error; 6645095Ssos 6756744Ssos /* set our most pessimistic default mode */ 6856744Ssos scp->mode[ATA_DEV(device)] = ATA_PIO; 6956744Ssos 7045095Ssos if (!scp->bmaddr) 7156744Ssos return; 7245095Ssos 7352067Ssos /* if simplex controller, only allow DMA on primary channel */ 7452067Ssos if (scp->unit == 1) { 7552067Ssos outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 7652067Ssos (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 7752067Ssos if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 7856558Ssos ata_printf(scp, device, "simplex device, DMA on primary only\n"); 7956744Ssos return; 8052067Ssos } 8152067Ssos } 8252067Ssos 8356558Ssos if (!scp->dmatab[ATA_DEV(device)]) { 8456558Ssos void *dmatab; 8545095Ssos 8656558Ssos if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) 8756744Ssos return; 8856558Ssos if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 8956558Ssos (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 9056558Ssos ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 9156558Ssos free(dmatab, M_DEVBUF); 9256744Ssos return; 9356558Ssos } 9456558Ssos scp->dmatab[ATA_DEV(device)] = dmatab; 9545095Ssos } 9660829Ssos if (udmamode > 2 && !ATA_PARAM(scp, device)->cblid) { 9760829Ssos ata_printf(scp, device, 9864027Ssteve "DMA limited to UDMA33, non-ATA66 compliant cable\n"); 9960829Ssos udmamode = 2; 10060829Ssos } 10145095Ssos 10255333Ssos switch (scp->chiptype) { 10345095Ssos 10464307Ssos case 0x244b8086: /* Intel ICH2 */ 10564307Ssos if (udmamode >= 5) { 10664307Ssos int32_t mask48, new48; 10764307Ssos int16_t word54; 10864307Ssos 10964307Ssos word54 = pci_read_config(parent, 0x54, 2); 11064307Ssos if (word54 & (0x10 << devno)) { 11164307Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 11264307Ssos ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 11364307Ssos if (bootverbose) 11464307Ssos ata_printf(scp, device, 11564307Ssos "%s setting up UDMA5 mode on ICH2 chip\n", 11664307Ssos (error) ? "failed" : "success"); 11764307Ssos if (!error) { 11864307Ssos mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 11964307Ssos new48 = (1 << devno) + (1 << (16 + (devno << 2))); 12064307Ssos pci_write_config(parent, 0x48, 12164307Ssos (pci_read_config(parent, 0x48, 4) & 12264307Ssos ~mask48) | new48, 4); 12364479Ssos pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 12464307Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 12564307Ssos return; 12664307Ssos } 12764307Ssos } 12864307Ssos } 12964479Ssos /* make sure eventual ATA100 mode from the BIOS is disabled */ 13064479Ssos pci_write_config(parent, 0x54, 13164479Ssos pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 13264307Ssos /* FALLTHROUGH */ 13364307Ssos 13457391Ssos case 0x24118086: /* Intel ICH */ 13557391Ssos if (udmamode >= 4) { 13657391Ssos int32_t mask48, new48; 13757391Ssos int16_t word54; 13857391Ssos 13957391Ssos word54 = pci_read_config(parent, 0x54, 2); 14057391Ssos if (word54 & (0x10 << devno)) { 14157391Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 14257391Ssos ATA_UDMA4, ATA_C_F_SETXFER,ATA_WAIT_READY); 14357391Ssos if (bootverbose) 14457391Ssos ata_printf(scp, device, 14564307Ssos "%s setting up UDMA4 mode on ICH%s chip\n", 14664307Ssos (error) ? "failed" : "success", 14764307Ssos (scp->chiptype == 0x244b8086) ? "2" : ""); 14857391Ssos if (!error) { 14957391Ssos mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 15057391Ssos new48 = (1 << devno) + (2 << (16 + (devno << 2))); 15157391Ssos pci_write_config(parent, 0x48, 15257391Ssos (pci_read_config(parent, 0x48, 4) & 15357391Ssos ~mask48) | new48, 4); 15457391Ssos pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 15557391Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 15657391Ssos return; 15757391Ssos } 15857391Ssos } 15957391Ssos } 16064479Ssos /* make sure eventual ATA66 mode from the BIOS is disabled */ 16164479Ssos pci_write_config(parent, 0x54, 16264479Ssos pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 16357391Ssos /* FALLTHROUGH */ 16457391Ssos 16545095Ssos case 0x71118086: /* Intel PIIX4 */ 16656138Ssos case 0x71998086: /* Intel PIIX4e */ 16756138Ssos case 0x24218086: /* Intel ICH0 */ 16845095Ssos if (udmamode >= 2) { 16951520Ssos int32_t mask48, new48; 17045095Ssos 17145095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 17253029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 17351520Ssos if (bootverbose) 17456558Ssos ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 17556558Ssos (error) ? "failed" : "success", 17664307Ssos (scp->chiptype == 0x244b8086) ? "ICH2" : 17764307Ssos (scp->chiptype == 0x24118086) ? "ICH" : 17864307Ssos (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 17953681Ssos if (!error) { 18053681Ssos mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 18153681Ssos new48 = (1 << devno) + (2 << (16 + (devno << 2))); 18257325Ssos pci_write_config(parent, 0x48, 18357325Ssos (pci_read_config(parent, 0x48, 4) & 18453681Ssos ~mask48) | new48, 4); 18556558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 18656744Ssos return; 18753681Ssos } 18845095Ssos } 18964479Ssos /* make sure eventual ATA33 mode from the BIOS is disabled */ 19064479Ssos pci_write_config(parent, 0x48, 19164479Ssos pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 19245095Ssos /* FALLTHROUGH */ 19345095Ssos 19445095Ssos case 0x70108086: /* Intel PIIX3 */ 19545095Ssos if (wdmamode >= 2 && apiomode >= 4) { 19645095Ssos int32_t mask40, new40, mask44, new44; 19745095Ssos 19845095Ssos /* if SITRE not set doit for both channels */ 19957325Ssos if (!((pci_read_config(parent, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 20057325Ssos new40 = pci_read_config(parent, 0x40, 4); 20157325Ssos new44 = pci_read_config(parent, 0x44, 4); 20251520Ssos if (!(new40 & 0x00004000)) { 20351520Ssos new44 &= ~0x0000000f; 20451520Ssos new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 20551520Ssos } 20651520Ssos if (!(new40 & 0x40000000)) { 20751520Ssos new44 &= ~0x000000f0; 20851520Ssos new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 20951520Ssos } 21051520Ssos new40 |= 0x40004000; 21157325Ssos pci_write_config(parent, 0x40, new40, 4); 21257325Ssos pci_write_config(parent, 0x44, new44, 4); 21345095Ssos } 21445095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 21553029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 21651520Ssos if (bootverbose) 21756558Ssos ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 21856558Ssos (error) ? "failed" : "success", 21964307Ssos (scp->chiptype == 0x244b8086) ? "ICH2" : 22056558Ssos (scp->chiptype == 0x24118086) ? "ICH" : 22164307Ssos (scp->chiptype == 0x24218086) ? "ICH0" : 22264307Ssos (scp->chiptype == 0x70108086) ? "PIIX3":"PIIX4"); 22353681Ssos if (!error) { 22453681Ssos if (device == ATA_MASTER) { 22553681Ssos mask40 = 0x0000330f; 22653681Ssos new40 = 0x00002307; 22753681Ssos mask44 = 0; 22853681Ssos new44 = 0; 22953681Ssos } 23053681Ssos else { 23153681Ssos mask40 = 0x000000f0; 23253681Ssos new40 = 0x00000070; 23353681Ssos mask44 = 0x0000000f; 23453681Ssos new44 = 0x0000000b; 23553681Ssos } 23653681Ssos if (scp->unit) { 23753681Ssos mask40 <<= 16; 23853681Ssos new40 <<= 16; 23953681Ssos mask44 <<= 4; 24053681Ssos new44 <<= 4; 24153681Ssos } 24257325Ssos pci_write_config(parent, 0x40, 24357325Ssos (pci_read_config(parent, 0x40, 4) & ~mask40)| 24453681Ssos new40, 4); 24557325Ssos pci_write_config(parent, 0x44, 24657325Ssos (pci_read_config(parent, 0x44, 4) & ~mask44)| 24753681Ssos new44, 4); 24856558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 24956744Ssos return; 25045095Ssos } 25151520Ssos } 25253681Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 25345095Ssos break; 25445095Ssos 25545095Ssos case 0x12308086: /* Intel PIIX */ 25654544Ssos if (wdmamode >= 2 && apiomode >= 4) { 25754544Ssos int32_t word40; 25854544Ssos 25957325Ssos word40 = pci_read_config(parent, 0x40, 4); 26054544Ssos word40 >>= scp->unit * 16; 26154544Ssos 26254544Ssos /* Check for timing config usable for DMA on controller */ 26354544Ssos if (!((word40 & 0x3300) == 0x2300 && 26454544Ssos ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 26554544Ssos break; 26654544Ssos 26754544Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 26854544Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 26954544Ssos if (bootverbose) 27056558Ssos ata_printf(scp, device, 27156558Ssos "%s setting up WDMA2 mode on PIIX chip\n", 27256558Ssos (error) ? "failed" : "success"); 27354544Ssos if (!error) { 27456558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 27556744Ssos return; 27654544Ssos } 27754544Ssos } 27845095Ssos break; 27945095Ssos 28052067Ssos case 0x522910b9: /* AcerLabs Aladdin IV/V */ 28153029Ssos /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 28253029Ssos if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 28356558Ssos ata_printf(scp, device, 28456558Ssos "Aladdin: two atapi devices on this channel, no DMA\n"); 28553029Ssos break; 28652067Ssos } 28753681Ssos if (udmamode >= 2) { 28857325Ssos int32_t word54 = pci_read_config(parent, 0x54, 4); 28952067Ssos 29051520Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 29153029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 29251520Ssos if (bootverbose) 29356558Ssos ata_printf(scp, device, 29456558Ssos "%s setting up UDMA2 mode on Aladdin chip\n", 29556558Ssos (error) ? "failed" : "success"); 29653681Ssos if (!error) { 29760829Ssos word54 &= ~(0x000f000f << (devno << 2)); 29860829Ssos word54 |= (0x000a0005 << (devno << 2)); 29957325Ssos pci_write_config(parent, 0x54, word54, 4); 30057325Ssos pci_write_config(parent, 0x53, 30157325Ssos pci_read_config(parent, 0x53, 1) | 0x03, 1); 30253681Ssos scp->flags |= ATA_ATAPI_DMA_RO; 30356558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 30456744Ssos return; 30553681Ssos } 30651520Ssos } 30753681Ssos if (wdmamode >= 2 && apiomode >= 4) { 30852067Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 30953029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 31052067Ssos if (bootverbose) 31156558Ssos ata_printf(scp, device, 31256558Ssos "%s setting up WDMA2 mode on Aladdin chip\n", 31356558Ssos (error) ? "failed" : "success"); 31453681Ssos if (!error) { 31557325Ssos pci_write_config(parent, 0x53, 31657325Ssos pci_read_config(parent, 0x53, 1) | 0x03, 1); 31753681Ssos scp->flags |= ATA_ATAPI_DMA_RO; 31856558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 31956744Ssos return; 32053681Ssos } 32152067Ssos } 32257771Ssos pci_write_config(parent, 0x53, 32357771Ssos (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 32453681Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 32552067Ssos break; 32652067Ssos 32759103Ssos case 0x74091022: /* AMD 756 */ 32859103Ssos if (udmamode >= 4) { 32959103Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 33059103Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 33159103Ssos if (bootverbose) 33259103Ssos ata_printf(scp, device, 33359103Ssos "%s setting up UDMA4 mode on AMD chip\n", 33459103Ssos (error) ? "failed" : "success"); 33559103Ssos if (!error) { 33659103Ssos pci_write_config(parent, 0x53 - devno, 0xc3, 1); 33759103Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 33859103Ssos return; 33959103Ssos } 34059103Ssos } 34159103Ssos goto via_82c586; 34259103Ssos 34356988Ssos case 0x06861106: /* VIA 82C686 */ 34459103Ssosvia_82c686: 34556988Ssos if (udmamode >= 4) { 34656988Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 34756988Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 34856988Ssos if (bootverbose) 34956988Ssos ata_printf(scp, device, 35056988Ssos "%s setting up UDMA4 mode on VIA chip\n", 35156988Ssos (error) ? "failed" : "success"); 35256988Ssos if (!error) { 35357325Ssos pci_write_config(parent, 0x53 - devno, 0xe8, 1); 35456988Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 35556988Ssos return; 35656138Ssos } 35756988Ssos } 35856988Ssos if (udmamode >= 2) { 35956988Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 36056988Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 36156988Ssos if (bootverbose) 36256988Ssos ata_printf(scp, device, 36356988Ssos "%s setting up UDMA2 mode on VIA chip\n", 36456988Ssos (error) ? "failed" : "success"); 36556988Ssos if (!error) { 36657325Ssos pci_write_config(parent, 0x53 - devno, 0xea, 1); 36756988Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 36856988Ssos return; 36956138Ssos } 37056138Ssos } 37156988Ssos goto via_generic; 37256138Ssos 37359103Ssos case 0x05961106: /* VIA 82C596 */ 37459103Ssos /* 82c596 revision >= 0x12 is like the 82c686 */ 37559103Ssos if (ata_find_dev(parent, 0x05961106, 0x12)) 37659103Ssos goto via_82c686; 37756988Ssos /* FALLTHROUGH */ 37854270Ssos 37956988Ssos case 0x05861106: /* VIA 82C586 */ 38059103Ssosvia_82c586: 38156138Ssos /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */ 38260829Ssos if ((udmamode >= 2 && ata_find_dev(parent, 0x05861106, 0x02)) || 38356988Ssos (udmamode >= 2 && scp->chiptype == 0x05961106) || 38455333Ssos (udmamode >= 2 && scp->chiptype == 0x74091022)) { 38553681Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 38653681Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 38753681Ssos if (bootverbose) 38856558Ssos ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 38956558Ssos (error) ? "failed" : "success", 39056558Ssos (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 39153681Ssos if (!error) { 39257325Ssos pci_write_config(parent, 0x53 - devno, 0xc0, 1); 39356558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 39456744Ssos return; 39553681Ssos } 39653681Ssos } 39756988Ssos /* FALLTHROUGH */ 39856988Ssos 39956988Ssos case 0x05711106: /* VIA 82C571 */ 40056988Ssosvia_generic: 40153681Ssos if (wdmamode >= 2 && apiomode >= 4) { 40253681Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 40353681Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 40453681Ssos if (bootverbose) 40556558Ssos ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 40656558Ssos (error) ? "failed" : "success", 40756558Ssos (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 40853681Ssos if (!error) { 40957325Ssos pci_write_config(parent, 0x53 - devno, 0x82, 1); 41057325Ssos pci_write_config(parent, 0x4b - devno, 0x31, 1); 41156558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 41256744Ssos return; 41353681Ssos } 41453681Ssos } 41553681Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 41653681Ssos break; 41753681Ssos 41854544Ssos case 0x55131039: /* SiS 5591 */ 41954544Ssos if (udmamode >= 2) { 42054544Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 42154544Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 42254544Ssos if (bootverbose) 42356558Ssos ata_printf(scp, device, 42456558Ssos "%s setting up UDMA2 mode on SiS chip\n", 42556558Ssos (error) ? "failed" : "success"); 42654544Ssos if (!error) { 42757325Ssos pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 42856558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 42956744Ssos return; 43054544Ssos } 43154544Ssos } 43254544Ssos if (wdmamode >=2 && apiomode >= 4) { 43354544Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 43454544Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 43554544Ssos if (bootverbose) 43656558Ssos ata_printf(scp, device, 43756558Ssos "%s setting up WDMA2 mode on SiS chip\n", 43856558Ssos (error) ? "failed" : "success"); 43954544Ssos if (!error) { 44057325Ssos pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 44156558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 44256744Ssos return; 44354544Ssos } 44454544Ssos } 44554544Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 44654544Ssos break; 44754544Ssos 44857325Ssos case 0x06461095: /* CMD 646 ATA controller */ 44957325Ssos if (wdmamode >= 2 && apiomode >= 4) { 45057325Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 45157325Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 45257325Ssos if (bootverbose) 45357325Ssos ata_printf(scp, device, 45457325Ssos "%s setting up WDMA2 mode on CMD646 chip\n", 45557325Ssos error ? "failed" : "success"); 45657325Ssos if (!error) { 45757325Ssos int32_t offset = (devno < 3) ? (devno << 1) : 7; 45857325Ssos 45957325Ssos pci_write_config(parent, 0x54 + offset, 0x3f, 1); 46057325Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 46157325Ssos return; 46257325Ssos } 46357325Ssos } 46457325Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 46557325Ssos break; 46657325Ssos 46757477Ssos case 0xc6931080: /* Cypress 82c693 ATA controller */ 46857477Ssos if (wdmamode >= 2 && apiomode >= 4) { 46957477Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 47057477Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 47157477Ssos if (bootverbose) 47257477Ssos ata_printf(scp, device, 47357477Ssos "%s setting up WDMA2 mode on Cypress chip\n", 47457477Ssos error ? "failed" : "success"); 47557477Ssos if (!error) { 47657477Ssos pci_write_config(scp->dev, scp->unit ? 0x4e : 0x4c, 0x2020, 2); 47757477Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 47857477Ssos return; 47957477Ssos } 48057477Ssos } 48157477Ssos /* we could set PIO mode timings, but we assume the BIOS did that */ 48257477Ssos break; 48357477Ssos 48452067Ssos case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 48552067Ssos case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ 48664307Ssos case 0x4d30105a: /* Promise Ultra100 / FastTrak100 controllers */ 48752067Ssos /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 48852067Ssos if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 48952067Ssos (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 49052067Ssos break; 49152067Ssos 49264307Ssos if (udmamode >=5 && scp->chiptype == 0x4d30105a && 49357325Ssos !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 49452918Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 49564307Ssos ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 49664307Ssos if (bootverbose) 49764307Ssos ata_printf(scp, device, 49864307Ssos "%s setting up UDMA5 mode on Promise chip\n", 49964307Ssos (error) ? "failed" : "success"); 50064307Ssos if (!error) { 50164307Ssos promise_timing(scp, devno, ATA_UDMA5); 50264307Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 50364307Ssos return; 50464307Ssos } 50564307Ssos } 50664307Ssos if (udmamode >=4 && 50764307Ssos (scp->chiptype == 0x4d38105a || scp->chiptype == 0x4d30105a) && 50864307Ssos !(pci_read_config(parent, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 50964307Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 51053029Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 51152918Ssos if (bootverbose) 51256558Ssos ata_printf(scp, device, 51356558Ssos "%s setting up UDMA4 mode on Promise chip\n", 51456558Ssos (error) ? "failed" : "success"); 51553681Ssos if (!error) { 51655333Ssos promise_timing(scp, devno, ATA_UDMA4); 51756558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 51856744Ssos return; 51953681Ssos } 52052918Ssos } 52153681Ssos if (udmamode >= 2) { 52245095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 52353029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 52451520Ssos if (bootverbose) 52556558Ssos ata_printf(scp, device, 52656558Ssos "%s setting up UDMA2 mode on Promise chip\n", 52756558Ssos (error) ? "failed" : "success"); 52853681Ssos if (!error) { 52955333Ssos promise_timing(scp, devno, ATA_UDMA2); 53056558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 53156744Ssos return; 53253681Ssos } 53345095Ssos } 53453681Ssos if (wdmamode >= 2 && apiomode >= 4) { 53545095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 53653029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 53751520Ssos if (bootverbose) 53856558Ssos ata_printf(scp, device, 53956558Ssos "%s setting up WDMA2 mode on Promise chip\n", 54056558Ssos (error) ? "failed" : "success"); 54153681Ssos if (!error) { 54255333Ssos promise_timing(scp, devno, ATA_WDMA2); 54356558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 54456744Ssos return; 54553681Ssos } 54651520Ssos } 54755333Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 54855333Ssos ata_pio2mode(apiomode), 54955333Ssos ATA_C_F_SETXFER, ATA_WAIT_READY); 55053681Ssos if (bootverbose) 55156558Ssos ata_printf(scp, device, 55256558Ssos "%s setting up PIO%d mode on Promise chip\n", 55356558Ssos (error) ? "failed" : "success", 55456558Ssos (apiomode >= 0) ? apiomode : 0); 55556686Ssos promise_timing(scp, devno, ata_pio2mode(apiomode)); 55656686Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 55756744Ssos return; 55845095Ssos 55964307Ssos case 0x00041103: /* HighPoint HPT366/368/370 controllers */ 56053681Ssos /* no ATAPI devices for now */ 56151520Ssos if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 56252067Ssos (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 56352067Ssos break; 56451520Ssos 56564307Ssos if (udmamode >=5 && pci_get_revid(parent) >= 0x03 && 56664307Ssos !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) { 56752067Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 56864307Ssos ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 56964307Ssos if (bootverbose) 57064307Ssos ata_printf(scp, device, 57164307Ssos "%s setting up UDMA5 mode on HPT370 chip\n", 57264307Ssos (error) ? "failed" : "success"); 57364307Ssos if (!error) { 57464307Ssos hpt_timing(scp, devno, ATA_UDMA5); 57564307Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA5; 57664307Ssos return; 57764307Ssos } 57864307Ssos } 57964307Ssos 58064307Ssos if (udmamode >=4 && 58164307Ssos !(pci_read_config(parent, 0x5a, 1) & (scp->unit ? 0x01 : 0x02))) { 58264307Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 58353029Ssos ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 58452067Ssos if (bootverbose) 58556558Ssos ata_printf(scp, device, 58656558Ssos "%s setting up UDMA4 mode on HPT366 chip\n", 58756558Ssos (error) ? "failed" : "success"); 58853681Ssos if (!error) { 58964307Ssos hpt_timing(scp, devno, ATA_UDMA4); 59056558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA4; 59156744Ssos return; 59253681Ssos } 59351520Ssos } 59453681Ssos if (udmamode >= 2) { 59552067Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 59653029Ssos ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 59751520Ssos if (bootverbose) 59856558Ssos ata_printf(scp, device, 59956558Ssos "%s setting up UDMA2 mode on HPT366 chip\n", 60056558Ssos (error) ? "failed" : "success"); 60153681Ssos if (!error) { 60264307Ssos hpt_timing(scp, devno, ATA_UDMA2); 60356558Ssos scp->mode[ATA_DEV(device)] = ATA_UDMA2; 60456744Ssos return; 60553681Ssos } 60645095Ssos } 60753681Ssos if (wdmamode >= 2 && apiomode >= 4) { 60845095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 60953029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 61051520Ssos if (bootverbose) 61156558Ssos ata_printf(scp, device, 61256558Ssos "%s setting up WDMA2 mode on HPT366 chip\n", 61356558Ssos (error) ? "failed" : "success"); 61453681Ssos if (!error) { 61564307Ssos hpt_timing(scp, devno, ATA_WDMA2); 61656558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 61756744Ssos return; 61853681Ssos } 61945095Ssos } 62055333Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 62155333Ssos ata_pio2mode(apiomode), 62255333Ssos ATA_C_F_SETXFER, ATA_WAIT_READY); 62353681Ssos if (bootverbose) 62456558Ssos ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n", 62556558Ssos (error) ? "failed" : "success", 62656558Ssos (apiomode >= 0) ? apiomode : 0); 62764307Ssos hpt_timing(scp, devno, ata_pio2mode(apiomode)); 62856686Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 62956744Ssos return; 63045095Ssos 63151548Ssos default: /* unknown controller chip */ 63251548Ssos /* better not try generic DMA on ATAPI devices it almost never works */ 63351548Ssos if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 63451548Ssos (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 63551548Ssos break; 63651548Ssos 63756744Ssos /* if controller says its setup for DMA take the easy way out */ 63856744Ssos /* the downside is we dont know what DMA mode we are in */ 63956744Ssos if ((udmamode >= 0 || wdmamode > 1) && 64056744Ssos (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 64156744Ssos ((device==ATA_MASTER) ? 64256744Ssos ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 64356744Ssos scp->mode[ATA_DEV(device)] = ATA_DMA; 64456744Ssos return; 64556744Ssos } 64656744Ssos 64751548Ssos /* well, we have no support for this, but try anyways */ 64854594Ssos if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 64945095Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 65053029Ssos ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 65151520Ssos if (bootverbose) 65256558Ssos ata_printf(scp, device, 65356558Ssos "%s setting up WDMA2 mode on generic chip\n", 65456558Ssos (error) ? "failed" : "success"); 65553681Ssos if (!error) { 65656558Ssos scp->mode[ATA_DEV(device)] = ATA_WDMA2; 65756744Ssos return; 65853681Ssos } 65945095Ssos } 66045095Ssos } 66156988Ssos error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 66256988Ssos ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 66355333Ssos if (bootverbose) 66456988Ssos ata_printf(scp, device, "%s setting up PIO%d mode on generic chip\n", 66556988Ssos (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 66656988Ssos if (!error) 66756988Ssos scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 66857771Ssos else { 66956988Ssos if (bootverbose) 67056988Ssos ata_printf(scp, device, "using PIO mode set by BIOS\n"); 67157771Ssos scp->mode[ATA_DEV(device)] = ATA_PIO; 67257771Ssos } 67345095Ssos} 67445095Ssos 67545095Ssosint32_t 67645095Ssosata_dmasetup(struct ata_softc *scp, int32_t device, 67745095Ssos int8_t *data, int32_t count, int32_t flags) 67845095Ssos{ 67945095Ssos struct ata_dmaentry *dmatab; 68045095Ssos u_int32_t dma_count, dma_base; 68164307Ssos int i = 0; 68245095Ssos 68345720Speter if (((uintptr_t)data & 1) || (count & 1)) 68445095Ssos return -1; 68545095Ssos 68645095Ssos if (!count) { 68756558Ssos ata_printf(scp, device, "zero length DMA transfer attempted\n"); 68845095Ssos return -1; 68945095Ssos } 69045095Ssos 69156558Ssos dmatab = scp->dmatab[ATA_DEV(device)]; 69245095Ssos dma_base = vtophys(data); 69356558Ssos dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 69445095Ssos data += dma_count; 69545095Ssos count -= dma_count; 69645095Ssos 69745095Ssos while (count) { 69845095Ssos dmatab[i].base = dma_base; 69945095Ssos dmatab[i].count = (dma_count & 0xffff); 70045095Ssos i++; 70145095Ssos if (i >= ATA_DMA_ENTRIES) { 70256558Ssos ata_printf(scp, device, "too many segments in DMA table\n"); 70345095Ssos return -1; 70445095Ssos } 70545095Ssos dma_base = vtophys(data); 70656558Ssos dma_count = min(count, PAGE_SIZE); 70756558Ssos data += min(count, PAGE_SIZE); 70856558Ssos count -= min(count, PAGE_SIZE); 70945095Ssos } 71045095Ssos dmatab[i].base = dma_base; 71145095Ssos dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 71245095Ssos outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 71345095Ssos outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0); 71445095Ssos outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 71545095Ssos (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 71645095Ssos return 0; 71745095Ssos} 71845095Ssos 71945095Ssosvoid 72052067Ssosata_dmastart(struct ata_softc *scp) 72145095Ssos{ 72252067Ssos scp->flags |= ATA_DMA_ACTIVE; 72345095Ssos outb(scp->bmaddr + ATA_BMCMD_PORT, 72445095Ssos inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 72545095Ssos} 72645095Ssos 72745095Ssosint32_t 72852067Ssosata_dmadone(struct ata_softc *scp) 72945095Ssos{ 73045095Ssos outb(scp->bmaddr + ATA_BMCMD_PORT, 73145095Ssos inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 73252067Ssos scp->flags &= ~ATA_DMA_ACTIVE; 73345095Ssos return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 73445095Ssos} 73545095Ssos 73645095Ssosint32_t 73752067Ssosata_dmastatus(struct ata_softc *scp) 73845095Ssos{ 73945095Ssos return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 74045095Ssos} 74145095Ssos 74252067Ssosstatic void 74355333Ssospromise_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 74452067Ssos{ 74556988Ssos u_int32_t timing = 0; 74656988Ssos struct promise_timing { 74756988Ssos u_int8_t pa:4; 74856988Ssos u_int8_t prefetch:1; 74956988Ssos u_int8_t iordy:1; 75056988Ssos u_int8_t errdy:1; 75156988Ssos u_int8_t syncin:1; 75256988Ssos u_int8_t pb:5; 75356988Ssos u_int8_t mb:3; 75456988Ssos u_int8_t mc:4; 75556988Ssos u_int8_t dmaw:1; 75656988Ssos u_int8_t dmar:1; 75756988Ssos u_int8_t iordyp:1; 75856988Ssos u_int8_t dmarqp:1; 75956988Ssos u_int8_t reserved:8; 76056988Ssos } *t = (struct promise_timing*)&timing; 76156988Ssos 76256988Ssos t->iordy = 1; t->iordyp = 1; 76356988Ssos if (mode >= ATA_DMA) { 76456988Ssos t->prefetch = 1; t->errdy = 1; t->syncin = 1; 76555333Ssos } 76656988Ssos 76756988Ssos switch (scp->chiptype) { 76856988Ssos case 0x4d33105a: /* Promise 33's */ 76956988Ssos switch (mode) { 77056988Ssos default: 77156988Ssos case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 77256988Ssos case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 77356988Ssos case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 77456988Ssos case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 77556988Ssos case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 77656988Ssos case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 77756988Ssos case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 77856988Ssos } 77956988Ssos break; 78056988Ssos 78156988Ssos case 0x4d38105a: /* Promise 66's */ 78264307Ssos case 0x4d30105a: /* Promise 100's */ 78356988Ssos switch (mode) { 78456988Ssos default: 78556988Ssos case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 78656988Ssos case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 78756988Ssos case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 78856988Ssos case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 78956988Ssos case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 79056988Ssos case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 79156988Ssos case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 79256988Ssos case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 79364307Ssos case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 79456988Ssos } 79556988Ssos break; 79656988Ssos } 79757325Ssos pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4); 79855333Ssos} 79952067Ssos 80055333Ssosstatic void 80164307Ssoshpt_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 80255333Ssos{ 80357325Ssos device_t parent = device_get_parent(scp->dev); 80455333Ssos u_int32_t timing; 80555333Ssos 80664307Ssos if (pci_get_revid(parent) >= 0x03) { /* HPT370 */ 80752067Ssos switch (mode) { 80864307Ssos case ATA_PIO0: timing = 0x06914e57; break; 80964307Ssos case ATA_PIO1: timing = 0x06914e43; break; 81064307Ssos case ATA_PIO2: timing = 0x06514e33; break; 81164307Ssos case ATA_PIO3: timing = 0x06514e22; break; 81264307Ssos case ATA_PIO4: timing = 0x06514e21; break; 81364307Ssos case ATA_WDMA2: timing = 0x26514e21; break; 81464307Ssos case ATA_UDMA2: timing = 0x16494e31; break; 81564307Ssos case ATA_UDMA4: timing = 0x16454e31; break; 81664307Ssos case ATA_UDMA5: timing = 0x16454e31; break; 81764307Ssos default: timing = 0x06514e57; 81852067Ssos } 81964307Ssos pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 82064307Ssos pci_write_config(parent, 0x5b, 0x22, 1); 82164307Ssos } 82264307Ssos else { /* HPT36[68] */ 82364307Ssos switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 82464307Ssos case 0x85: /* 25Mhz */ 82564307Ssos switch (mode) { 82664307Ssos case ATA_PIO0: timing = 0xc0d08585; break; 82764307Ssos case ATA_PIO1: timing = 0xc0d08572; break; 82864307Ssos case ATA_PIO2: timing = 0xc0ca8542; break; 82964307Ssos case ATA_PIO3: timing = 0xc0ca8532; break; 83064307Ssos case ATA_PIO4: timing = 0xc0ca8521; break; 83164307Ssos case ATA_WDMA2: timing = 0xa0ca8521; break; 83264307Ssos case ATA_UDMA2: timing = 0x90cf8521; break; 83364307Ssos case ATA_UDMA4: timing = 0x90c98521; break; 83464307Ssos default: timing = 0x01208585; 83564307Ssos } 83664307Ssos break; 83764307Ssos default: 83864307Ssos case 0xa7: /* 33MHz */ 83964307Ssos switch (mode) { 84064307Ssos case ATA_PIO0: timing = 0xc0d0a7aa; break; 84164307Ssos case ATA_PIO1: timing = 0xc0d0a7a3; break; 84264307Ssos case ATA_PIO2: timing = 0xc0d0a753; break; 84364307Ssos case ATA_PIO3: timing = 0xc0c8a742; break; 84464307Ssos case ATA_PIO4: timing = 0xc0c8a731; break; 84564307Ssos case ATA_WDMA2: timing = 0xa0c8a731; break; 84664307Ssos case ATA_UDMA2: timing = 0x90caa731; break; 84764307Ssos case ATA_UDMA4: timing = 0x90c9a731; break; 84864307Ssos default: timing = 0x0120a7a7; 84964307Ssos } 85064307Ssos break; 85164307Ssos case 0xd9: /* 40Mhz */ 85264307Ssos switch (mode) { 85364307Ssos case ATA_PIO0: timing = 0xc018d9d9; break; 85464307Ssos case ATA_PIO1: timing = 0xc010d9c7; break; 85564307Ssos case ATA_PIO2: timing = 0xc010d997; break; 85664307Ssos case ATA_PIO3: timing = 0xc010d974; break; 85764307Ssos case ATA_PIO4: timing = 0xc008d963; break; 85864307Ssos case ATA_WDMA2: timing = 0xa008d943; break; 85964307Ssos case ATA_UDMA2: timing = 0x900bd943; break; 86064307Ssos case ATA_UDMA4: timing = 0x900fd943; break; 86164307Ssos default: timing = 0x0120d9d9; 86264307Ssos } 86352067Ssos } 86464307Ssos pci_write_config(parent, 0x40 + (devno << 2), (timing & ~0x80000000),4); 86552067Ssos } 86652067Ssos} 86752067Ssos 86845095Ssos#else /* NPCI > 0 */ 86945095Ssos 87056754Ssosvoid 87145095Ssosata_dmainit(struct ata_softc *scp, int32_t device, 87251520Ssos int32_t piomode, int32_t wdmamode, int32_t udmamode) 87345095Ssos{ 87445095Ssos} 87545095Ssos 87645095Ssosint32_t 87745095Ssosata_dmasetup(struct ata_softc *scp, int32_t device, 87851520Ssos int8_t *data, int32_t count, int32_t flags) 87945095Ssos{ 88045095Ssos return -1; 88145095Ssos} 88245095Ssos 88345095Ssosvoid 88452067Ssosata_dmastart(struct ata_softc *scp) 88545095Ssos{ 88645095Ssos} 88745095Ssos 88845095Ssosint32_t 88952067Ssosata_dmadone(struct ata_softc *scp) 89045095Ssos{ 89145095Ssos return -1; 89245095Ssos} 89345095Ssos 89445095Ssosint32_t 89552067Ssosata_dmastatus(struct ata_softc *scp) 89645095Ssos{ 89745095Ssos return -1; 89845095Ssos} 89945095Ssos 90045095Ssos#endif /* NPCI > 0 */ 901