ata-dma.c revision 56558
1218152Slstewart/*- 2218152Slstewart * Copyright (c) 1998,1999,2000 S�ren Schmidt 3218152Slstewart * All rights reserved. 4218152Slstewart * 5218152Slstewart * Redistribution and use in source and binary forms, with or without 6218152Slstewart * modification, are permitted provided that the following conditions 7218152Slstewart * are met: 8218152Slstewart * 1. Redistributions of source code must retain the above copyright 9220560Slstewart * notice, this list of conditions and the following disclaimer, 10220560Slstewart * without modification, immediately at the beginning of the file. 11220560Slstewart * 2. Redistributions in binary form must reproduce the above copyright 12218152Slstewart * notice, this list of conditions and the following disclaimer in the 13218152Slstewart * documentation and/or other materials provided with the distribution. 14218152Slstewart * 3. The name of the author may not be used to endorse or promote products 15218152Slstewart * derived from this software without specific prior written permission. 16218152Slstewart * 17218152Slstewart * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18218152Slstewart * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19218152Slstewart * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20218152Slstewart * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21218152Slstewart * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22218152Slstewart * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23218152Slstewart * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24218152Slstewart * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25218152Slstewart * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26218152Slstewart * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27218152Slstewart * 28218152Slstewart * $FreeBSD: head/sys/dev/ata/ata-dma.c 56558 2000-01-24 20:45:24Z sos $ 29218152Slstewart */ 30218152Slstewart 31218152Slstewart#include "pci.h" 32218152Slstewart#include "apm.h" 33218152Slstewart#include <sys/param.h> 34218152Slstewart#include <sys/systm.h> 35218152Slstewart#include <sys/buf.h> 36218152Slstewart#include <sys/malloc.h> 37218152Slstewart#include <sys/bus.h> 38218152Slstewart#include <sys/disk.h> 39218152Slstewart#include <sys/devicestat.h> 40218152Slstewart#include <vm/vm.h> 41218152Slstewart#include <vm/pmap.h> 42218152Slstewart#if NPCI > 0 43218152Slstewart#include <pci/pcivar.h> 44218156Slstewart#endif 45218152Slstewart#if NAPM > 0 46218152Slstewart#include <machine/apm_bios.h> 47218152Slstewart#endif 48218152Slstewart#include <dev/ata/ata-all.h> 49220560Slstewart#include <dev/ata/ata-disk.h> 50220560Slstewart 51220560Slstewart/* prototypes */ 52220560Slstewartstatic void promise_timing(struct ata_softc *, int32_t, int32_t); 53218152Slstewartstatic void hpt366_timing(struct ata_softc *, int32_t, int32_t); 54218152Slstewart 55218152Slstewart/* misc defines */ 56218152Slstewart#ifdef __alpha__ 57218152Slstewart#undef vtophys 58218152Slstewart#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 59218152Slstewart#endif 60218152Slstewart 61218152Slstewart#if NPCI > 0 62218152Slstewart 63218152Slstewartint32_t 64218152Slstewartata_dmainit(struct ata_softc *scp, int32_t device, 65218152Slstewart int32_t apiomode, int32_t wdmamode, int32_t udmamode) 66218152Slstewart{ 67218152Slstewart int32_t devno = (scp->unit << 1) + ATA_DEV(device); 68218152Slstewart int32_t error; 69218152Slstewart 70218152Slstewart if (!scp->bmaddr) 71218152Slstewart return -1; 72294535Sglebius 73218152Slstewart /* if simplex controller, only allow DMA on primary channel */ 74218152Slstewart if (scp->unit == 1) { 75294931Sglebius outb(scp->bmaddr + ATA_BMSTAT_PORT, inb(scp->bmaddr + ATA_BMSTAT_PORT) & 76218152Slstewart (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 77218152Slstewart if (inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) { 78218152Slstewart ata_printf(scp, device, "simplex device, DMA on primary only\n"); 79218152Slstewart return -1; 80218152Slstewart } 81218152Slstewart } 82218152Slstewart 83218152Slstewart if (!scp->dmatab[ATA_DEV(device)]) { 84218152Slstewart void *dmatab; 85218152Slstewart 86218152Slstewart if (!(dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) 87218152Slstewart return -1; 88218152Slstewart if (((uintptr_t)dmatab >> PAGE_SHIFT) ^ 89218152Slstewart (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) { 90218152Slstewart ata_printf(scp, device, "dmatab crosses page boundary, no DMA\n"); 91218152Slstewart free(dmatab, M_DEVBUF); 92218152Slstewart return -1; 93218152Slstewart } 94218152Slstewart scp->dmatab[ATA_DEV(device)] = dmatab; 95218152Slstewart } 96218152Slstewart 97218152Slstewart switch (scp->chiptype) { 98218152Slstewart 99218152Slstewart case 0x71118086: /* Intel PIIX4 */ 100218152Slstewart case 0x71998086: /* Intel PIIX4e */ 101218152Slstewart case 0x24118086: /* Intel ICH */ 102218152Slstewart case 0x24218086: /* Intel ICH0 */ 103218152Slstewart if (udmamode >= 2) { 104218152Slstewart int32_t mask48, new48; 105218152Slstewart 106220592Spluknet error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 107218152Slstewart ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 108218152Slstewart if (bootverbose) 109218152Slstewart ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 110218152Slstewart (error) ? "failed" : "success", 111218152Slstewart (scp->chiptype == 0x24118086) ? "ICH" : 112218152Slstewart (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 113218152Slstewart if (!error) { 114218152Slstewart mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 115218152Slstewart new48 = (1 << devno) + (2 << (16 + (devno << 2))); 116218152Slstewart pci_write_config(scp->dev, 0x48, 117218152Slstewart (pci_read_config(scp->dev, 0x48, 4) & 118218152Slstewart ~mask48) | new48, 4); 119218152Slstewart scp->mode[ATA_DEV(device)] = ATA_UDMA2; 120218152Slstewart return 0; 121218152Slstewart } 122218152Slstewart } 123218152Slstewart /* FALLTHROUGH */ 124218152Slstewart 125218152Slstewart case 0x70108086: /* Intel PIIX3 */ 126218152Slstewart if (wdmamode >= 2 && apiomode >= 4) { 127218152Slstewart int32_t mask40, new40, mask44, new44; 128218152Slstewart 129218152Slstewart /* if SITRE not set doit for both channels */ 130218152Slstewart if (!((pci_read_config(scp->dev, 0x40, 4)>>(scp->unit<<8))&0x4000)){ 131218152Slstewart new40 = pci_read_config(scp->dev, 0x40, 4); 132218152Slstewart new44 = pci_read_config(scp->dev, 0x44, 4); 133218152Slstewart if (!(new40 & 0x00004000)) { 134218152Slstewart new44 &= ~0x0000000f; 135218152Slstewart new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 136218152Slstewart } 137218152Slstewart if (!(new40 & 0x40000000)) { 138218152Slstewart new44 &= ~0x000000f0; 139218152Slstewart new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 140218152Slstewart } 141218152Slstewart new40 |= 0x40004000; 142218152Slstewart pci_write_config(scp->dev, 0x40, new40, 4); 143218152Slstewart pci_write_config(scp->dev, 0x44, new44, 4); 144218152Slstewart } 145218152Slstewart error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 146218152Slstewart ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 147218152Slstewart if (bootverbose) 148218152Slstewart ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 149218152Slstewart (error) ? "failed" : "success", 150218152Slstewart (scp->chiptype == 0x70108086) ? "PIIX3" : 151218152Slstewart (scp->chiptype == 0x24118086) ? "ICH" : 152218152Slstewart (scp->chiptype == 0x24218086) ? "ICH0" :"PIIX4"); 153218152Slstewart if (!error) { 154218152Slstewart if (device == ATA_MASTER) { 155218152Slstewart mask40 = 0x0000330f; 156218152Slstewart new40 = 0x00002307; 157218152Slstewart mask44 = 0; 158218152Slstewart new44 = 0; 159218152Slstewart } 160218152Slstewart else { 161218152Slstewart mask40 = 0x000000f0; 162218152Slstewart new40 = 0x00000070; 163218152Slstewart mask44 = 0x0000000f; 164218152Slstewart new44 = 0x0000000b; 165218152Slstewart } 166218152Slstewart if (scp->unit) { 167218152Slstewart mask40 <<= 16; 168218152Slstewart new40 <<= 16; 169218152Slstewart mask44 <<= 4; 170218152Slstewart new44 <<= 4; 171218152Slstewart } 172218152Slstewart pci_write_config(scp->dev, 0x40, 173218152Slstewart (pci_read_config(scp->dev, 0x40, 4) & ~mask40)| 174218152Slstewart new40, 4); 175218152Slstewart pci_write_config(scp->dev, 0x44, 176218152Slstewart (pci_read_config(scp->dev, 0x44, 4) & ~mask44)| 177218152Slstewart new44, 4); 178218152Slstewart scp->mode[ATA_DEV(device)] = ATA_WDMA2; 179218152Slstewart return 0; 180218152Slstewart } 181218152Slstewart } 182218152Slstewart /* we could set PIO mode timings, but we assume the BIOS did that */ 183218152Slstewart break; 184218152Slstewart 185218152Slstewart case 0x12308086: /* Intel PIIX */ 186218152Slstewart if (wdmamode >= 2 && apiomode >= 4) { 187218152Slstewart int32_t word40; 188218152Slstewart 189218152Slstewart word40 = pci_read_config(scp->dev, 0x40, 4); 190218152Slstewart word40 >>= scp->unit * 16; 191218152Slstewart 192218152Slstewart /* Check for timing config usable for DMA on controller */ 193218152Slstewart if (!((word40 & 0x3300) == 0x2300 && 194218152Slstewart ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1)) 195218152Slstewart break; 196218152Slstewart 197218152Slstewart error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 198218152Slstewart ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 199218152Slstewart if (bootverbose) 200218152Slstewart ata_printf(scp, device, 201218152Slstewart "%s setting up WDMA2 mode on PIIX chip\n", 202218152Slstewart (error) ? "failed" : "success"); 203218152Slstewart if (!error) { 204218152Slstewart scp->mode[ATA_DEV(device)] = ATA_WDMA2; 205218152Slstewart return 0; 206218152Slstewart } 207218152Slstewart } 208218152Slstewart break; 209218152Slstewart 210218152Slstewart case 0x522910b9: /* AcerLabs Aladdin IV/V */ 211218152Slstewart /* the Aladdin doesn't support ATAPI DMA on both master & slave */ 212218152Slstewart if (scp->devices & ATA_ATAPI_MASTER && scp->devices & ATA_ATAPI_SLAVE) { 213218152Slstewart ata_printf(scp, device, 214218152Slstewart "Aladdin: two atapi devices on this channel, no DMA\n"); 215218152Slstewart break; 216218152Slstewart } 217218152Slstewart if (udmamode >= 2) { 218218152Slstewart int32_t word54 = pci_read_config(scp->dev, 0x54, 4); 219218152Slstewart 220218152Slstewart error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 221218152Slstewart ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 222218152Slstewart if (bootverbose) 223218152Slstewart ata_printf(scp, device, 224218152Slstewart "%s setting up UDMA2 mode on Aladdin chip\n", 225218152Slstewart (error) ? "failed" : "success"); 226218152Slstewart if (!error) { 227218152Slstewart word54 |= 0x5555; 228218152Slstewart word54 |= (0x0a << (16 + (scp->unit << 3) + (device << 2))); 229218152Slstewart pci_write_config(scp->dev, 0x54, word54, 4); 230218152Slstewart pci_write_config(scp->dev, 0x53, 231218152Slstewart pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 232218152Slstewart scp->flags |= ATA_ATAPI_DMA_RO; 233218152Slstewart scp->mode[ATA_DEV(device)] = ATA_UDMA2; 234218152Slstewart return 0; 235218152Slstewart } 236218152Slstewart } 237218152Slstewart if (wdmamode >= 2 && apiomode >= 4) { 238218152Slstewart error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 239218152Slstewart ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 240218152Slstewart if (bootverbose) 241218152Slstewart ata_printf(scp, device, 242218152Slstewart "%s setting up WDMA2 mode on Aladdin chip\n", 243218152Slstewart (error) ? "failed" : "success"); 244218152Slstewart if (!error) { 245218152Slstewart pci_write_config(scp->dev, 0x53, 246218152Slstewart pci_read_config(scp->dev, 0x53, 1) | 0x03, 1); 247218152Slstewart scp->flags |= ATA_ATAPI_DMA_RO; 248218152Slstewart scp->mode[ATA_DEV(device)] = ATA_WDMA2; 249218152Slstewart return 0; 250218152Slstewart } 251218152Slstewart } 252218152Slstewart /* we could set PIO mode timings, but we assume the BIOS did that */ 253218152Slstewart break; 254218152Slstewart 255218152Slstewart case 0x05711106: /* VIA 82C571, 82C586, 82C596 & 82C686 */ 256218152Slstewart case 0x74091022: /* AMD 756 */ 257218152Slstewart /* UDMA modes on 82C686 */ 258218152Slstewart if (ata_find_dev(scp->dev, 0x06861106)) { 259218152Slstewart if (udmamode >= 4) { 260218152Slstewart error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 261218152Slstewart ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 262218152Slstewart if (bootverbose) 263218152Slstewart ata_printf(scp, device, "%s setting up UDMA4 mode on VIA chip\n", 264218152Slstewart (error) ? "failed" : "success"); 265218152Slstewart if (!error) { 266218152Slstewart pci_write_config(scp->dev, 0x53 - devno, 0xe8, 1); 267218152Slstewart scp->mode[ATA_DEV(device)] = ATA_UDMA4; 268218152Slstewart return 0; 269218152Slstewart } 270218152Slstewart } 271218152Slstewart if (udmamode >= 2) { 272218152Slstewart error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 273218152Slstewart ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 274218152Slstewart if (bootverbose) 275218152Slstewart ata_printf(scp, device, 276218152Slstewart "%s setting up UDMA2 mode on VIA chip\n", 277218152Slstewart (error) ? "failed" : "success"); 278218152Slstewart if (!error) { 279218152Slstewart pci_write_config(scp->dev, 0x53 - devno, 0xea, 1); 280218152Slstewart scp->mode[ATA_DEV(device)] = ATA_UDMA2; 281218152Slstewart return 0; 282218152Slstewart } 283218152Slstewart } 284218152Slstewart } 285218152Slstewart 286218152Slstewart /* UDMA4 mode on AMD 756 */ 287218152Slstewart if (udmamode >= 4 && scp->chiptype == 0x74091022) { 288218152Slstewart error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 289218152Slstewart ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 290218152Slstewart if (bootverbose) 291218152Slstewart ata_printf(scp, device, 292218152Slstewart "%s setting up UDMA4 mode on AMD chip\n", 293218152Slstewart (error) ? "failed" : "success"); 294218152Slstewart if (!error) { 295218152Slstewart pci_write_config(scp->dev, 0x53 - devno, 0xc3, 1); 296274225Sglebius scp->mode[ATA_DEV(device)] = ATA_UDMA4; 297274225Sglebius return 0; 298274225Sglebius } 299274225Sglebius } 300218152Slstewart 301274225Sglebius /* UDMA2 mode only on 82C586 > rev1, 82C596, AMD 756 */ 302274225Sglebius if ((udmamode >= 2 && ata_find_dev(scp->dev, 0x05861106) && 303274225Sglebius pci_read_config(scp->dev, 0x08, 1) >= 0x01) || 304274225Sglebius (udmamode >= 2 && ata_find_dev(scp->dev, 0x05961106)) || 305218152Slstewart (udmamode >= 2 && scp->chiptype == 0x74091022)) { 306218152Slstewart error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 307218152Slstewart ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 308 if (bootverbose) 309 ata_printf(scp, device, "%s setting up UDMA2 mode on %s chip\n", 310 (error) ? "failed" : "success", 311 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 312 if (!error) { 313 pci_write_config(scp->dev, 0x53 - devno, 0xc0, 1); 314 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 315 return 0; 316 } 317 } 318 if (wdmamode >= 2 && apiomode >= 4) { 319 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 320 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 321 if (bootverbose) 322 ata_printf(scp, device, "%s setting up WDMA2 mode on %s chip\n", 323 (error) ? "failed" : "success", 324 (scp->chiptype == 0x74091022) ? "AMD" : "VIA"); 325 if (!error) { 326 pci_write_config(scp->dev, 0x53 - devno, 0x82, 1); 327 pci_write_config(scp->dev, 0x4b - devno, 0x31, 1); 328 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 329 return 0; 330 } 331 } 332 /* we could set PIO mode timings, but we assume the BIOS did that */ 333 break; 334 335 case 0x55131039: /* SiS 5591 */ 336 if (udmamode >= 2) { 337 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 338 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 339 if (bootverbose) 340 ata_printf(scp, device, 341 "%s setting up UDMA2 mode on SiS chip\n", 342 (error) ? "failed" : "success"); 343 if (!error) { 344 pci_write_config(scp->dev, 0x40 + (devno << 1), 0xa301, 2); 345 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 346 return 0; 347 } 348 } 349 if (wdmamode >=2 && apiomode >= 4) { 350 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 351 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 352 if (bootverbose) 353 ata_printf(scp, device, 354 "%s setting up WDMA2 mode on SiS chip\n", 355 (error) ? "failed" : "success"); 356 if (!error) { 357 pci_write_config(scp->dev, 0x40 + (devno << 1), 0x0301, 2); 358 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 359 return 0; 360 } 361 } 362 /* we could set PIO mode timings, but we assume the BIOS did that */ 363 break; 364 365 case 0x4d33105a: /* Promise Ultra33 / FastTrak33 controllers */ 366 case 0x4d38105a: /* Promise Ultra66 / FastTrak66 controllers */ 367 /* the Promise can only do DMA on ATA disks not on ATAPI devices */ 368 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 369 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 370 break; 371 372 if (udmamode >=4 && scp->chiptype == 0x4d38105a && 373 !(pci_read_config(scp->dev, 0x50, 2)&(scp->unit ? 1<<11 : 1<<10))) { 374 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 375 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 376 if (bootverbose) 377 ata_printf(scp, device, 378 "%s setting up UDMA4 mode on Promise chip\n", 379 (error) ? "failed" : "success"); 380 if (!error) { 381 outb(scp->bmaddr+0x11, inl(scp->bmaddr+0x11) | scp->unit ? 8:2); 382 promise_timing(scp, devno, ATA_UDMA4); 383 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 384 return 0; 385 } 386 } 387 if (udmamode >= 2) { 388 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 389 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 390 if (bootverbose) 391 ata_printf(scp, device, 392 "%s setting up UDMA2 mode on Promise chip\n", 393 (error) ? "failed" : "success"); 394 if (!error) { 395 promise_timing(scp, devno, ATA_UDMA2); 396 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 397 return 0; 398 } 399 } 400 if (wdmamode >= 2 && apiomode >= 4) { 401 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 402 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 403 if (bootverbose) 404 ata_printf(scp, device, 405 "%s setting up WDMA2 mode on Promise chip\n", 406 (error) ? "failed" : "success"); 407 if (!error) { 408 promise_timing(scp, devno, ATA_WDMA2); 409 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 410 return 0; 411 } 412 } 413 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 414 ata_pio2mode(apiomode), 415 ATA_C_F_SETXFER, ATA_WAIT_READY); 416 if (bootverbose) 417 ata_printf(scp, device, 418 "%s setting up PIO%d mode on Promise chip\n", 419 (error) ? "failed" : "success", 420 (apiomode >= 0) ? apiomode : 0); 421 if (!error) { 422 promise_timing(scp, devno, ata_pio2mode(apiomode)); 423 return 0; 424 } 425 break; 426 427 case 0x00041103: /* HighPoint HPT366 controller */ 428 /* no ATAPI devices for now */ 429 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 430 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 431 break; 432 433 if (udmamode >=4 && !(pci_read_config(scp->dev, 0x5a, 1) & 0x2)) { 434 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 435 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 436 if (bootverbose) 437 ata_printf(scp, device, 438 "%s setting up UDMA4 mode on HPT366 chip\n", 439 (error) ? "failed" : "success"); 440 if (!error) { 441 hpt366_timing(scp, devno, ATA_UDMA4); 442 scp->mode[ATA_DEV(device)] = ATA_UDMA4; 443 return 0; 444 } 445 } 446 if (udmamode >= 2) { 447 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 448 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 449 if (bootverbose) 450 ata_printf(scp, device, 451 "%s setting up UDMA2 mode on HPT366 chip\n", 452 (error) ? "failed" : "success"); 453 if (!error) { 454 hpt366_timing(scp, devno, ATA_UDMA2); 455 scp->mode[ATA_DEV(device)] = ATA_UDMA2; 456 return 0; 457 } 458 } 459 if (wdmamode >= 2 && apiomode >= 4) { 460 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 461 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 462 if (bootverbose) 463 ata_printf(scp, device, 464 "%s setting up WDMA2 mode on HPT366 chip\n", 465 (error) ? "failed" : "success"); 466 if (!error) { 467 hpt366_timing(scp, devno, ATA_WDMA2); 468 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 469 return 0; 470 } 471 } 472 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 473 ata_pio2mode(apiomode), 474 ATA_C_F_SETXFER, ATA_WAIT_READY); 475 if (bootverbose) 476 ata_printf(scp, device, "%s setting up PIO%d mode on HPT366 chip\n", 477 (error) ? "failed" : "success", 478 (apiomode >= 0) ? apiomode : 0); 479 if (!error) { 480 hpt366_timing(scp, devno, ata_pio2mode(apiomode)); 481 return 0; 482 } 483 break; 484 485 default: /* unknown controller chip */ 486 /* better not try generic DMA on ATAPI devices it almost never works */ 487 if ((device == ATA_MASTER && scp->devices & ATA_ATAPI_MASTER) || 488 (device == ATA_SLAVE && scp->devices & ATA_ATAPI_SLAVE)) 489 break; 490 491 /* well, we have no support for this, but try anyways */ 492 if ((wdmamode >= 2 && apiomode >= 4) && scp->bmaddr) { 493#if MAYBE_NOT 494 && (inb(scp->bmaddr + ATA_BMSTAT_PORT) & 495 ((device == ATA_MASTER) ? 496 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) { 497#endif 498 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 499 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 500 if (bootverbose) 501 ata_printf(scp, device, 502 "%s setting up WDMA2 mode on generic chip\n", 503 (error) ? "failed" : "success"); 504 if (!error) { 505 scp->mode[ATA_DEV(device)] = ATA_WDMA2; 506 return 0; 507 } 508 } 509 } 510 error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0, 511 ata_pio2mode(apiomode), ATA_C_F_SETXFER,ATA_WAIT_READY); 512 if (bootverbose) 513 ata_printf(scp, device, "%s setting up PIO%d mode on generic chip\n", 514 (error) ? "failed" : "success",(apiomode>=0) ? apiomode : 0); 515 if (!error) 516 scp->mode[ATA_DEV(device)] = ata_pio2mode(apiomode); 517 return -1; 518} 519 520int32_t 521ata_dmasetup(struct ata_softc *scp, int32_t device, 522 int8_t *data, int32_t count, int32_t flags) 523{ 524 struct ata_dmaentry *dmatab; 525 u_int32_t dma_count, dma_base; 526 int32_t i = 0; 527 528 if (((uintptr_t)data & 1) || (count & 1)) 529 return -1; 530 531 if (!count) { 532 ata_printf(scp, device, "zero length DMA transfer attempted\n"); 533 return -1; 534 } 535 536 dmatab = scp->dmatab[ATA_DEV(device)]; 537 dma_base = vtophys(data); 538 dma_count = min(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK))); 539 data += dma_count; 540 count -= dma_count; 541 542 while (count) { 543 dmatab[i].base = dma_base; 544 dmatab[i].count = (dma_count & 0xffff); 545 i++; 546 if (i >= ATA_DMA_ENTRIES) { 547 ata_printf(scp, device, "too many segments in DMA table\n"); 548 return -1; 549 } 550 dma_base = vtophys(data); 551 dma_count = min(count, PAGE_SIZE); 552 data += min(count, PAGE_SIZE); 553 count -= min(count, PAGE_SIZE); 554 } 555 dmatab[i].base = dma_base; 556 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT; 557 outl(scp->bmaddr + ATA_BMDTP_PORT, vtophys(dmatab)); 558 outb(scp->bmaddr + ATA_BMCMD_PORT, flags ? ATA_BMCMD_WRITE_READ:0); 559 outb(scp->bmaddr + ATA_BMSTAT_PORT, (inb(scp->bmaddr + ATA_BMSTAT_PORT) | 560 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 561 return 0; 562} 563 564void 565ata_dmastart(struct ata_softc *scp) 566{ 567 scp->flags |= ATA_DMA_ACTIVE; 568 outb(scp->bmaddr + ATA_BMCMD_PORT, 569 inb(scp->bmaddr + ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 570} 571 572int32_t 573ata_dmadone(struct ata_softc *scp) 574{ 575 outb(scp->bmaddr + ATA_BMCMD_PORT, 576 inb(scp->bmaddr + ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 577 scp->flags &= ~ATA_DMA_ACTIVE; 578 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 579} 580 581int32_t 582ata_dmastatus(struct ata_softc *scp) 583{ 584 return inb(scp->bmaddr + ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 585} 586 587static void 588promise_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 589{ 590 u_int32_t timing; 591 switch (mode) { 592 default: 593 case ATA_PIO0: timing = 0x004ff329; break; 594 case ATA_PIO1: timing = 0x004fec25; break; 595 case ATA_PIO2: timing = 0x004fe823; break; 596 case ATA_PIO3: timing = 0x004fe622; break; 597 case ATA_PIO4: timing = 0x004fe421; break; 598 case ATA_WDMA2: timing = 0x004367f3; break; 599 case ATA_UDMA2: timing = 0x004127f3; break; 600 case ATA_UDMA4: timing = 0x004127f3; break; 601 } 602 pci_write_config(scp->dev, 0x60 + (devno << 2), timing, 4); 603} 604 605static void 606hpt366_timing(struct ata_softc *scp, int32_t devno, int32_t mode) 607{ 608 u_int32_t timing; 609 610 switch (pci_read_config(scp->dev, 0x41 + (devno << 2), 1)) { 611 case 0x85: /* 25Mhz */ 612 switch (mode) { 613 case ATA_PIO0: timing = 0xc0d08585; break; 614 case ATA_PIO1: timing = 0xc0d08572; break; 615 case ATA_PIO2: timing = 0xc0ca8542; break; 616 case ATA_PIO3: timing = 0xc0ca8532; break; 617 case ATA_PIO4: timing = 0xc0ca8521; break; 618 case ATA_WDMA2: timing = 0xa0ca8521; break; 619 case ATA_UDMA2: timing = 0x90cf8521; break; 620 case ATA_UDMA4: timing = 0x90c98521; break; 621 default: timing = 0x01208585; 622 } 623 break; 624 default: 625 case 0xa7: /* 33MHz */ 626 switch (mode) { 627 case ATA_PIO0: timing = 0xc0d0a7aa; break; 628 case ATA_PIO1: timing = 0xc0d0a7a3; break; 629 case ATA_PIO2: timing = 0xc0d0a753; break; 630 case ATA_PIO3: timing = 0xc0c8a742; break; 631 case ATA_PIO4: timing = 0xc0c8a731; break; 632 case ATA_WDMA2: timing = 0xa0c8a731; break; 633 case ATA_UDMA2: timing = 0x90caa731; break; 634 case ATA_UDMA4: timing = 0x90c9a731; break; 635 default: timing = 0x0120a7a7; 636 } 637 break; 638 case 0xd9: /* 40Mhz */ 639 switch (mode) { 640 case ATA_PIO0: timing = 0xc018d9d9; break; 641 case ATA_PIO1: timing = 0xc010d9c7; break; 642 case ATA_PIO2: timing = 0xc010d997; break; 643 case ATA_PIO3: timing = 0xc010d974; break; 644 case ATA_PIO4: timing = 0xc008d963; break; 645 case ATA_WDMA2: timing = 0xa008d943; break; 646 case ATA_UDMA2: timing = 0x900bd943; break; 647 case ATA_UDMA4: timing = 0x900fd943; break; 648 default: timing = 0x0120d9d9; 649 } 650 } 651 pci_write_config(scp->dev, 0x40 + (devno << 2) , timing, 4); 652} 653 654#else /* NPCI > 0 */ 655 656int32_t 657ata_dmainit(struct ata_softc *scp, int32_t device, 658 int32_t piomode, int32_t wdmamode, int32_t udmamode) 659{ 660 return -1; 661} 662 663int32_t 664ata_dmasetup(struct ata_softc *scp, int32_t device, 665 int8_t *data, int32_t count, int32_t flags) 666{ 667 return -1; 668} 669 670void 671ata_dmastart(struct ata_softc *scp) 672{ 673} 674 675int32_t 676ata_dmadone(struct ata_softc *scp) 677{ 678 return -1; 679} 680 681int32_t 682ata_dmastatus(struct ata_softc *scp) 683{ 684 return -1; 685} 686 687#endif /* NPCI > 0 */ 688