ata-dma.c revision 108949
1/*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 108949 2003-01-08 16:51:41Z sos $ 29 */ 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/ata.h> 34#include <sys/endian.h> 35#include <sys/malloc.h> 36#include <sys/bus.h> 37#include <pci/pcivar.h> 38#include <machine/bus.h> 39#include <sys/rman.h> 40#include <dev/ata/ata-all.h> 41 42/* prototypes */ 43static void ata_dmacreate(struct ata_device *, int, int); 44static void ata_dmasetupd_cb(void *, bus_dma_segment_t *, int, int); 45static void ata_dmasetupc_cb(void *, bus_dma_segment_t *, int, int); 46static void cyrix_timing(struct ata_device *, int, int); 47static void promise_timing(struct ata_device *, int, int); 48static void hpt_timing(struct ata_device *, int, int); 49static int hpt_cable80(struct ata_device *); 50 51/* misc defines */ 52#define ATAPI_DEVICE(atadev) \ 53 ((atadev->unit == ATA_MASTER && \ 54 atadev->channel->devices & ATA_ATAPI_MASTER) || \ 55 (atadev->unit == ATA_SLAVE && \ 56 atadev->channel->devices & ATA_ATAPI_SLAVE)) 57 58#define MAXSEGSZ PAGE_SIZE 59#define MAXTABSZ PAGE_SIZE 60#define MAXCTLDMASZ (2 * (MAXTABSZ + MAXPHYS)) 61 62struct ata_dc_cb_args { 63 bus_addr_t maddr; 64 int error; 65}; 66 67static void 68ata_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 69{ 70 struct ata_dc_cb_args *cba = (struct ata_dc_cb_args *)xsc; 71 72 if (!(cba->error = error)) 73 cba->maddr = segs[0].ds_addr; 74} 75 76int 77ata_dmaalloc(struct ata_device *atadev) 78{ 79 struct ata_channel *ch; 80 struct ata_dc_cb_args ccba; 81 struct ata_dmastate *ds; 82 int error; 83 84 ch = atadev->channel; 85 ds = &atadev->dmastate; 86 if (!ds->cdmatag) { 87 if ((error = bus_dma_tag_create(ch->dmatag, 1, PAGE_SIZE, 88 BUS_SPACE_MAXADDR_32BIT, 89 BUS_SPACE_MAXADDR, NULL, NULL, 90 MAXTABSZ, 1, MAXTABSZ, 91 BUS_DMA_ALLOCNOW, &ds->cdmatag))) 92 return error; 93 } 94 if (!ds->ddmatag) { 95 if ((error = bus_dma_tag_create(ch->dmatag, ch->alignment + 1, 0, 96 BUS_SPACE_MAXADDR_32BIT, 97 BUS_SPACE_MAXADDR, NULL, NULL, 98 MAXPHYS, ATA_DMA_ENTRIES, MAXSEGSZ, 99 BUS_DMA_ALLOCNOW, &ds->ddmatag))) 100 return error; 101 } 102 if (!ds->mdmatab) { 103 if ((error = bus_dmamem_alloc(ds->cdmatag, (void **)&ds->dmatab, 0, 104 &ds->cdmamap))) 105 return error; 106 107 if ((error = bus_dmamap_load(ds->cdmatag, ds->cdmamap, ds->dmatab, 108 MAXTABSZ, ata_dmasetupc_cb, &ccba, 109 0)) != 0 || ccba.error != 0) { 110 bus_dmamem_free(ds->cdmatag, ds->dmatab, ds->cdmamap); 111 return error; 112 } 113 ds->mdmatab = ccba.maddr; 114 } 115 if (!ds->ddmamap) { 116 if ((error = bus_dmamap_create(ds->ddmatag, 0, &ds->ddmamap)) != 0) 117 return error; 118 } 119 return 0; 120} 121 122void 123ata_dmafree(struct ata_device *atadev) 124{ 125 struct ata_dmastate *ds; 126 127 ds = &atadev->dmastate; 128 if (ds->mdmatab) { 129 bus_dmamap_unload(ds->cdmatag, ds->cdmamap); 130 bus_dmamem_free(ds->cdmatag, ds->dmatab, ds->cdmamap); 131 ds->mdmatab = 0; 132 ds->cdmamap = NULL; 133 ds->dmatab = NULL; 134 } 135 if (ds->ddmamap) { 136 bus_dmamap_destroy(ds->ddmatag, ds->ddmamap); 137 ds->ddmamap = NULL; 138 } 139 if (ds->cdmatag) { 140 bus_dma_tag_destroy(ds->cdmatag); 141 ds->cdmatag = NULL; 142 } 143 if (ds->ddmatag) { 144 bus_dma_tag_destroy(ds->ddmatag); 145 ds->ddmatag = NULL; 146 } 147} 148 149void 150ata_dmafreetags(struct ata_channel *ch) 151{ 152 153 if (ch->dmatag) { 154 bus_dma_tag_destroy(ch->dmatag); 155 ch->dmatag = NULL; 156 } 157} 158 159static void 160ata_dmacreate(struct ata_device *atadev, int apiomode, int mode) 161{ 162 163 atadev->mode = mode; 164 if (!atadev->channel->dmatag) { 165 if (bus_dma_tag_create(NULL, 1, 0, 166 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 167 NULL, NULL, MAXCTLDMASZ, ATA_DMA_ENTRIES, 168 BUS_SPACE_MAXSIZE_32BIT, 0, 169 &atadev->channel->dmatag)) { 170 ata_prtdev(atadev, "DMA tag allocation failed, disabling DMA\n"); 171 ata_dmainit(atadev, apiomode, -1, -1); 172 } 173 } 174} 175 176void 177ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode) 178{ 179 device_t parent = device_get_parent(atadev->channel->dev); 180 int chiptype = atadev->channel->chiptype; 181 int chiprev = pci_get_revid(parent); 182 int channel = atadev->channel->unit; 183 int device = ATA_DEV(atadev->unit); 184 int devno = (channel << 1) + device; 185 int error; 186 187 /* set our most pessimistic default mode */ 188 atadev->mode = ATA_PIO; 189 190 if (!atadev->channel->r_bmio) 191 return; 192 193 /* if simplex controller, only allow DMA on primary channel */ 194 if (channel == 1) { 195 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT, 196 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 197 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 198 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 199 ATA_BMSTAT_DMA_SIMPLEX) { 200 ata_prtdev(atadev, "simplex device, DMA on primary only\n"); 201 return; 202 } 203 } 204 205 /* DMA engine address alignment is usually 1 word (2 bytes) */ 206 atadev->channel->alignment = 0x1; 207 208#if 1 209 if (udmamode > 2 && !atadev->param->hwres_cblid) { 210 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n"); 211 udmamode = 2; 212 } 213#endif 214 switch (chiptype) { 215 216 case 0x24cb8086: /* Intel ICH4 */ 217 case 0x248a8086: /* Intel ICH3 mobile */ 218 case 0x248b8086: /* Intel ICH3 */ 219 case 0x244a8086: /* Intel ICH2 mobile */ 220 case 0x244b8086: /* Intel ICH2 */ 221 if (udmamode >= 5) { 222 int32_t mask48, new48; 223 int16_t word54; 224 225 word54 = pci_read_config(parent, 0x54, 2); 226 if (word54 & (0x10 << devno)) { 227 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 228 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 229 if (bootverbose) 230 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n", 231 (error) ? "failed" : "success"); 232 if (!error) { 233 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 234 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 235 pci_write_config(parent, 0x48, 236 (pci_read_config(parent, 0x48, 4) & 237 ~mask48) | new48, 4); 238 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 239 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 240 return; 241 } 242 } 243 } 244 /* make sure eventual ATA100 mode from the BIOS is disabled */ 245 pci_write_config(parent, 0x54, 246 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 247 /* FALLTHROUGH */ 248 249 case 0x24118086: /* Intel ICH */ 250 case 0x76018086: /* Intel ICH */ 251 if (udmamode >= 4) { 252 int32_t mask48, new48; 253 int16_t word54; 254 255 word54 = pci_read_config(parent, 0x54, 2); 256 if (word54 & (0x10 << devno)) { 257 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 258 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 259 if (bootverbose) 260 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n", 261 (error) ? "failed" : "success"); 262 if (!error) { 263 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 264 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 265 pci_write_config(parent, 0x48, 266 (pci_read_config(parent, 0x48, 4) & 267 ~mask48) | new48, 4); 268 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 269 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 270 return; 271 } 272 } 273 } 274 /* make sure eventual ATA66 mode from the BIOS is disabled */ 275 pci_write_config(parent, 0x54, 276 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 277 /* FALLTHROUGH */ 278 279 case 0x71118086: /* Intel PIIX4 */ 280 case 0x84CA8086: /* Intel PIIX4 */ 281 case 0x71998086: /* Intel PIIX4e */ 282 case 0x24218086: /* Intel ICH0 */ 283 if (udmamode >= 2) { 284 int32_t mask48, new48; 285 286 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 287 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 288 if (bootverbose) 289 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n", 290 (error) ? "failed" : "success"); 291 if (!error) { 292 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 293 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 294 pci_write_config(parent, 0x48, 295 (pci_read_config(parent, 0x48, 4) & 296 ~mask48) | new48, 4); 297 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 298 return; 299 } 300 } 301 /* make sure eventual ATA33 mode from the BIOS is disabled */ 302 pci_write_config(parent, 0x48, 303 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 304 /* FALLTHROUGH */ 305 306 case 0x70108086: /* Intel PIIX3 */ 307 if (wdmamode >= 2 && apiomode >= 4) { 308 int32_t mask40, new40, mask44, new44; 309 310 /* if SITRE not set doit for both channels */ 311 if (!((pci_read_config(parent, 0x40, 4) >> (channel<<8)) & 0x4000)){ 312 new40 = pci_read_config(parent, 0x40, 4); 313 new44 = pci_read_config(parent, 0x44, 4); 314 if (!(new40 & 0x00004000)) { 315 new44 &= ~0x0000000f; 316 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 317 } 318 if (!(new40 & 0x40000000)) { 319 new44 &= ~0x000000f0; 320 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 321 } 322 new40 |= 0x40004000; 323 pci_write_config(parent, 0x40, new40, 4); 324 pci_write_config(parent, 0x44, new44, 4); 325 } 326 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 327 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 328 if (bootverbose) 329 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 330 (error) ? "failed" : "success"); 331 if (!error) { 332 if (device == ATA_MASTER) { 333 mask40 = 0x0000330f; 334 new40 = 0x00002307; 335 mask44 = 0; 336 new44 = 0; 337 } 338 else { 339 mask40 = 0x000000f0; 340 new40 = 0x00000070; 341 mask44 = 0x0000000f; 342 new44 = 0x0000000b; 343 } 344 if (channel) { 345 mask40 <<= 16; 346 new40 <<= 16; 347 mask44 <<= 4; 348 new44 <<= 4; 349 } 350 pci_write_config(parent, 0x40, 351 (pci_read_config(parent, 0x40, 4) & ~mask40)| 352 new40, 4); 353 pci_write_config(parent, 0x44, 354 (pci_read_config(parent, 0x44, 4) & ~mask44)| 355 new44, 4); 356 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 357 return; 358 } 359 } 360 /* we could set PIO mode timings, but we assume the BIOS did that */ 361 break; 362 363 case 0x12308086: /* Intel PIIX */ 364 if (wdmamode >= 2 && apiomode >= 4) { 365 int32_t word40; 366 367 word40 = pci_read_config(parent, 0x40, 4); 368 word40 >>= channel * 16; 369 370 /* Check for timing config usable for DMA on controller */ 371 if (!((word40 & 0x3300) == 0x2300 && 372 ((word40 >> (device ? 4 : 0)) & 1) == 1)) 373 break; 374 375 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 376 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 377 if (bootverbose) 378 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 379 (error) ? "failed" : "success"); 380 if (!error) { 381 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 382 return; 383 } 384 } 385 break; 386 387 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 388 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 389 if (chiprev < 0xc2 && 390 atadev->channel->devices & ATA_ATAPI_MASTER && 391 atadev->channel->devices & ATA_ATAPI_SLAVE) { 392 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n"); 393 break; 394 } 395 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4); 396 if (udmamode >= 5 && chiprev >= 0xc4) { 397 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 398 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 399 if (bootverbose) 400 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n", 401 (error) ? "failed" : "success"); 402 if (!error) { 403 int32_t word54 = pci_read_config(parent, 0x54, 4); 404 405 pci_write_config(parent, 0x4b, 406 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 407 word54 &= ~(0x000f000f << (devno << 2)); 408 word54 |= (0x000f0005 << (devno << 2)); 409 pci_write_config(parent, 0x54, word54, 4); 410 pci_write_config(parent, 0x53, 411 pci_read_config(parent, 0x53, 1) | 0x03, 1); 412 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 413 return; 414 } 415 } 416 if (udmamode >= 4 && chiprev >= 0xc2) { 417 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 418 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 419 if (bootverbose) 420 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n", 421 (error) ? "failed" : "success"); 422 if (!error) { 423 int32_t word54 = pci_read_config(parent, 0x54, 4); 424 425 pci_write_config(parent, 0x4b, 426 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 427 word54 &= ~(0x000f000f << (devno << 2)); 428 word54 |= (0x00080005 << (devno << 2)); 429 pci_write_config(parent, 0x54, word54, 4); 430 pci_write_config(parent, 0x53, 431 pci_read_config(parent, 0x53, 1) | 0x03, 1); 432 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 433 return; 434 } 435 } 436 if (udmamode >= 2 && chiprev >= 0x20) { 437 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 438 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 439 if (bootverbose) 440 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n", 441 (error) ? "failed" : "success"); 442 if (!error) { 443 int32_t word54 = pci_read_config(parent, 0x54, 4); 444 445 word54 &= ~(0x000f000f << (devno << 2)); 446 word54 |= (0x000a0005 << (devno << 2)); 447 pci_write_config(parent, 0x54, word54, 4); 448 pci_write_config(parent, 0x53, 449 pci_read_config(parent, 0x53, 1) | 0x03, 1); 450 atadev->channel->flags |= ATA_ATAPI_DMA_RO; 451 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 452 return; 453 } 454 } 455 456 /* make sure eventual UDMA mode from the BIOS is disabled */ 457 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 458 ~(0x0008 << (devno << 2)), 2); 459 460 if (wdmamode >= 2 && apiomode >= 4) { 461 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 462 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 463 if (bootverbose) 464 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n", 465 (error) ? "failed" : "success"); 466 if (!error) { 467 pci_write_config(parent, 0x53, 468 pci_read_config(parent, 0x53, 1) | 0x03, 1); 469 atadev->channel->flags |= ATA_ATAPI_DMA_RO; 470 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 471 return; 472 } 473 } 474 pci_write_config(parent, 0x53, 475 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 476 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 477 ATA_PIO0 + apiomode, 478 ATA_C_F_SETXFER, ATA_WAIT_READY); 479 if (bootverbose) 480 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n", 481 (error) ? "failed" : "success", 482 (apiomode >= 0) ? apiomode : 0); 483 if (!error) { 484 int32_t word54 = pci_read_config(parent, 0x54, 4); 485 int32_t timing; 486 487 switch(ATA_PIO0 + apiomode) { 488 case ATA_PIO0: timing = 0x006d0003; 489 case ATA_PIO1: timing = 0x00580002; 490 case ATA_PIO2: timing = 0x00440001; 491 case ATA_PIO3: timing = 0x00330001; 492 case ATA_PIO4: timing = 0x00310001; 493 default: timing = 0x006d0003; 494 } 495 pci_write_config(parent, 0x58 + (channel << 2), timing, 4); 496 word54 &= ~(0x000f000f << (devno << 2)); 497 word54 |= (0x00000004 << (devno << 2)); 498 pci_write_config(parent, 0x54, word54, 4); 499 atadev->mode = ATA_PIO0 + apiomode; 500 return; 501 } 502 break; 503 504 case 0x01bc10de: /* nVIDIA nForce */ 505 case 0x006510de: /* nVIDIA nForce2 */ 506 case 0x74411022: /* AMD 768 */ 507 case 0x74111022: /* AMD 766 */ 508 case 0x74091022: /* AMD 756 */ 509 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */ 510 { 511 int via_modes[5][7] = { 512 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 513 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 514 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 515 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 516 { 0x00, 0x00, 0xc0, 0x00, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */ 517 int reg = 0x53 - devno; 518 int *reg_val = NULL; 519 char *chip = "VIA"; 520 521 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */ 522 ata_find_dev(parent, 0x31771106, 0)) { /* 8235 */ 523 udmamode = imin(udmamode, 6); 524 reg_val = via_modes[3]; 525 } 526 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */ 527 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */ 528 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */ 529 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */ 530 udmamode = imin(udmamode, 5); 531 reg_val = via_modes[2]; 532 } 533 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */ 534 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 535 udmamode = imin(udmamode, 4); 536 reg_val = via_modes[1]; 537 } 538 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */ 539 udmamode = imin(udmamode, 2); 540 reg_val = via_modes[1]; 541 } 542 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 543 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 544 udmamode = imin(udmamode, 2); 545 reg_val = via_modes[0]; 546 } 547 else if (chiptype == 0x74411022 || /* AMD 768 */ 548 chiptype == 0x74111022) { /* AMD 766 */ 549 udmamode = imin(udmamode, 5); 550 reg_val = via_modes[4]; 551 chip = "AMD"; 552 } 553 else if (chiptype == 0x74091022) { /* AMD 756 */ 554 udmamode = imin(udmamode, 4); 555 reg_val = via_modes[4]; 556 chip = "AMD"; 557 } 558 else if (chiptype == 0x006510de) { /* nForce2 */ 559 udmamode = imin(udmamode, 6); 560 reg += 0x10; 561 reg_val = via_modes[4]; 562 chip = "nVidia"; 563 } 564 else if (chiptype == 0x01bc10de) { /* nForce */ 565 udmamode = imin(udmamode, 5); 566 reg += 0x10; 567 reg_val = via_modes[4]; 568 chip = "nVidia"; 569 } 570 else 571 udmamode = 0; 572 573 if (udmamode || wdmamode) 574 pci_write_config(parent, reg - 0x08, 0x20, 1); 575 576 if (udmamode >= 6) { 577 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 578 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 579 if (bootverbose) 580 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n", 581 (error) ? "failed" : "success", chip); 582 if (!error) { 583 pci_write_config(parent, reg, reg_val[6], 1); 584 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 585 return; 586 } 587 } 588 if (udmamode >= 5) { 589 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 590 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 591 if (bootverbose) 592 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n", 593 (error) ? "failed" : "success", chip); 594 if (!error) { 595 pci_write_config(parent, reg, reg_val[5], 1); 596 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 597 return; 598 } 599 } 600 if (udmamode >= 4) { 601 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 602 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 603 if (bootverbose) 604 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n", 605 (error) ? "failed" : "success", chip); 606 if (!error) { 607 pci_write_config(parent, reg, reg_val[4], 1); 608 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 609 return; 610 } 611 } 612 if (udmamode >= 2) { 613 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 614 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 615 if (bootverbose) 616 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n", 617 (error) ? "failed" : "success", chip); 618 if (!error) { 619 pci_write_config(parent, reg, reg_val[2], 1); 620 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 621 return; 622 } 623 } 624 if (wdmamode >= 2 && apiomode >= 4) { 625 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 626 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 627 if (bootverbose) 628 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n", 629 (error) ? "failed" : "success", chip); 630 if (!error) { 631 pci_write_config(parent, reg, 0x0b, 1); 632 pci_write_config(parent, reg - 0x08, 0x31, 1); 633 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 634 return; 635 } 636 } 637 } 638 /* we could set PIO mode timings, but we assume the BIOS did that */ 639 break; 640 641 case 0x55131039: /* SiS 5591 */ 642 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */ 643 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */ 644 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */ 645 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */ 646 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */ 647 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */ 648 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */ 649 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */ 650 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */ 651 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */ 652 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */ 653 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */ 654 int8_t reg = 0x40 + (devno << 1); 655 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 656 657 if (udmamode >= 5) { 658 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 659 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 660 if (bootverbose) 661 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n", 662 (error) ? "failed" : "success"); 663 if (!error) { 664 pci_write_config(parent, reg, val | 0x8000, 2); 665 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 666 return; 667 } 668 } 669 if (udmamode >= 4) { 670 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 671 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 672 if (bootverbose) 673 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 674 (error) ? "failed" : "success"); 675 if (!error) { 676 pci_write_config(parent, reg, val | 0x9000, 2); 677 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 678 return; 679 } 680 } 681 if (udmamode >= 2) { 682 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 683 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 684 if (bootverbose) 685 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 686 (error) ? "failed" : "success"); 687 if (!error) { 688 pci_write_config(parent, reg, val | 0xb000, 2); 689 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 690 return; 691 } 692 } 693 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */ 694 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */ 695 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */ 696 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */ 697 int8_t reg = 0x40 + (devno << 1); 698 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 699 700 if (udmamode >= 4) { 701 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 702 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 703 if (bootverbose) 704 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 705 (error) ? "failed" : "success"); 706 if (!error) { 707 pci_write_config(parent, reg, val | 0x9000, 2); 708 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 709 return; 710 } 711 } 712 if (udmamode >= 2) { 713 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 714 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 715 if (bootverbose) 716 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 717 (error) ? "failed" : "success"); 718 if (!error) { 719 pci_write_config(parent, reg, val | 0xa000, 2); 720 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 721 return; 722 } 723 } 724 } else if (udmamode >= 2 && chiprev > 0xc1) { 725 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 726 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 727 if (bootverbose) 728 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 729 (error) ? "failed" : "success"); 730 if (!error) { 731 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 732 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 733 return; 734 } 735 } 736 if (wdmamode >=2 && apiomode >= 4) { 737 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 738 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 739 if (bootverbose) 740 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n", 741 (error) ? "failed" : "success"); 742 if (!error) { 743 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 744 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 745 return; 746 } 747 } 748 /* we could set PIO mode timings, but we assume the BIOS did that */ 749 break; 750 751 case 0x06801095: /* Sil 0680 ATA133 controller */ 752 { 753 u_int8_t ureg = 0xac + (device * 0x02) + (channel * 0x10); 754 u_int8_t uval = pci_read_config(parent, ureg, 1); 755 u_int8_t mreg = channel ? 0x84 : 0x80; 756 u_int8_t mask = device ? 0x30 : 0x03; 757 u_int8_t mode = pci_read_config(parent, mreg, 1); 758 759 /* enable UDMA mode */ 760 pci_write_config(parent, mreg, 761 (mode & ~mask) | (device ? 0x30 : 0x03), 1); 762 if (udmamode >= 6) { 763 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 764 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 765 if (bootverbose) 766 ata_prtdev(atadev, "%s setting UDMA6 on Sil chip\n", 767 (error) ? "failed" : "success"); 768 if (!error) { 769 pci_write_config(parent, ureg, (uval & 0x3f) | 0x01, 1); 770 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 771 return; 772 } 773 } 774 if (udmamode >= 5) { 775 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 776 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 777 if (bootverbose) 778 ata_prtdev(atadev, "%s setting UDMA5 on Sil chip\n", 779 (error) ? "failed" : "success"); 780 if (!error) { 781 pci_write_config(parent, ureg, (uval & 0x3f) | 0x02, 1); 782 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 783 return; 784 } 785 } 786 if (udmamode >= 4) { 787 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 788 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 789 if (bootverbose) 790 ata_prtdev(atadev, "%s setting UDMA4 on Sil chip\n", 791 (error) ? "failed" : "success"); 792 if (!error) { 793 pci_write_config(parent, ureg, (uval & 0x3f) | 0x03, 1); 794 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 795 return; 796 } 797 } 798 if (udmamode >= 2) { 799 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 800 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 801 if (bootverbose) 802 ata_prtdev(atadev, "%s setting UDMA2 on Sil chip\n", 803 (error) ? "failed" : "success"); 804 if (!error) { 805 pci_write_config(parent, ureg, (uval & 0x3f) | 0x07, 1); 806 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 807 return; 808 } 809 } 810 811 /* disable UDMA mode and enable WDMA mode */ 812 pci_write_config(parent, mreg, 813 (mode & ~mask) | (device ? 0x20 : 0x02), 1); 814 if (wdmamode >= 2 && apiomode >= 4) { 815 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 816 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 817 if (bootverbose) 818 ata_prtdev(atadev, "%s setting WDMA2 on Sil chip\n", 819 (error) ? "failed" : "success"); 820 if (!error) { 821 pci_write_config(parent, ureg - 0x4, 0x10c1, 2); 822 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 823 return; 824 } 825 } 826 827 /* restore PIO mode */ 828 pci_write_config(parent, mreg, mode, 1); 829 } 830 /* we could set PIO mode timings, but we assume the BIOS did that */ 831 break; 832 833 case 0x06491095: /* CMD 649 ATA100 controller */ 834 if (udmamode >= 5) { 835 u_int8_t umode; 836 837 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 838 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 839 if (bootverbose) 840 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n", 841 (error) ? "failed" : "success"); 842 if (!error) { 843 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 844 umode &= ~(device ? 0xca : 0x35); 845 umode |= (device ? 0x0a : 0x05); 846 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 847 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 848 return; 849 } 850 } 851 /* FALLTHROUGH */ 852 853 case 0x06481095: /* CMD 648 ATA66 controller */ 854 if (udmamode >= 4) { 855 u_int8_t umode; 856 857 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 858 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 859 if (bootverbose) 860 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n", 861 (error) ? "failed" : "success"); 862 if (!error) { 863 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 864 umode &= ~(device ? 0xca : 0x35); 865 umode |= (device ? 0x4a : 0x15); 866 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 867 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 868 return; 869 } 870 } 871 if (udmamode >= 2) { 872 u_int8_t umode; 873 874 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 875 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 876 if (bootverbose) 877 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n", 878 (error) ? "failed" : "success"); 879 if (!error) { 880 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 881 umode &= ~(device ? 0xca : 0x35); 882 umode |= (device ? 0x42 : 0x11); 883 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 884 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 885 return; 886 } 887 } 888 /* make sure eventual UDMA mode from the BIOS is disabled */ 889 pci_write_config(parent, channel ? 0x7b : 0x73, 890 pci_read_config(parent, channel ? 0x7b : 0x73, 1) & 891 ~(device ? 0xca : 0x53), 1); 892 /* FALLTHROUGH */ 893 894 case 0x06461095: /* CMD 646 ATA controller */ 895 if (wdmamode >= 2 && apiomode >= 4) { 896 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 897 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 898 if (bootverbose) 899 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n", 900 error ? "failed" : "success"); 901 if (!error) { 902 int32_t offset = (devno < 3) ? (devno << 1) : 7; 903 904 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 905 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 906 return; 907 } 908 } 909 /* we could set PIO mode timings, but we assume the BIOS did that */ 910 break; 911 912 case 0xc6931080: /* Cypress 82c693 ATA controller */ 913 if (wdmamode >= 2 && apiomode >= 4) { 914 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 915 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 916 if (bootverbose) 917 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n", 918 error ? "failed" : "success"); 919 if (!error) { 920 pci_write_config(atadev->channel->dev, 921 channel ? 0x4e:0x4c, 0x2020, 2); 922 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 923 return; 924 } 925 } 926 /* we could set PIO mode timings, but we assume the BIOS did that */ 927 break; 928 929 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 930 atadev->channel->alignment = 0xf; 931 if (udmamode >= 2) { 932 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 933 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 934 if (bootverbose) 935 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n", 936 (error) ? "failed" : "success"); 937 if (!error) { 938 cyrix_timing(atadev, devno, ATA_UDMA2); 939 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 940 return; 941 } 942 } 943 if (wdmamode >= 2 && apiomode >= 4) { 944 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 945 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 946 if (bootverbose) 947 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n", 948 (error) ? "failed" : "success"); 949 if (!error) { 950 cyrix_timing(atadev, devno, ATA_WDMA2); 951 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 952 return; 953 } 954 } 955 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 956 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 957 ATA_WAIT_READY); 958 if (bootverbose) 959 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n", 960 (error) ? "failed" : "success", 961 ata_mode2str(ATA_PIO0 + apiomode)); 962 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode); 963 atadev->mode = ATA_PIO0 + apiomode; 964 return; 965 966 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */ 967 if (udmamode >= 5 && chiprev >= 0x92) { 968 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 969 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 970 if (bootverbose) 971 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n", 972 (error) ? "failed" : "success"); 973 if (!error) { 974 u_int16_t reg56; 975 976 pci_write_config(parent, 0x54, 977 pci_read_config(parent, 0x54, 1) | 978 (0x01 << devno), 1); 979 reg56 = pci_read_config(parent, 0x56, 2); 980 reg56 &= ~(0xf << (devno * 4)); 981 reg56 |= (0x5 << (devno * 4)); 982 pci_write_config(parent, 0x56, reg56, 2); 983 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 984 return; 985 } 986 } 987 if (udmamode >= 4) { 988 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 989 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 990 if (bootverbose) 991 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n", 992 (error) ? "failed" : "success"); 993 if (!error) { 994 u_int16_t reg56; 995 996 pci_write_config(parent, 0x54, 997 pci_read_config(parent, 0x54, 1) | 998 (0x01 << devno), 1); 999 reg56 = pci_read_config(parent, 0x56, 2); 1000 reg56 &= ~(0xf << (devno * 4)); 1001 reg56 |= (0x4 << (devno * 4)); 1002 pci_write_config(parent, 0x56, reg56, 2); 1003 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1004 return; 1005 } 1006 } 1007 /* FALLTHROUGH */ 1008 1009 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 1010 if (udmamode >= 2) { 1011 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1012 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1013 if (bootverbose) 1014 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n", 1015 (error) ? "failed" : "success"); 1016 if (!error) { 1017 u_int16_t reg56; 1018 1019 pci_write_config(parent, 0x54, 1020 pci_read_config(parent, 0x54, 1) | 1021 (0x01 << devno), 1); 1022 reg56 = pci_read_config(parent, 0x56, 2); 1023 reg56 &= ~(0xf << (devno * 4)); 1024 reg56 |= (0x2 << (devno * 4)); 1025 pci_write_config(parent, 0x56, reg56, 2); 1026 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1027 return; 1028 } 1029 } 1030 if (wdmamode >= 2 && apiomode >= 4) { 1031 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1032 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1033 if (bootverbose) 1034 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n", 1035 (error) ? "failed" : "success"); 1036 if (!error) { 1037 int offset = devno ^ 0x01; 1038 int word44 = pci_read_config(parent, 0x44, 4); 1039 1040 pci_write_config(parent, 0x54, 1041 pci_read_config(parent, 0x54, 1) & 1042 ~(0x01 << devno), 1); 1043 word44 &= ~(0xff << (offset << 8)); 1044 word44 |= (0x20 << (offset << 8)); 1045 pci_write_config(parent, 0x44, 0x20, 4); 1046 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1047 return; 1048 } 1049 } 1050 /* we could set PIO mode timings, but we assume the BIOS did that */ 1051 break; 1052 1053 case 0x4d69105a: /* Promise TX2 ATA133 controllers */ 1054 case 0x5275105a: /* Promise TX2 ATA133 controllers */ 1055 case 0x6269105a: /* Promise TX2 ATA133 controllers */ 1056 case 0x7275105a: /* Promise TX2 ATA133 controllers */ 1057 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 1058 if (udmamode >= 6 && 1059 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 1060 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1061 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 1062 if (bootverbose) 1063 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n", 1064 (error) ? "failed" : "success"); 1065 if (!error) { 1066 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 1067 return; 1068 } 1069 } 1070 /* FALLTHROUGH */ 1071 1072 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 1073 case 0x6268105a: /* Promise TX2 ATA100 controllers */ 1074 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 1075 if (udmamode >= 5 && 1076 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 1077 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1078 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1079 if (bootverbose) 1080 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 1081 (error) ? "failed" : "success"); 1082 if (!error) { 1083 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1084 return; 1085 } 1086 } 1087 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 1088 if (udmamode >= 4 && 1089 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 1090 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1091 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1092 if (bootverbose) 1093 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 1094 (error) ? "failed" : "success"); 1095 if (!error) { 1096 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1097 return; 1098 } 1099 } 1100 if (udmamode >= 2) { 1101 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1102 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1103 if (bootverbose) 1104 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n", 1105 (error) ? "failed" : "success"); 1106 if (!error) { 1107 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1108 return; 1109 } 1110 } 1111 if (wdmamode >= 2 && apiomode >= 4) { 1112 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1113 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1114 if (bootverbose) 1115 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 1116 (error) ? "failed" : "success"); 1117 if (!error) { 1118 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1119 return; 1120 } 1121 } 1122 break; 1123 1124 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 1125 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 1126 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && 1127 !(pci_read_config(parent, 0x50, 2) & (channel ? 1<<11 : 1<<10))) { 1128 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1129 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1130 if (bootverbose) 1131 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 1132 (error) ? "failed" : "success"); 1133 if (!error) { 1134 promise_timing(atadev, devno, ATA_UDMA5); 1135 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1136 return; 1137 } 1138 } 1139 /* FALLTHROUGH */ 1140 1141 case 0x0d38105a: /* Promise FastTrak 66 controllers */ 1142 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 1143 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && 1144 !(pci_read_config(parent, 0x50, 2) & (channel ? 1<<11 : 1<<10))) { 1145 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1146 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1147 if (bootverbose) 1148 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 1149 (error) ? "failed" : "success"); 1150 if (!error) { 1151 promise_timing(atadev, devno, ATA_UDMA4); 1152 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1153 return; 1154 } 1155 } 1156 /* FALLTHROUGH */ 1157 1158 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 1159 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) { 1160 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1161 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1162 if (bootverbose) 1163 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n", 1164 (error) ? "failed" : "success"); 1165 if (!error) { 1166 promise_timing(atadev, devno, ATA_UDMA2); 1167 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1168 return; 1169 } 1170 } 1171 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) { 1172 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1173 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1174 if (bootverbose) 1175 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 1176 (error) ? "failed" : "success"); 1177 if (!error) { 1178 promise_timing(atadev, devno, ATA_WDMA2); 1179 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1180 return; 1181 } 1182 } 1183 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1184 ATA_PIO0 + apiomode, 1185 ATA_C_F_SETXFER, ATA_WAIT_READY); 1186 if (bootverbose) 1187 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n", 1188 (error) ? "failed" : "success", 1189 (apiomode >= 0) ? apiomode : 0); 1190 promise_timing(atadev, devno, ATA_PIO0 + apiomode); 1191 atadev->mode = ATA_PIO0 + apiomode; 1192 return; 1193 1194 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 1195 case 0x00051103: /* HighPoint HPT372 controllers */ 1196 case 0x00081103: /* HighPoint HPT374 controllers */ 1197 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) && 1198 ((chiptype == 0x00041103 && chiprev >= 0x05) || 1199 (chiptype == 0x00051103 && chiprev >= 0x01) || 1200 (chiptype == 0x00081103 && chiprev >= 0x07))) { 1201 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1202 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 1203 if (bootverbose) 1204 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n", 1205 (error) ? "failed" : "success"); 1206 if (!error) { 1207 hpt_timing(atadev, devno, ATA_UDMA6); 1208 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 1209 return; 1210 } 1211 } 1212 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) && 1213 ((chiptype == 0x00041103 && chiprev >= 0x03) || 1214 (chiptype == 0x00051103 && chiprev >= 0x01) || 1215 (chiptype == 0x00081103 && chiprev >= 0x07))) { 1216 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1217 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1218 if (bootverbose) 1219 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n", 1220 (error) ? "failed" : "success"); 1221 if (!error) { 1222 hpt_timing(atadev, devno, ATA_UDMA5); 1223 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1224 return; 1225 } 1226 } 1227 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) { 1228 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1229 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1230 if (bootverbose) 1231 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n", 1232 (error) ? "failed" : "success"); 1233 if (!error) { 1234 hpt_timing(atadev, devno, ATA_UDMA4); 1235 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1236 return; 1237 } 1238 } 1239 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) { 1240 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1241 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1242 if (bootverbose) 1243 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n", 1244 (error) ? "failed" : "success"); 1245 if (!error) { 1246 hpt_timing(atadev, devno, ATA_UDMA2); 1247 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1248 return; 1249 } 1250 } 1251 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) { 1252 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1253 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1254 if (bootverbose) 1255 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n", 1256 (error) ? "failed" : "success"); 1257 if (!error) { 1258 hpt_timing(atadev, devno, ATA_WDMA2); 1259 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1260 return; 1261 } 1262 } 1263 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1264 ATA_PIO0 + apiomode, 1265 ATA_C_F_SETXFER, ATA_WAIT_READY); 1266 if (bootverbose) 1267 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n", 1268 (error) ? "failed" : "success", 1269 (apiomode >= 0) ? apiomode : 0); 1270 hpt_timing(atadev, devno, ATA_PIO0 + apiomode); 1271 atadev->mode = ATA_PIO0 + apiomode; 1272 return; 1273 1274 case 0x00091191: /* Acard ATP865R controller */ 1275 case 0x00081191: /* Acard ATP865 controller */ 1276 if (ATAPI_DEVICE(atadev)) 1277 break; 1278 if (udmamode >= 6) { 1279 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1280 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 1281 if (bootverbose) 1282 ata_prtdev(atadev, "%s setting up UDMA6 mode on Acard chip\n", 1283 (error) ? "failed" : "success"); 1284 if (!error) { 1285 u_int16_t reg44 = pci_read_config(parent, 0x44, 2); 1286 1287 reg44 &= ~(0x000f << (devno << 2)); 1288 reg44 |= (0x0007 << (devno << 2)); 1289 pci_write_config(parent, 0x44, reg44, 2); 1290 pci_write_config(parent, 0x4a, 0xa6, 1); 1291 pci_write_config(parent, 0x40 + devno, 0x031, 1); 1292 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 1293 return; 1294 } 1295 } 1296 if (udmamode >= 5) { 1297 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1298 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1299 if (bootverbose) 1300 ata_prtdev(atadev, "%s setting up UDMA5 mode on Acard chip\n", 1301 (error) ? "failed" : "success"); 1302 if (!error) { 1303 u_int16_t reg44 = pci_read_config(parent, 0x44, 2); 1304 1305 reg44 &= ~(0x000f << (devno << 2)); 1306 reg44 |= (0x0006 << (devno << 2)); 1307 pci_write_config(parent, 0x44, reg44, 2); 1308 pci_write_config(parent, 0x4a, 0xa6, 1); 1309 pci_write_config(parent, 0x40 + devno, 0x031, 1); 1310 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1311 return; 1312 } 1313 } 1314 /* FALLTHROUGH */ 1315 1316 case 0x00071191: /* Acard ATP860R controller */ 1317 case 0x00061191: /* Acard ATP860 controller */ 1318 if (ATAPI_DEVICE(atadev)) 1319 break; 1320 if (udmamode >= 4) { 1321 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1322 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1323 if (bootverbose) 1324 ata_prtdev(atadev, "%s setting up UDMA4 mode on Acard chip\n", 1325 (error) ? "failed" : "success"); 1326 if (!error) { 1327 u_int16_t reg44 = pci_read_config(parent, 0x44, 2); 1328 1329 reg44 &= ~(0x000f << (devno << 2)); 1330 reg44 |= (0x0005 << (devno << 2)); 1331 pci_write_config(parent, 0x44, reg44, 2); 1332 pci_write_config(parent, 0x4a, 0xa6, 1); 1333 pci_write_config(parent, 0x40 + devno, 0x031, 1); 1334 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1335 return; 1336 } 1337 } 1338 if (udmamode >= 2) { 1339 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1340 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1341 if (bootverbose) 1342 ata_prtdev(atadev, "%s setting up UDMA2 mode on Acard chip\n", 1343 (error) ? "failed" : "success"); 1344 if (!error) { 1345 u_int16_t reg44 = pci_read_config(parent, 0x44, 2); 1346 1347 reg44 &= ~(0x000f << (devno << 2)); 1348 reg44 |= (0x0003 << (devno << 2)); 1349 pci_write_config(parent, 0x44, reg44, 2); 1350 pci_write_config(parent, 0x4a, 0xa6, 1); 1351 pci_write_config(parent, 0x40 + devno, 0x031, 1); 1352 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1353 return; 1354 } 1355 } 1356 if (wdmamode >= 2 && apiomode >= 4) { 1357 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1358 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1359 if (bootverbose) 1360 ata_prtdev(atadev, "%s setting up WDMA2 mode on Acard chip\n", 1361 (error) ? "failed" : "success"); 1362 if (!error) { 1363 u_int16_t reg44 = pci_read_config(parent, 0x44, 2); 1364 1365 reg44 &= ~(0x000f << (devno << 2)); 1366 pci_write_config(parent, 0x44, reg44, 2); 1367 pci_write_config(parent, 0x4a, 0xa6, 1); 1368 pci_write_config(parent, 0x40 + devno, 0x031, 1); 1369 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1370 return; 1371 } 1372 } 1373 /* we could set PIO mode timings, but we assume the BIOS did that */ 1374 break; 1375 1376 case 0x00051191: /* Acard ATP850UF controller */ 1377 if (ATAPI_DEVICE(atadev)) 1378 break; 1379 if (udmamode >= 2) { 1380 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1381 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1382 if (bootverbose) 1383 ata_prtdev(atadev, "%s setting up UDMA2 mode on Acard chip\n", 1384 (error) ? "failed" : "success"); 1385 if (!error) { 1386 u_int8_t reg54 = pci_read_config(parent, 0x54, 1); 1387 1388 reg54 |= (0x03 << (devno << 1)); 1389 pci_write_config(parent, 0x54, reg54, 1); 1390 pci_write_config(parent, 0x4a, 0xa6, 1); 1391 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 1392 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1393 return; 1394 } 1395 } 1396 if (wdmamode >= 2 && apiomode >= 4) { 1397 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1398 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1399 if (bootverbose) 1400 ata_prtdev(atadev, "%s setting up WDMA2 mode on Acard chip\n", 1401 (error) ? "failed" : "success"); 1402 if (!error) { 1403 u_int8_t reg54 = pci_read_config(parent, 0x54, 1); 1404 1405 reg54 &= ~(0x03 << (devno << 1)); 1406 pci_write_config(parent, 0x54, reg54, 1); 1407 pci_write_config(parent, 0x4a, 0xa6, 1); 1408 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 1409 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1410 return; 1411 } 1412 } 1413 /* we could set PIO mode timings, but we assume the BIOS did that */ 1414 break; 1415 1416 case 0x000116ca: /* Cenatek Rocket Drive controller */ 1417 if (wdmamode >= 0 && 1418 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 1419 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) 1420 ata_dmacreate(atadev, apiomode, ATA_DMA); 1421 else 1422 atadev->mode = ATA_PIO; 1423 return; 1424 1425 default: /* unknown controller chip */ 1426 /* better not try generic DMA on ATAPI devices it almost never works */ 1427 if (ATAPI_DEVICE(atadev)) 1428 break; 1429 1430 /* if controller says its setup for DMA take the easy way out */ 1431 /* the downside is we dont know what DMA mode we are in */ 1432 if ((udmamode >= 0 || wdmamode >= 2) && 1433 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 1434 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) { 1435 ata_dmacreate(atadev, apiomode, ATA_DMA); 1436 return; 1437 } 1438 1439 /* well, we have no support for this, but try anyways */ 1440 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) { 1441 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1442 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1443 if (bootverbose) 1444 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n", 1445 (error) ? "failed" : "success"); 1446 if (!error) { 1447 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1448 return; 1449 } 1450 } 1451 } 1452 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 1453 ATA_C_F_SETXFER, ATA_WAIT_READY); 1454 if (bootverbose) 1455 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n", 1456 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 1457 if (!error) 1458 atadev->mode = ATA_PIO0 + apiomode; 1459 else { 1460 if (bootverbose) 1461 ata_prtdev(atadev, "using PIO mode set by BIOS\n"); 1462 atadev->mode = ATA_PIO; 1463 } 1464} 1465 1466struct ata_dmasetup_data_cb_args { 1467 struct ata_dmaentry *dmatab; 1468 int error; 1469}; 1470 1471static void 1472ata_dmasetupd_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1473{ 1474 struct ata_dmasetup_data_cb_args *cba = 1475 (struct ata_dmasetup_data_cb_args *)xsc; 1476 bus_size_t cnt; 1477 u_int32_t lastcount; 1478 int i, j; 1479 1480 cba->error = error; 1481 if (error != 0) 1482 return; 1483 lastcount = j = 0; 1484 for (i = 0; i < nsegs; i++) { 1485 /* 1486 * A maximum segment size was specified for bus_dma_tag_create, but 1487 * some busdma code does not seem to honor this, so fix up if needed. 1488 */ 1489 for (cnt = 0; cnt < segs[i].ds_len; cnt += MAXSEGSZ, j++) { 1490 cba->dmatab[j].base = htole32(segs[i].ds_addr + cnt); 1491 lastcount = ulmin(segs[i].ds_len - cnt, MAXSEGSZ) & 0xffff; 1492 cba->dmatab[j].count = htole32(lastcount); 1493 } 1494 } 1495 cba->dmatab[j - 1].count = htole32(lastcount | ATA_DMA_EOT); 1496} 1497 1498int 1499ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count) 1500{ 1501 struct ata_channel *ch = atadev->channel; 1502 1503 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) { 1504 ata_prtdev(atadev, "non aligned DMA transfer attempted\n"); 1505 return -1; 1506 } 1507 1508 if (!count) { 1509 ata_prtdev(atadev, "zero length DMA transfer attempted\n"); 1510 return -1; 1511 } 1512 return 0; 1513} 1514 1515int 1516ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir) 1517{ 1518 struct ata_channel *ch = atadev->channel; 1519 struct ata_dmastate *ds = &atadev->dmastate; 1520 struct ata_dmasetup_data_cb_args cba; 1521 1522 if (ds->flags & ATA_DS_ACTIVE) 1523 panic("ata_dmasetup: transfer active on this device!"); 1524 1525 switch(ch->chiptype) { 1526 case 0x0d38105a: /* Promise Fasttrak 66 */ 1527 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1528 case 0x0d30105a: /* Promise OEM ATA 100 */ 1529 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1530 ATA_OUTB(ch->r_bmio, 0x11, 1531 ATA_INB(ch->r_bmio, 0x11) | (atadev->unit ? 0x08 : 0x02)); 1532 1533 ATA_OUTL(ch->r_bmio, (atadev->unit ? 0x24 : 0x20), 1534 (dir ? 0x05000000 : 0x06000000) | (count >> 1)); 1535 break; 1536 } 1537 1538 cba.dmatab = ds->dmatab; 1539 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_PREWRITE); 1540 if (bus_dmamap_load(ds->ddmatag, ds->ddmamap, data, count, 1541 ata_dmasetupd_cb, &cba, 0) || cba.error) 1542 return -1; 1543 1544 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_POSTWRITE); 1545 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, dir ? BUS_DMASYNC_PREREAD : 1546 BUS_DMASYNC_PREWRITE); 1547 1548 ch->flags |= ATA_DMA_ACTIVE; 1549 ds->flags = dir ? (ATA_DS_ACTIVE | ATA_DS_READ) : ATA_DS_ACTIVE; 1550 1551 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, ds->mdmatab); 1552 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1553 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1554 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) | 1555 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1556 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1557 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1558 return 0; 1559} 1560 1561int 1562ata_dmadone(struct ata_device *atadev) 1563{ 1564 struct ata_channel *ch = atadev->channel; 1565 struct ata_dmastate *ds = &atadev->dmastate; 1566 int error; 1567 1568 switch(ch->chiptype) { 1569 case 0x0d38105a: /* Promise Fasttrak 66 */ 1570 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1571 case 0x0d30105a: /* Promise OEM ATA 100 */ 1572 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1573 ATA_OUTL(ch->r_bmio, (atadev->unit ? 0x24 : 0x20), 0); 1574 ATA_OUTB(ch->r_bmio, 0x11, 1575 ATA_INB(ch->r_bmio, 0x11) & ~(atadev->unit ? 0x08 : 0x02)); 1576 break; 1577 } 1578 1579 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, (ds->flags & ATA_DS_READ) != 0 ? 1580 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1581 bus_dmamap_unload(ds->ddmatag, ds->ddmamap); 1582 1583 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1584 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1585 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT); 1586 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1587 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1588 ch->flags &= ~ATA_DMA_ACTIVE; 1589 ds->flags = 0; 1590 return (error & ATA_BMSTAT_MASK); 1591} 1592 1593int 1594ata_dmastatus(struct ata_channel *ch) 1595{ 1596 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1597} 1598 1599static void 1600cyrix_timing(struct ata_device *atadev, int devno, int mode) 1601{ 1602 u_int32_t reg20 = 0x0000e132; 1603 u_int32_t reg24 = 0x00017771; 1604 1605 switch (mode) { 1606 case ATA_PIO0: reg20 = 0x0000e132; break; 1607 case ATA_PIO1: reg20 = 0x00018121; break; 1608 case ATA_PIO2: reg20 = 0x00024020; break; 1609 case ATA_PIO3: reg20 = 0x00032010; break; 1610 case ATA_PIO4: reg20 = 0x00040010; break; 1611 case ATA_WDMA2: reg24 = 0x00002020; break; 1612 case ATA_UDMA2: reg24 = 0x00911030; break; 1613 } 1614 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20); 1615 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24); 1616} 1617 1618static void 1619promise_timing(struct ata_device *atadev, int devno, int mode) 1620{ 1621 u_int32_t timing = 0; 1622 /* XXX: Endianess */ 1623 struct promise_timing { 1624 u_int8_t pa:4; 1625 u_int8_t prefetch:1; 1626 u_int8_t iordy:1; 1627 u_int8_t errdy:1; 1628 u_int8_t syncin:1; 1629 u_int8_t pb:5; 1630 u_int8_t mb:3; 1631 u_int8_t mc:4; 1632 u_int8_t dmaw:1; 1633 u_int8_t dmar:1; 1634 u_int8_t iordyp:1; 1635 u_int8_t dmarqp:1; 1636 u_int8_t reserved:8; 1637 } *t = (struct promise_timing*)&timing; 1638 1639 t->iordy = 1; t->iordyp = 1; 1640 if (mode >= ATA_DMA) { 1641 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1642 } 1643 1644 switch (atadev->channel->chiptype) { 1645 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1646 switch (mode) { 1647 default: 1648 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1649 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1650 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1651 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1652 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1653 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1654 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1655 } 1656 break; 1657 1658 case 0x0d38105a: /* Promise Fasttrak 66 */ 1659 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1660 case 0x0d30105a: /* Promise OEM ATA 100 */ 1661 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1662 switch (mode) { 1663 default: 1664 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1665 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1666 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1667 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1668 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1669 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1670 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1671 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1672 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1673 } 1674 break; 1675 } 1676 pci_write_config(device_get_parent(atadev->channel->dev), 1677 0x60 + (devno << 2), timing, 4); 1678} 1679 1680static void 1681hpt_timing(struct ata_device *atadev, int devno, int mode) 1682{ 1683 device_t parent = device_get_parent(atadev->channel->dev); 1684 u_int32_t chiptype = atadev->channel->chiptype; 1685 int chiprev = pci_get_revid(parent); 1686 u_int32_t timing; 1687 1688 if (chiptype == 0x00081103 && chiprev >= 0x07) { 1689 switch (mode) { /* HPT374 */ 1690 case ATA_PIO0: timing = 0x0ac1f48a; break; 1691 case ATA_PIO1: timing = 0x0ac1f465; break; 1692 case ATA_PIO2: timing = 0x0a81f454; break; 1693 case ATA_PIO3: timing = 0x0a81f443; break; 1694 case ATA_PIO4: timing = 0x0a81f442; break; 1695 case ATA_WDMA2: timing = 0x22808242; break; 1696 case ATA_UDMA2: timing = 0x120c8242; break; 1697 case ATA_UDMA4: timing = 0x12ac8242; break; 1698 case ATA_UDMA5: timing = 0x12848242; break; 1699 case ATA_UDMA6: timing = 0x12808242; break; 1700 default: timing = 0x0d029d5e; 1701 } 1702 } 1703 else if ((chiptype == 0x00041103 && chiprev >= 0x05) || 1704 (chiptype == 0x00051103 && chiprev >= 0x01)) { 1705 switch (mode) { /* HPT372 */ 1706 case ATA_PIO0: timing = 0x0d029d5e; break; 1707 case ATA_PIO1: timing = 0x0d029d26; break; 1708 case ATA_PIO2: timing = 0x0c829ca6; break; 1709 case ATA_PIO3: timing = 0x0c829c84; break; 1710 case ATA_PIO4: timing = 0x0c829c62; break; 1711 case ATA_WDMA2: timing = 0x2c829262; break; 1712 case ATA_UDMA2: timing = 0x1c91dc62; break; 1713 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1714 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1715 case ATA_UDMA6: timing = 0x1c81dc62; break; 1716 default: timing = 0x0d029d5e; 1717 } 1718 } 1719 else if (chiptype == 0x00041103 && chiprev >= 0x03) { 1720 switch (mode) { /* HPT370 */ 1721 case ATA_PIO0: timing = 0x06914e57; break; 1722 case ATA_PIO1: timing = 0x06914e43; break; 1723 case ATA_PIO2: timing = 0x06514e33; break; 1724 case ATA_PIO3: timing = 0x06514e22; break; 1725 case ATA_PIO4: timing = 0x06514e21; break; 1726 case ATA_WDMA2: timing = 0x26514e21; break; 1727 case ATA_UDMA2: timing = 0x16494e31; break; 1728 case ATA_UDMA4: timing = 0x16454e31; break; 1729 case ATA_UDMA5: timing = 0x16454e31; break; 1730 default: timing = 0x06514e57; 1731 } 1732 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1733 } 1734 else { /* HPT36[68] */ 1735 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1736 case 0x85: /* 25Mhz */ 1737 switch (mode) { 1738 case ATA_PIO0: timing = 0x40d08585; break; 1739 case ATA_PIO1: timing = 0x40d08572; break; 1740 case ATA_PIO2: timing = 0x40ca8542; break; 1741 case ATA_PIO3: timing = 0x40ca8532; break; 1742 case ATA_PIO4: timing = 0x40ca8521; break; 1743 case ATA_WDMA2: timing = 0x20ca8521; break; 1744 case ATA_UDMA2: timing = 0x10cf8521; break; 1745 case ATA_UDMA4: timing = 0x10c98521; break; 1746 default: timing = 0x01208585; 1747 } 1748 break; 1749 default: 1750 case 0xa7: /* 33MHz */ 1751 switch (mode) { 1752 case ATA_PIO0: timing = 0x40d0a7aa; break; 1753 case ATA_PIO1: timing = 0x40d0a7a3; break; 1754 case ATA_PIO2: timing = 0x40d0a753; break; 1755 case ATA_PIO3: timing = 0x40c8a742; break; 1756 case ATA_PIO4: timing = 0x40c8a731; break; 1757 case ATA_WDMA2: timing = 0x20c8a731; break; 1758 case ATA_UDMA2: timing = 0x10caa731; break; 1759 case ATA_UDMA4: timing = 0x10c9a731; break; 1760 default: timing = 0x0120a7a7; 1761 } 1762 break; 1763 case 0xd9: /* 40Mhz */ 1764 switch (mode) { 1765 case ATA_PIO0: timing = 0x4018d9d9; break; 1766 case ATA_PIO1: timing = 0x4010d9c7; break; 1767 case ATA_PIO2: timing = 0x4010d997; break; 1768 case ATA_PIO3: timing = 0x4010d974; break; 1769 case ATA_PIO4: timing = 0x4008d963; break; 1770 case ATA_WDMA2: timing = 0x2008d943; break; 1771 case ATA_UDMA2: timing = 0x100bd943; break; 1772 case ATA_UDMA4: timing = 0x100fd943; break; 1773 default: timing = 0x0120d9d9; 1774 } 1775 } 1776 } 1777 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1778} 1779 1780static int 1781hpt_cable80(struct ata_device *atadev) 1782{ 1783 device_t parent = device_get_parent(atadev->channel->dev); 1784 u_int8_t reg, val, res; 1785 1786 if (atadev->channel->chiptype==0x00081103 && pci_get_function(parent)==1) { 1787 reg = atadev->channel->unit ? 0x57 : 0x53; 1788 val = pci_read_config(parent, reg, 1); 1789 pci_write_config(parent, reg, val | 0x80, 1); 1790 } 1791 else { 1792 reg = 0x5b; 1793 val = pci_read_config(parent, reg, 1); 1794 pci_write_config(parent, reg, val & 0xfe, 1); 1795 } 1796 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2); 1797 pci_write_config(parent, reg, val, 1); 1798 return !res; 1799} 1800