ata-dma.c revision 103255
1/*- 2 * Copyright (c) 1998,1999,2000,2001,2002 S�ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/ata/ata-dma.c 103255 2002-09-12 15:25:59Z sos $ 29 */ 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/ata.h> 34#include <sys/bio.h> 35#include <sys/endian.h> 36#include <sys/malloc.h> 37#include <sys/bus.h> 38#include <sys/disk.h> 39#include <sys/devicestat.h> 40#include <pci/pcivar.h> 41#include <machine/bus.h> 42#include <sys/rman.h> 43#include <dev/ata/ata-all.h> 44 45/* prototypes */ 46static void ata_dmacreate(struct ata_device *, int, int); 47static void ata_dmasetupd_cb(void *, bus_dma_segment_t *, int, int); 48static void ata_dmasetupc_cb(void *, bus_dma_segment_t *, int, int); 49static void cyrix_timing(struct ata_device *, int, int); 50static void promise_timing(struct ata_device *, int, int); 51static void hpt_timing(struct ata_device *, int, int); 52static int hpt_cable80(struct ata_device *); 53 54/* misc defines */ 55#define ATAPI_DEVICE(atadev) \ 56 ((atadev->unit == ATA_MASTER && \ 57 atadev->channel->devices & ATA_ATAPI_MASTER) || \ 58 (atadev->unit == ATA_SLAVE && \ 59 atadev->channel->devices & ATA_ATAPI_SLAVE)) 60 61#define MAXSEGSZ PAGE_SIZE 62#define MAXTABSZ PAGE_SIZE 63#define MAXCTLDMASZ (2 * (MAXTABSZ + MAXPHYS)) 64 65struct ata_dc_cb_args { 66 bus_addr_t maddr; 67 int error; 68}; 69 70static void 71ata_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 72{ 73 struct ata_dc_cb_args *cba = (struct ata_dc_cb_args *)xsc; 74 75 if (!(cba->error = error)) 76 cba->maddr = segs[0].ds_addr; 77} 78 79int 80ata_dmaalloc(struct ata_device *atadev) 81{ 82 struct ata_channel *ch; 83 struct ata_dc_cb_args ccba; 84 struct ata_dmastate *ds; 85 int error; 86 87 ch = atadev->channel; 88 ds = &atadev->dmastate; 89 if (!ds->cdmatag) { 90 if ((error = bus_dma_tag_create(ch->dmatag, 1, PAGE_SIZE, 91 BUS_SPACE_MAXADDR_32BIT, 92 BUS_SPACE_MAXADDR, NULL, NULL, 93 MAXTABSZ, 1, MAXTABSZ, 94 BUS_DMA_ALLOCNOW, &ds->cdmatag))) 95 return error; 96 } 97 if (!ds->ddmatag) { 98 if ((error = bus_dma_tag_create(ch->dmatag, ch->alignment + 1, 0, 99 BUS_SPACE_MAXADDR_32BIT, 100 BUS_SPACE_MAXADDR, NULL, NULL, 101 MAXPHYS, ATA_DMA_ENTRIES, MAXSEGSZ, 102 BUS_DMA_ALLOCNOW, &ds->ddmatag))) 103 return error; 104 } 105 if (!ds->mdmatab) { 106 if ((error = bus_dmamem_alloc(ds->cdmatag, (void **)&ds->dmatab, 0, 107 &ds->cdmamap))) 108 return error; 109 110 if ((error = bus_dmamap_load(ds->cdmatag, ds->cdmamap, ds->dmatab, 111 MAXTABSZ, ata_dmasetupc_cb, &ccba, 112 0)) != 0 || ccba.error != 0) { 113 bus_dmamem_free(ds->cdmatag, ds->dmatab, ds->cdmamap); 114 return error; 115 } 116 ds->mdmatab = ccba.maddr; 117 } 118 if (!ds->ddmamap) { 119 if ((error = bus_dmamap_create(ds->ddmatag, 0, &ds->ddmamap)) != 0) 120 return error; 121 } 122 return 0; 123} 124 125void 126ata_dmafree(struct ata_device *atadev) 127{ 128 struct ata_dmastate *ds; 129 130 ds = &atadev->dmastate; 131 if (ds->mdmatab) { 132 bus_dmamap_unload(ds->cdmatag, ds->cdmamap); 133 bus_dmamem_free(ds->cdmatag, ds->dmatab, ds->cdmamap); 134 ds->mdmatab = 0; 135 ds->cdmamap = NULL; 136 ds->dmatab = NULL; 137 } 138 if (ds->ddmamap) { 139 bus_dmamap_destroy(ds->ddmatag, ds->ddmamap); 140 ds->ddmamap = NULL; 141 } 142 if (ds->cdmatag) { 143 bus_dma_tag_destroy(ds->cdmatag); 144 ds->cdmatag = NULL; 145 } 146 if (ds->ddmatag) { 147 bus_dma_tag_destroy(ds->ddmatag); 148 ds->ddmatag = NULL; 149 } 150} 151 152void 153ata_dmafreetags(struct ata_channel *ch) 154{ 155 156 if (ch->dmatag) { 157 bus_dma_tag_destroy(ch->dmatag); 158 ch->dmatag = NULL; 159 } 160} 161 162static void 163ata_dmacreate(struct ata_device *atadev, int apiomode, int mode) 164{ 165 166 atadev->mode = mode; 167 if (!atadev->channel->dmatag) { 168 if (bus_dma_tag_create(NULL, 1, 0, 169 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, 170 NULL, NULL, MAXCTLDMASZ, ATA_DMA_ENTRIES, 171 BUS_SPACE_MAXSIZE_32BIT, 0, 172 &atadev->channel->dmatag)) { 173 ata_prtdev(atadev, "DMA tag allocation failed, disabling DMA\n"); 174 ata_dmainit(atadev, apiomode, -1, -1); 175 } 176 } 177} 178 179void 180ata_dmainit(struct ata_device *atadev, int apiomode, int wdmamode, int udmamode) 181{ 182 device_t parent = device_get_parent(atadev->channel->dev); 183 int chiptype = atadev->channel->chiptype; 184 int chiprev = pci_get_revid(parent); 185 int channel = atadev->channel->unit; 186 int device = ATA_DEV(atadev->unit); 187 int devno = (channel << 1) + device; 188 int error; 189 190 /* set our most pessimistic default mode */ 191 atadev->mode = ATA_PIO; 192 193 if (!atadev->channel->r_bmio) 194 return; 195 196 /* if simplex controller, only allow DMA on primary channel */ 197 if (channel == 1) { 198 ATA_OUTB(atadev->channel->r_bmio, ATA_BMSTAT_PORT, 199 ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 200 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE)); 201 if (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 202 ATA_BMSTAT_DMA_SIMPLEX) { 203 ata_prtdev(atadev, "simplex device, DMA on primary only\n"); 204 return; 205 } 206 } 207 208 /* DMA engine address alignment is usually 1 word (2 bytes) */ 209 atadev->channel->alignment = 0x1; 210 211#if 1 212 if (udmamode > 2 && !atadev->param->hwres_cblid) { 213 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n"); 214 udmamode = 2; 215 } 216#endif 217 switch (chiptype) { 218 219 case 0x24cb8086: /* Intel ICH4 */ 220 case 0x248a8086: /* Intel ICH3 mobile */ 221 case 0x248b8086: /* Intel ICH3 */ 222 case 0x244a8086: /* Intel ICH2 mobile */ 223 case 0x244b8086: /* Intel ICH2 */ 224 if (udmamode >= 5) { 225 int32_t mask48, new48; 226 int16_t word54; 227 228 word54 = pci_read_config(parent, 0x54, 2); 229 if (word54 & (0x10 << devno)) { 230 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 231 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY); 232 if (bootverbose) 233 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n", 234 (error) ? "failed" : "success"); 235 if (!error) { 236 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 237 new48 = (1 << devno) + (1 << (16 + (devno << 2))); 238 pci_write_config(parent, 0x48, 239 (pci_read_config(parent, 0x48, 4) & 240 ~mask48) | new48, 4); 241 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2); 242 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 243 return; 244 } 245 } 246 } 247 /* make sure eventual ATA100 mode from the BIOS is disabled */ 248 pci_write_config(parent, 0x54, 249 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2); 250 /* FALLTHROUGH */ 251 252 case 0x24118086: /* Intel ICH */ 253 case 0x76018086: /* Intel ICH */ 254 if (udmamode >= 4) { 255 int32_t mask48, new48; 256 int16_t word54; 257 258 word54 = pci_read_config(parent, 0x54, 2); 259 if (word54 & (0x10 << devno)) { 260 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 261 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 262 if (bootverbose) 263 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n", 264 (error) ? "failed" : "success"); 265 if (!error) { 266 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 267 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 268 pci_write_config(parent, 0x48, 269 (pci_read_config(parent, 0x48, 4) & 270 ~mask48) | new48, 4); 271 pci_write_config(parent, 0x54, word54 | (1 << devno), 2); 272 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 273 return; 274 } 275 } 276 } 277 /* make sure eventual ATA66 mode from the BIOS is disabled */ 278 pci_write_config(parent, 0x54, 279 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2); 280 /* FALLTHROUGH */ 281 282 case 0x71118086: /* Intel PIIX4 */ 283 case 0x84CA8086: /* Intel PIIX4 */ 284 case 0x71998086: /* Intel PIIX4e */ 285 case 0x24218086: /* Intel ICH0 */ 286 if (udmamode >= 2) { 287 int32_t mask48, new48; 288 289 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 290 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 291 if (bootverbose) 292 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n", 293 (error) ? "failed" : "success"); 294 if (!error) { 295 mask48 = (1 << devno) + (3 << (16 + (devno << 2))); 296 new48 = (1 << devno) + (2 << (16 + (devno << 2))); 297 pci_write_config(parent, 0x48, 298 (pci_read_config(parent, 0x48, 4) & 299 ~mask48) | new48, 4); 300 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 301 return; 302 } 303 } 304 /* make sure eventual ATA33 mode from the BIOS is disabled */ 305 pci_write_config(parent, 0x48, 306 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4); 307 /* FALLTHROUGH */ 308 309 case 0x70108086: /* Intel PIIX3 */ 310 if (wdmamode >= 2 && apiomode >= 4) { 311 int32_t mask40, new40, mask44, new44; 312 313 /* if SITRE not set doit for both channels */ 314 if (!((pci_read_config(parent, 0x40, 4) >> (channel<<8)) & 0x4000)){ 315 new40 = pci_read_config(parent, 0x40, 4); 316 new44 = pci_read_config(parent, 0x44, 4); 317 if (!(new40 & 0x00004000)) { 318 new44 &= ~0x0000000f; 319 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8); 320 } 321 if (!(new40 & 0x40000000)) { 322 new44 &= ~0x000000f0; 323 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20); 324 } 325 new40 |= 0x40004000; 326 pci_write_config(parent, 0x40, new40, 4); 327 pci_write_config(parent, 0x44, new44, 4); 328 } 329 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 330 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 331 if (bootverbose) 332 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 333 (error) ? "failed" : "success"); 334 if (!error) { 335 if (device == ATA_MASTER) { 336 mask40 = 0x0000330f; 337 new40 = 0x00002307; 338 mask44 = 0; 339 new44 = 0; 340 } 341 else { 342 mask40 = 0x000000f0; 343 new40 = 0x00000070; 344 mask44 = 0x0000000f; 345 new44 = 0x0000000b; 346 } 347 if (channel) { 348 mask40 <<= 16; 349 new40 <<= 16; 350 mask44 <<= 4; 351 new44 <<= 4; 352 } 353 pci_write_config(parent, 0x40, 354 (pci_read_config(parent, 0x40, 4) & ~mask40)| 355 new40, 4); 356 pci_write_config(parent, 0x44, 357 (pci_read_config(parent, 0x44, 4) & ~mask44)| 358 new44, 4); 359 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 360 return; 361 } 362 } 363 /* we could set PIO mode timings, but we assume the BIOS did that */ 364 break; 365 366 case 0x12308086: /* Intel PIIX */ 367 if (wdmamode >= 2 && apiomode >= 4) { 368 int32_t word40; 369 370 word40 = pci_read_config(parent, 0x40, 4); 371 word40 >>= channel * 16; 372 373 /* Check for timing config usable for DMA on controller */ 374 if (!((word40 & 0x3300) == 0x2300 && 375 ((word40 >> (device ? 4 : 0)) & 1) == 1)) 376 break; 377 378 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 379 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 380 if (bootverbose) 381 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n", 382 (error) ? "failed" : "success"); 383 if (!error) { 384 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 385 return; 386 } 387 } 388 break; 389 390 case 0x522910b9: /* AcerLabs Aladdin IV/V */ 391 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */ 392 if (chiprev < 0xc2 && 393 atadev->channel->devices & ATA_ATAPI_MASTER && 394 atadev->channel->devices & ATA_ATAPI_SLAVE) { 395 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n"); 396 break; 397 } 398 pci_write_config(parent, 0x58 + (channel << 2), 0x00310001, 4); 399 if (udmamode >= 5 && chiprev >= 0xc4) { 400 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 401 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 402 if (bootverbose) 403 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n", 404 (error) ? "failed" : "success"); 405 if (!error) { 406 int32_t word54 = pci_read_config(parent, 0x54, 4); 407 408 pci_write_config(parent, 0x4b, 409 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 410 word54 &= ~(0x000f000f << (devno << 2)); 411 word54 |= (0x000f0005 << (devno << 2)); 412 pci_write_config(parent, 0x54, word54, 4); 413 pci_write_config(parent, 0x53, 414 pci_read_config(parent, 0x53, 1) | 0x03, 1); 415 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 416 return; 417 } 418 } 419 if (udmamode >= 4 && chiprev >= 0xc2) { 420 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 421 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 422 if (bootverbose) 423 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n", 424 (error) ? "failed" : "success"); 425 if (!error) { 426 int32_t word54 = pci_read_config(parent, 0x54, 4); 427 428 pci_write_config(parent, 0x4b, 429 pci_read_config(parent, 0x4b, 1) | 0x01, 1); 430 word54 &= ~(0x000f000f << (devno << 2)); 431 word54 |= (0x00080005 << (devno << 2)); 432 pci_write_config(parent, 0x54, word54, 4); 433 pci_write_config(parent, 0x53, 434 pci_read_config(parent, 0x53, 1) | 0x03, 1); 435 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 436 return; 437 } 438 } 439 if (udmamode >= 2 && chiprev >= 0x20) { 440 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 441 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 442 if (bootverbose) 443 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n", 444 (error) ? "failed" : "success"); 445 if (!error) { 446 int32_t word54 = pci_read_config(parent, 0x54, 4); 447 448 word54 &= ~(0x000f000f << (devno << 2)); 449 word54 |= (0x000a0005 << (devno << 2)); 450 pci_write_config(parent, 0x54, word54, 4); 451 pci_write_config(parent, 0x53, 452 pci_read_config(parent, 0x53, 1) | 0x03, 1); 453 atadev->channel->flags |= ATA_ATAPI_DMA_RO; 454 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 455 return; 456 } 457 } 458 459 /* make sure eventual UDMA mode from the BIOS is disabled */ 460 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) & 461 ~(0x0008 << (devno << 2)), 2); 462 463 if (wdmamode >= 2 && apiomode >= 4) { 464 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 465 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 466 if (bootverbose) 467 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n", 468 (error) ? "failed" : "success"); 469 if (!error) { 470 pci_write_config(parent, 0x53, 471 pci_read_config(parent, 0x53, 1) | 0x03, 1); 472 atadev->channel->flags |= ATA_ATAPI_DMA_RO; 473 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 474 return; 475 } 476 } 477 pci_write_config(parent, 0x53, 478 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1); 479 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 480 ATA_PIO0 + apiomode, 481 ATA_C_F_SETXFER, ATA_WAIT_READY); 482 if (bootverbose) 483 ata_prtdev(atadev, "%s setting PIO%d on Acer chip\n", 484 (error) ? "failed" : "success", 485 (apiomode >= 0) ? apiomode : 0); 486 if (!error) { 487 int32_t word54 = pci_read_config(parent, 0x54, 4); 488 int32_t timing; 489 490 switch(ATA_PIO0 + apiomode) { 491 case ATA_PIO0: timing = 0x006d0003; 492 case ATA_PIO1: timing = 0x00580002; 493 case ATA_PIO2: timing = 0x00440001; 494 case ATA_PIO3: timing = 0x00330001; 495 case ATA_PIO4: timing = 0x00310001; 496 default: timing = 0x006d0003; 497 } 498 pci_write_config(parent, 0x58 + (channel << 2), timing, 4); 499 word54 &= ~(0x000f000f << (devno << 2)); 500 word54 |= (0x00000004 << (devno << 2)); 501 pci_write_config(parent, 0x54, word54, 4); 502 atadev->mode = ATA_PIO0 + apiomode; 503 return; 504 } 505 break; 506 507 case 0x01bc10de: /* nVIDIA nForce */ 508 case 0x74411022: /* AMD 768 */ 509 case 0x74111022: /* AMD 766 */ 510 case 0x74091022: /* AMD 756 */ 511 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686 , 8231, 8233 */ 512 { 513 int via_modes[5][7] = { 514 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */ 515 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */ 516 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */ 517 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */ 518 { 0x00, 0x00, 0xc0, 0x00, 0xc5, 0xc6, 0x00 }}; /* AMD/nVIDIA */ 519 int *reg_val = NULL; 520 char *chip = "VIA"; 521 522 if (ata_find_dev(parent, 0x31471106, 0)) { /* 8233a */ 523 udmamode = imin(udmamode, 6); 524 reg_val = via_modes[3]; 525 } 526 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */ 527 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */ 528 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */ 529 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */ 530 udmamode = imin(udmamode, 5); 531 reg_val = via_modes[2]; 532 } 533 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */ 534 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */ 535 udmamode = imin(udmamode, 4); 536 reg_val = via_modes[1]; 537 } 538 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */ 539 udmamode = imin(udmamode, 2); 540 reg_val = via_modes[1]; 541 } 542 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */ 543 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */ 544 udmamode = imin(udmamode, 2); 545 reg_val = via_modes[0]; 546 } 547 else if (chiptype == 0x74411022 || /* AMD 768 */ 548 chiptype == 0x74111022) { /* AMD 766 */ 549 udmamode = imin(udmamode, 5); 550 reg_val = via_modes[4]; 551 chip = "AMD"; 552 } 553 else if (chiptype == 0x74091022) { /* AMD 756 */ 554 udmamode = imin(udmamode, 4); 555 reg_val = via_modes[4]; 556 chip = "AMD"; 557 } 558 else if (chiptype == 0x01bc10de) { /* nVIDIA */ 559 udmamode = imin(udmamode, 5); 560 reg_val = via_modes[4]; 561 chip = "nVIDIA"; 562 } 563 else 564 udmamode = 0; 565 566 if (udmamode >= 6) { 567 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 568 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 569 if (bootverbose) 570 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n", 571 (error) ? "failed" : "success", chip); 572 if (!error) { 573 pci_write_config(parent, 0x53 - devno, reg_val[6], 1); 574 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 575 return; 576 } 577 } 578 if (udmamode >= 5) { 579 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 580 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 581 if (bootverbose) 582 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n", 583 (error) ? "failed" : "success", chip); 584 if (!error) { 585 pci_write_config(parent, 0x53 - devno, reg_val[5], 1); 586 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 587 return; 588 } 589 } 590 if (udmamode >= 4) { 591 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 592 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 593 if (bootverbose) 594 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n", 595 (error) ? "failed" : "success", chip); 596 if (!error) { 597 pci_write_config(parent, 0x53 - devno, reg_val[4], 1); 598 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 599 return; 600 } 601 } 602 if (udmamode >= 2) { 603 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 604 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 605 if (bootverbose) 606 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n", 607 (error) ? "failed" : "success", chip); 608 if (!error) { 609 pci_write_config(parent, 0x53 - devno, reg_val[2], 1); 610 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 611 return; 612 } 613 } 614 if (wdmamode >= 2 && apiomode >= 4) { 615 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 616 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 617 if (bootverbose) 618 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n", 619 (error) ? "failed" : "success", chip); 620 if (!error) { 621 pci_write_config(parent, 0x53 - devno, 0x0b, 1); 622 pci_write_config(parent, 0x4b - devno, 0x31, 1); 623 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 624 return; 625 } 626 } 627 } 628 /* we could set PIO mode timings, but we assume the BIOS did that */ 629 break; 630 631 case 0x55131039: /* SiS 5591 */ 632 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */ 633 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */ 634 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */ 635 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */ 636 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */ 637 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */ 638 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */ 639 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */ 640 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */ 641 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */ 642 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */ 643 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */ 644 int8_t reg = 0x40 + (devno << 1); 645 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 646 647 if (udmamode >= 5) { 648 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 649 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 650 if (bootverbose) 651 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n", 652 (error) ? "failed" : "success"); 653 if (!error) { 654 pci_write_config(parent, reg, val | 0x8000, 2); 655 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 656 return; 657 } 658 } 659 if (udmamode >= 4) { 660 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 661 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 662 if (bootverbose) 663 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 664 (error) ? "failed" : "success"); 665 if (!error) { 666 pci_write_config(parent, reg, val | 0x9000, 2); 667 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 668 return; 669 } 670 } 671 if (udmamode >= 2) { 672 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 673 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 674 if (bootverbose) 675 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 676 (error) ? "failed" : "success"); 677 if (!error) { 678 pci_write_config(parent, reg, val | 0xb000, 2); 679 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 680 return; 681 } 682 } 683 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */ 684 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */ 685 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */ 686 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */ 687 int8_t reg = 0x40 + (devno << 1); 688 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff; 689 690 if (udmamode >= 4) { 691 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 692 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 693 if (bootverbose) 694 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n", 695 (error) ? "failed" : "success"); 696 if (!error) { 697 pci_write_config(parent, reg, val | 0x9000, 2); 698 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 699 return; 700 } 701 } 702 if (udmamode >= 2) { 703 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 704 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 705 if (bootverbose) 706 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 707 (error) ? "failed" : "success"); 708 if (!error) { 709 pci_write_config(parent, reg, val | 0xa000, 2); 710 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 711 return; 712 } 713 } 714 } else if (udmamode >= 2 && chiprev > 0xc1) { 715 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 716 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 717 if (bootverbose) 718 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n", 719 (error) ? "failed" : "success"); 720 if (!error) { 721 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2); 722 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 723 return; 724 } 725 } 726 if (wdmamode >=2 && apiomode >= 4) { 727 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 728 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 729 if (bootverbose) 730 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n", 731 (error) ? "failed" : "success"); 732 if (!error) { 733 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2); 734 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 735 return; 736 } 737 } 738 /* we could set PIO mode timings, but we assume the BIOS did that */ 739 break; 740 741 case 0x06801095: /* Sil 0680 ATA133 controller */ 742 { 743 u_int8_t ureg = 0xac + (device * 0x02) + (channel * 0x10); 744 u_int8_t uval = pci_read_config(parent, ureg, 1); 745 u_int8_t mreg = channel ? 0x84 : 0x80; 746 u_int8_t mask = device ? 0x30 : 0x03; 747 u_int8_t mode = pci_read_config(parent, mreg, 1); 748 749 /* enable UDMA mode */ 750 pci_write_config(parent, mreg, 751 (mode & ~mask) | (device ? 0x30 : 0x03), 1); 752 if (udmamode >= 6) { 753 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 754 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 755 if (bootverbose) 756 ata_prtdev(atadev, "%s setting UDMA6 on Sil chip\n", 757 (error) ? "failed" : "success"); 758 if (!error) { 759 pci_write_config(parent, ureg, (uval & 0x3f) | 0x01, 1); 760 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 761 return; 762 } 763 } 764 if (udmamode >= 5) { 765 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 766 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 767 if (bootverbose) 768 ata_prtdev(atadev, "%s setting UDMA5 on Sil chip\n", 769 (error) ? "failed" : "success"); 770 if (!error) { 771 pci_write_config(parent, ureg, (uval & 0x3f) | 0x02, 1); 772 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 773 return; 774 } 775 } 776 if (udmamode >= 4) { 777 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 778 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 779 if (bootverbose) 780 ata_prtdev(atadev, "%s setting UDMA4 on Sil chip\n", 781 (error) ? "failed" : "success"); 782 if (!error) { 783 pci_write_config(parent, ureg, (uval & 0x3f) | 0x03, 1); 784 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 785 return; 786 } 787 } 788 if (udmamode >= 2) { 789 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 790 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 791 if (bootverbose) 792 ata_prtdev(atadev, "%s setting UDMA2 on Sil chip\n", 793 (error) ? "failed" : "success"); 794 if (!error) { 795 pci_write_config(parent, ureg, (uval & 0x3f) | 0x07, 1); 796 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 797 return; 798 } 799 } 800 801 /* disable UDMA mode and enable WDMA mode */ 802 pci_write_config(parent, mreg, 803 (mode & ~mask) | (device ? 0x20 : 0x02), 1); 804 if (wdmamode >= 2 && apiomode >= 4) { 805 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 806 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 807 if (bootverbose) 808 ata_prtdev(atadev, "%s setting WDMA2 on Sil chip\n", 809 (error) ? "failed" : "success"); 810 if (!error) { 811 pci_write_config(parent, ureg - 0x4, 0x10c1, 2); 812 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 813 return; 814 } 815 } 816 817 /* restore PIO mode */ 818 pci_write_config(parent, mreg, mode, 1); 819 } 820 /* we could set PIO mode timings, but we assume the BIOS did that */ 821 break; 822 823 case 0x06491095: /* CMD 649 ATA100 controller */ 824 if (udmamode >= 5) { 825 u_int8_t umode; 826 827 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 828 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 829 if (bootverbose) 830 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n", 831 (error) ? "failed" : "success"); 832 if (!error) { 833 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 834 umode &= ~(device ? 0xca : 0x35); 835 umode |= (device ? 0x0a : 0x05); 836 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 837 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 838 return; 839 } 840 } 841 /* FALLTHROUGH */ 842 843 case 0x06481095: /* CMD 648 ATA66 controller */ 844 if (udmamode >= 4) { 845 u_int8_t umode; 846 847 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 848 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 849 if (bootverbose) 850 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n", 851 (error) ? "failed" : "success"); 852 if (!error) { 853 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 854 umode &= ~(device ? 0xca : 0x35); 855 umode |= (device ? 0x4a : 0x15); 856 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 857 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 858 return; 859 } 860 } 861 if (udmamode >= 2) { 862 u_int8_t umode; 863 864 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 865 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 866 if (bootverbose) 867 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n", 868 (error) ? "failed" : "success"); 869 if (!error) { 870 umode = pci_read_config(parent, channel ? 0x7b : 0x73, 1); 871 umode &= ~(device ? 0xca : 0x35); 872 umode |= (device ? 0x42 : 0x11); 873 pci_write_config(parent, channel ? 0x7b : 0x73, umode, 1); 874 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 875 return; 876 } 877 } 878 /* make sure eventual UDMA mode from the BIOS is disabled */ 879 pci_write_config(parent, channel ? 0x7b : 0x73, 880 pci_read_config(parent, channel ? 0x7b : 0x73, 1) & 881 ~(device ? 0xca : 0x53), 1); 882 /* FALLTHROUGH */ 883 884 case 0x06461095: /* CMD 646 ATA controller */ 885 if (wdmamode >= 2 && apiomode >= 4) { 886 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 887 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 888 if (bootverbose) 889 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n", 890 error ? "failed" : "success"); 891 if (!error) { 892 int32_t offset = (devno < 3) ? (devno << 1) : 7; 893 894 pci_write_config(parent, 0x54 + offset, 0x3f, 1); 895 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 896 return; 897 } 898 } 899 /* we could set PIO mode timings, but we assume the BIOS did that */ 900 break; 901 902 case 0xc6931080: /* Cypress 82c693 ATA controller */ 903 if (wdmamode >= 2 && apiomode >= 4) { 904 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 905 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 906 if (bootverbose) 907 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n", 908 error ? "failed" : "success"); 909 if (!error) { 910 pci_write_config(atadev->channel->dev, 911 channel ? 0x4e:0x4c, 0x2020, 2); 912 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 913 return; 914 } 915 } 916 /* we could set PIO mode timings, but we assume the BIOS did that */ 917 break; 918 919 case 0x01021078: /* Cyrix 5530 ATA33 controller */ 920 atadev->channel->alignment = 0xf; 921 if (udmamode >= 2) { 922 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 923 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 924 if (bootverbose) 925 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n", 926 (error) ? "failed" : "success"); 927 if (!error) { 928 cyrix_timing(atadev, devno, ATA_UDMA2); 929 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 930 return; 931 } 932 } 933 if (wdmamode >= 2 && apiomode >= 4) { 934 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 935 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 936 if (bootverbose) 937 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n", 938 (error) ? "failed" : "success"); 939 if (!error) { 940 cyrix_timing(atadev, devno, ATA_WDMA2); 941 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 942 return; 943 } 944 } 945 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 946 ATA_PIO0 + apiomode, ATA_C_F_SETXFER, 947 ATA_WAIT_READY); 948 if (bootverbose) 949 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n", 950 (error) ? "failed" : "success", 951 ata_mode2str(ATA_PIO0 + apiomode)); 952 cyrix_timing(atadev, devno, ATA_PIO0 + apiomode); 953 atadev->mode = ATA_PIO0 + apiomode; 954 return; 955 956 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */ 957 if (udmamode >= 5 && chiprev >= 0x92) { 958 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 959 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 960 if (bootverbose) 961 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n", 962 (error) ? "failed" : "success"); 963 if (!error) { 964 u_int16_t reg56; 965 966 pci_write_config(parent, 0x54, 967 pci_read_config(parent, 0x54, 1) | 968 (0x01 << devno), 1); 969 reg56 = pci_read_config(parent, 0x56, 2); 970 reg56 &= ~(0xf << (devno * 4)); 971 reg56 |= (0x5 << (devno * 4)); 972 pci_write_config(parent, 0x56, reg56, 2); 973 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 974 return; 975 } 976 } 977 if (udmamode >= 4) { 978 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 979 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 980 if (bootverbose) 981 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n", 982 (error) ? "failed" : "success"); 983 if (!error) { 984 u_int16_t reg56; 985 986 pci_write_config(parent, 0x54, 987 pci_read_config(parent, 0x54, 1) | 988 (0x01 << devno), 1); 989 reg56 = pci_read_config(parent, 0x56, 2); 990 reg56 &= ~(0xf << (devno * 4)); 991 reg56 |= (0x4 << (devno * 4)); 992 pci_write_config(parent, 0x56, reg56, 2); 993 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 994 return; 995 } 996 } 997 /* FALLTHROUGH */ 998 999 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */ 1000 if (udmamode >= 2) { 1001 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1002 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1003 if (bootverbose) 1004 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n", 1005 (error) ? "failed" : "success"); 1006 if (!error) { 1007 u_int16_t reg56; 1008 1009 pci_write_config(parent, 0x54, 1010 pci_read_config(parent, 0x54, 1) | 1011 (0x01 << devno), 1); 1012 reg56 = pci_read_config(parent, 0x56, 2); 1013 reg56 &= ~(0xf << (devno * 4)); 1014 reg56 |= (0x2 << (devno * 4)); 1015 pci_write_config(parent, 0x56, reg56, 2); 1016 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1017 return; 1018 } 1019 } 1020 if (wdmamode >= 2 && apiomode >= 4) { 1021 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1022 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1023 if (bootverbose) 1024 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n", 1025 (error) ? "failed" : "success"); 1026 if (!error) { 1027 int offset = devno ^ 0x01; 1028 int word44 = pci_read_config(parent, 0x44, 4); 1029 1030 pci_write_config(parent, 0x54, 1031 pci_read_config(parent, 0x54, 1) & 1032 ~(0x01 << devno), 1); 1033 word44 &= ~(0xff << (offset << 8)); 1034 word44 |= (0x20 << (offset << 8)); 1035 pci_write_config(parent, 0x44, 0x20, 4); 1036 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1037 return; 1038 } 1039 } 1040 /* we could set PIO mode timings, but we assume the BIOS did that */ 1041 break; 1042 1043 case 0x4d69105a: /* Promise TX2 ATA133 controllers */ 1044 case 0x5275105a: /* Promise TX2 ATA133 controllers */ 1045 case 0x6269105a: /* Promise TX2 ATA133 controllers */ 1046 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 1047 if (udmamode >= 6 && 1048 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 1049 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1050 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 1051 if (bootverbose) 1052 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n", 1053 (error) ? "failed" : "success"); 1054 if (!error) { 1055 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 1056 return; 1057 } 1058 } 1059 /* FALLTHROUGH */ 1060 1061 case 0x4d68105a: /* Promise TX2 ATA100 controllers */ 1062 case 0x6268105a: /* Promise TX2 ATA100 controllers */ 1063 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 1064 if (udmamode >= 5 && 1065 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 1066 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1067 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1068 if (bootverbose) 1069 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 1070 (error) ? "failed" : "success"); 1071 if (!error) { 1072 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1073 return; 1074 } 1075 } 1076 ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b); 1077 if (udmamode >= 4 && 1078 !(ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) { 1079 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1080 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1081 if (bootverbose) 1082 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 1083 (error) ? "failed" : "success"); 1084 if (!error) { 1085 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1086 return; 1087 } 1088 } 1089 if (udmamode >= 2) { 1090 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1091 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1092 if (bootverbose) 1093 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n", 1094 (error) ? "failed" : "success"); 1095 if (!error) { 1096 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1097 return; 1098 } 1099 } 1100 if (wdmamode >= 2 && apiomode >= 4) { 1101 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1102 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1103 if (bootverbose) 1104 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 1105 (error) ? "failed" : "success"); 1106 if (!error) { 1107 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1108 return; 1109 } 1110 } 1111 break; 1112 1113 case 0x0d30105a: /* Promise OEM ATA100 controllers */ 1114 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */ 1115 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && 1116 !(pci_read_config(parent, 0x50, 2) & (channel ? 1<<11 : 1<<10))) { 1117 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1118 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1119 if (bootverbose) 1120 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n", 1121 (error) ? "failed" : "success"); 1122 if (!error) { 1123 promise_timing(atadev, devno, ATA_UDMA5); 1124 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1125 return; 1126 } 1127 } 1128 /* FALLTHROUGH */ 1129 1130 case 0x0d38105a: /* Promise FastTrak 66 controllers */ 1131 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */ 1132 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && 1133 !(pci_read_config(parent, 0x50, 2) & (channel ? 1<<11 : 1<<10))) { 1134 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1135 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1136 if (bootverbose) 1137 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n", 1138 (error) ? "failed" : "success"); 1139 if (!error) { 1140 promise_timing(atadev, devno, ATA_UDMA4); 1141 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1142 return; 1143 } 1144 } 1145 /* FALLTHROUGH */ 1146 1147 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */ 1148 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) { 1149 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1150 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1151 if (bootverbose) 1152 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n", 1153 (error) ? "failed" : "success"); 1154 if (!error) { 1155 promise_timing(atadev, devno, ATA_UDMA2); 1156 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1157 return; 1158 } 1159 } 1160 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) { 1161 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1162 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1163 if (bootverbose) 1164 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n", 1165 (error) ? "failed" : "success"); 1166 if (!error) { 1167 promise_timing(atadev, devno, ATA_WDMA2); 1168 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1169 return; 1170 } 1171 } 1172 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1173 ATA_PIO0 + apiomode, 1174 ATA_C_F_SETXFER, ATA_WAIT_READY); 1175 if (bootverbose) 1176 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n", 1177 (error) ? "failed" : "success", 1178 (apiomode >= 0) ? apiomode : 0); 1179 promise_timing(atadev, devno, ATA_PIO0 + apiomode); 1180 atadev->mode = ATA_PIO0 + apiomode; 1181 return; 1182 1183 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */ 1184 case 0x00051103: /* HighPoint HPT372 controllers */ 1185 case 0x00081103: /* HighPoint HPT374 controllers */ 1186 if (!ATAPI_DEVICE(atadev) && udmamode >= 6 && hpt_cable80(atadev) && 1187 ((chiptype == 0x00041103 && chiprev >= 0x05) || 1188 (chiptype == 0x00051103 && chiprev >= 0x01) || 1189 (chiptype == 0x00081103 && chiprev >= 0x07))) { 1190 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1191 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY); 1192 if (bootverbose) 1193 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n", 1194 (error) ? "failed" : "success"); 1195 if (!error) { 1196 hpt_timing(atadev, devno, ATA_UDMA6); 1197 ata_dmacreate(atadev, apiomode, ATA_UDMA6); 1198 return; 1199 } 1200 } 1201 if (!ATAPI_DEVICE(atadev) && udmamode >= 5 && hpt_cable80(atadev) && 1202 ((chiptype == 0x00041103 && chiprev >= 0x03) || 1203 (chiptype == 0x00051103 && chiprev >= 0x01) || 1204 (chiptype == 0x00081103 && chiprev >= 0x07))) { 1205 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1206 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY); 1207 if (bootverbose) 1208 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n", 1209 (error) ? "failed" : "success"); 1210 if (!error) { 1211 hpt_timing(atadev, devno, ATA_UDMA5); 1212 ata_dmacreate(atadev, apiomode, ATA_UDMA5); 1213 return; 1214 } 1215 } 1216 if (!ATAPI_DEVICE(atadev) && udmamode >= 4 && hpt_cable80(atadev)) { 1217 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1218 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY); 1219 if (bootverbose) 1220 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n", 1221 (error) ? "failed" : "success"); 1222 if (!error) { 1223 hpt_timing(atadev, devno, ATA_UDMA4); 1224 ata_dmacreate(atadev, apiomode, ATA_UDMA4); 1225 return; 1226 } 1227 } 1228 if (!ATAPI_DEVICE(atadev) && udmamode >= 2) { 1229 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1230 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1231 if (bootverbose) 1232 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n", 1233 (error) ? "failed" : "success"); 1234 if (!error) { 1235 hpt_timing(atadev, devno, ATA_UDMA2); 1236 ata_dmacreate(atadev, apiomode, ATA_UDMA2); 1237 return; 1238 } 1239 } 1240 if (!ATAPI_DEVICE(atadev) && wdmamode >= 2 && apiomode >= 4) { 1241 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1242 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1243 if (bootverbose) 1244 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n", 1245 (error) ? "failed" : "success"); 1246 if (!error) { 1247 hpt_timing(atadev, devno, ATA_WDMA2); 1248 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1249 return; 1250 } 1251 } 1252 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1253 ATA_PIO0 + apiomode, 1254 ATA_C_F_SETXFER, ATA_WAIT_READY); 1255 if (bootverbose) 1256 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n", 1257 (error) ? "failed" : "success", 1258 (apiomode >= 0) ? apiomode : 0); 1259 hpt_timing(atadev, devno, ATA_PIO0 + apiomode); 1260 atadev->mode = ATA_PIO0 + apiomode; 1261 return; 1262 1263 case 0x000116ca: /* Cenatek Rocket Drive controller */ 1264 if (wdmamode >= 0 && 1265 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 1266 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) 1267 ata_dmacreate(atadev, apiomode, ATA_DMA); 1268 else 1269 atadev->mode = ATA_PIO; 1270 return; 1271 1272 default: /* unknown controller chip */ 1273 /* better not try generic DMA on ATAPI devices it almost never works */ 1274 if (ATAPI_DEVICE(atadev)) 1275 break; 1276 1277 /* if controller says its setup for DMA take the easy way out */ 1278 /* the downside is we dont know what DMA mode we are in */ 1279 if ((udmamode >= 0 || wdmamode >= 2) && 1280 (ATA_INB(atadev->channel->r_bmio, ATA_BMSTAT_PORT) & 1281 (device ? ATA_BMSTAT_DMA_SLAVE : ATA_BMSTAT_DMA_MASTER))) { 1282 ata_dmacreate(atadev, apiomode, ATA_DMA); 1283 return; 1284 } 1285 1286 /* well, we have no support for this, but try anyways */ 1287 if ((wdmamode >= 2 && apiomode >= 4) && atadev->channel->r_bmio) { 1288 error = ata_command(atadev, ATA_C_SETFEATURES, 0, 1289 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY); 1290 if (bootverbose) 1291 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n", 1292 (error) ? "failed" : "success"); 1293 if (!error) { 1294 ata_dmacreate(atadev, apiomode, ATA_WDMA2); 1295 return; 1296 } 1297 } 1298 } 1299 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode, 1300 ATA_C_F_SETXFER, ATA_WAIT_READY); 1301 if (bootverbose) 1302 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n", 1303 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode); 1304 if (!error) 1305 atadev->mode = ATA_PIO0 + apiomode; 1306 else { 1307 if (bootverbose) 1308 ata_prtdev(atadev, "using PIO mode set by BIOS\n"); 1309 atadev->mode = ATA_PIO; 1310 } 1311} 1312 1313struct ata_dmasetup_data_cb_args { 1314 struct ata_dmaentry *dmatab; 1315 int error; 1316}; 1317 1318static void 1319ata_dmasetupd_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1320{ 1321 struct ata_dmasetup_data_cb_args *cba = 1322 (struct ata_dmasetup_data_cb_args *)xsc; 1323 bus_size_t cnt; 1324 u_int32_t lastcount; 1325 int i, j; 1326 1327 cba->error = error; 1328 if (error != 0) 1329 return; 1330 lastcount = j = 0; 1331 for (i = 0; i < nsegs; i++) { 1332 /* 1333 * A maximum segment size was specified for bus_dma_tag_create, but 1334 * some busdma code does not seem to honor this, so fix up if needed. 1335 */ 1336 for (cnt = 0; cnt < segs[i].ds_len; cnt += MAXSEGSZ, j++) { 1337 cba->dmatab[j].base = htole32(segs[i].ds_addr + cnt); 1338 lastcount = ulmin(segs[i].ds_len - cnt, MAXSEGSZ) & 0xffff; 1339 cba->dmatab[j].count = htole32(lastcount); 1340 } 1341 } 1342 cba->dmatab[j - 1].count = htole32(lastcount | ATA_DMA_EOT); 1343} 1344 1345int 1346ata_dmasetup(struct ata_device *atadev, caddr_t data, int32_t count) 1347{ 1348 struct ata_channel *ch = atadev->channel; 1349 1350 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) { 1351 ata_prtdev(atadev, "non aligned DMA transfer attempted\n"); 1352 return -1; 1353 } 1354 1355 if (!count) { 1356 ata_prtdev(atadev, "zero length DMA transfer attempted\n"); 1357 return -1; 1358 } 1359 return 0; 1360} 1361 1362int 1363ata_dmastart(struct ata_device *atadev, caddr_t data, int32_t count, int dir) 1364{ 1365 struct ata_channel *ch = atadev->channel; 1366 struct ata_dmastate *ds = &atadev->dmastate; 1367 struct ata_dmasetup_data_cb_args cba; 1368 1369 if (ds->flags & ATA_DS_ACTIVE) 1370 panic("ata_dmasetup: transfer active on this device!"); 1371 1372 cba.dmatab = ds->dmatab; 1373 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_PREWRITE); 1374 if (bus_dmamap_load(ds->ddmatag, ds->ddmamap, data, count, 1375 ata_dmasetupd_cb, &cba, 0) || cba.error) 1376 return -1; 1377 1378 bus_dmamap_sync(ds->cdmatag, ds->cdmamap, BUS_DMASYNC_POSTWRITE); 1379 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, dir ? BUS_DMASYNC_PREREAD : 1380 BUS_DMASYNC_PREWRITE); 1381 1382 ch->flags |= ATA_DMA_ACTIVE; 1383 ds->flags = ATA_DS_ACTIVE; 1384 if (dir) 1385 ds->flags |= ATA_DS_READ; 1386 1387 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, ds->mdmatab); 1388 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0); 1389 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1390 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) | 1391 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR))); 1392 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1393 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP); 1394 return 0; 1395} 1396 1397int 1398ata_dmadone(struct ata_device *atadev) 1399{ 1400 struct ata_channel *ch; 1401 struct ata_dmastate *ds; 1402 int error; 1403 1404 ch = atadev->channel; 1405 ds = &atadev->dmastate; 1406 bus_dmamap_sync(ds->ddmatag, ds->ddmamap, (ds->flags & ATA_DS_READ) != 0 ? 1407 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1408 bus_dmamap_unload(ds->ddmatag, ds->ddmamap); 1409 1410 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, 1411 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP); 1412 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT); 1413 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, 1414 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR); 1415 ch->flags &= ~ATA_DMA_ACTIVE; 1416 ds->flags = 0; 1417 return (error & ATA_BMSTAT_MASK); 1418} 1419 1420int 1421ata_dmastatus(struct ata_channel *ch) 1422{ 1423 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK; 1424} 1425 1426static void 1427cyrix_timing(struct ata_device *atadev, int devno, int mode) 1428{ 1429 u_int32_t reg20 = 0x0000e132; 1430 u_int32_t reg24 = 0x00017771; 1431 1432 switch (mode) { 1433 case ATA_PIO0: reg20 = 0x0000e132; break; 1434 case ATA_PIO1: reg20 = 0x00018121; break; 1435 case ATA_PIO2: reg20 = 0x00024020; break; 1436 case ATA_PIO3: reg20 = 0x00032010; break; 1437 case ATA_PIO4: reg20 = 0x00040010; break; 1438 case ATA_WDMA2: reg24 = 0x00002020; break; 1439 case ATA_UDMA2: reg24 = 0x00911030; break; 1440 } 1441 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x20, reg20); 1442 ATA_OUTL(atadev->channel->r_bmio, (devno << 3) + 0x24, reg24); 1443} 1444 1445static void 1446promise_timing(struct ata_device *atadev, int devno, int mode) 1447{ 1448 u_int32_t timing = 0; 1449 /* XXX: Endianess */ 1450 struct promise_timing { 1451 u_int8_t pa:4; 1452 u_int8_t prefetch:1; 1453 u_int8_t iordy:1; 1454 u_int8_t errdy:1; 1455 u_int8_t syncin:1; 1456 u_int8_t pb:5; 1457 u_int8_t mb:3; 1458 u_int8_t mc:4; 1459 u_int8_t dmaw:1; 1460 u_int8_t dmar:1; 1461 u_int8_t iordyp:1; 1462 u_int8_t dmarqp:1; 1463 u_int8_t reserved:8; 1464 } *t = (struct promise_timing*)&timing; 1465 1466 t->iordy = 1; t->iordyp = 1; 1467 if (mode >= ATA_DMA) { 1468 t->prefetch = 1; t->errdy = 1; t->syncin = 1; 1469 } 1470 1471 switch (atadev->channel->chiptype) { 1472 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */ 1473 switch (mode) { 1474 default: 1475 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break; 1476 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break; 1477 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break; 1478 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break; 1479 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break; 1480 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break; 1481 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1482 } 1483 break; 1484 1485 case 0x0d38105a: /* Promise Fasttrak 66 */ 1486 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */ 1487 case 0x0d30105a: /* Promise OEM ATA 100 */ 1488 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */ 1489 switch (mode) { 1490 default: 1491 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break; 1492 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break; 1493 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break; 1494 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break; 1495 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break; 1496 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break; 1497 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break; 1498 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1499 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break; 1500 } 1501 break; 1502 } 1503 pci_write_config(device_get_parent(atadev->channel->dev), 1504 0x60 + (devno << 2), timing, 4); 1505} 1506 1507static void 1508hpt_timing(struct ata_device *atadev, int devno, int mode) 1509{ 1510 device_t parent = device_get_parent(atadev->channel->dev); 1511 u_int32_t chiptype = atadev->channel->chiptype; 1512 int chiprev = pci_get_revid(parent); 1513 u_int32_t timing; 1514 1515 if (chiptype == 0x00081103 && chiprev >= 0x07) { 1516 switch (mode) { /* HPT374 */ 1517 case ATA_PIO0: timing = 0x0ac1f48a; break; 1518 case ATA_PIO1: timing = 0x0ac1f465; break; 1519 case ATA_PIO2: timing = 0x0a81f454; break; 1520 case ATA_PIO3: timing = 0x0a81f443; break; 1521 case ATA_PIO4: timing = 0x0a81f442; break; 1522 case ATA_WDMA2: timing = 0x22808242; break; 1523 case ATA_UDMA2: timing = 0x120c8242; break; 1524 case ATA_UDMA4: timing = 0x12ac8242; break; 1525 case ATA_UDMA5: timing = 0x12848242; break; 1526 case ATA_UDMA6: timing = 0x12808242; break; 1527 default: timing = 0x0d029d5e; 1528 } 1529 } 1530 else if ((chiptype == 0x00041103 && chiprev >= 0x05) || 1531 (chiptype == 0x00051103 && chiprev >= 0x01)) { 1532 switch (mode) { /* HPT372 */ 1533 case ATA_PIO0: timing = 0x0d029d5e; break; 1534 case ATA_PIO1: timing = 0x0d029d26; break; 1535 case ATA_PIO2: timing = 0x0c829ca6; break; 1536 case ATA_PIO3: timing = 0x0c829c84; break; 1537 case ATA_PIO4: timing = 0x0c829c62; break; 1538 case ATA_WDMA2: timing = 0x2c829262; break; 1539 case ATA_UDMA2: timing = 0x1c91dc62; break; 1540 case ATA_UDMA4: timing = 0x1c8ddc62; break; 1541 case ATA_UDMA5: timing = 0x1c6ddc62; break; 1542 case ATA_UDMA6: timing = 0x1c81dc62; break; 1543 default: timing = 0x0d029d5e; 1544 } 1545 } 1546 else if (chiptype == 0x00041103 && chiprev >= 0x03) { 1547 switch (mode) { /* HPT370 */ 1548 case ATA_PIO0: timing = 0x06914e57; break; 1549 case ATA_PIO1: timing = 0x06914e43; break; 1550 case ATA_PIO2: timing = 0x06514e33; break; 1551 case ATA_PIO3: timing = 0x06514e22; break; 1552 case ATA_PIO4: timing = 0x06514e21; break; 1553 case ATA_WDMA2: timing = 0x26514e21; break; 1554 case ATA_UDMA2: timing = 0x16494e31; break; 1555 case ATA_UDMA4: timing = 0x16454e31; break; 1556 case ATA_UDMA5: timing = 0x16454e31; break; 1557 default: timing = 0x06514e57; 1558 } 1559 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1560 } 1561 else { /* HPT36[68] */ 1562 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) { 1563 case 0x85: /* 25Mhz */ 1564 switch (mode) { 1565 case ATA_PIO0: timing = 0x40d08585; break; 1566 case ATA_PIO1: timing = 0x40d08572; break; 1567 case ATA_PIO2: timing = 0x40ca8542; break; 1568 case ATA_PIO3: timing = 0x40ca8532; break; 1569 case ATA_PIO4: timing = 0x40ca8521; break; 1570 case ATA_WDMA2: timing = 0x20ca8521; break; 1571 case ATA_UDMA2: timing = 0x10cf8521; break; 1572 case ATA_UDMA4: timing = 0x10c98521; break; 1573 default: timing = 0x01208585; 1574 } 1575 break; 1576 default: 1577 case 0xa7: /* 33MHz */ 1578 switch (mode) { 1579 case ATA_PIO0: timing = 0x40d0a7aa; break; 1580 case ATA_PIO1: timing = 0x40d0a7a3; break; 1581 case ATA_PIO2: timing = 0x40d0a753; break; 1582 case ATA_PIO3: timing = 0x40c8a742; break; 1583 case ATA_PIO4: timing = 0x40c8a731; break; 1584 case ATA_WDMA2: timing = 0x20c8a731; break; 1585 case ATA_UDMA2: timing = 0x10caa731; break; 1586 case ATA_UDMA4: timing = 0x10c9a731; break; 1587 default: timing = 0x0120a7a7; 1588 } 1589 break; 1590 case 0xd9: /* 40Mhz */ 1591 switch (mode) { 1592 case ATA_PIO0: timing = 0x4018d9d9; break; 1593 case ATA_PIO1: timing = 0x4010d9c7; break; 1594 case ATA_PIO2: timing = 0x4010d997; break; 1595 case ATA_PIO3: timing = 0x4010d974; break; 1596 case ATA_PIO4: timing = 0x4008d963; break; 1597 case ATA_WDMA2: timing = 0x2008d943; break; 1598 case ATA_UDMA2: timing = 0x100bd943; break; 1599 case ATA_UDMA4: timing = 0x100fd943; break; 1600 default: timing = 0x0120d9d9; 1601 } 1602 } 1603 } 1604 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4); 1605} 1606 1607static int 1608hpt_cable80(struct ata_device *atadev) 1609{ 1610 device_t parent = device_get_parent(atadev->channel->dev); 1611 u_int8_t reg, val, res; 1612 1613 if (atadev->channel->chiptype==0x00081103 && pci_get_function(parent)==1) { 1614 reg = atadev->channel->unit ? 0x57 : 0x53; 1615 val = pci_read_config(parent, reg, 1); 1616 pci_write_config(parent, reg, val | 0x80, 1); 1617 } 1618 else { 1619 reg = 0x5b; 1620 val = pci_read_config(parent, reg, 1); 1621 pci_write_config(parent, reg, val & 0xfe, 1); 1622 } 1623 res = pci_read_config(parent, 0x5a, 1) & (atadev->channel->unit ? 0x1:0x2); 1624 pci_write_config(parent, reg, val, 1); 1625 return !res; 1626} 1627