asmcvar.h revision 302408
1/*- 2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/11/sys/dev/asmc/asmcvar.h 298990 2016-05-03 17:11:33Z adrian $ 27 * 28 */ 29 30#define ASMC_MAXFANS 6 31 32struct asmc_softc { 33 device_t sc_dev; 34 struct mtx sc_mtx; 35 int sc_nfan; 36 int16_t sms_rest_x; 37 int16_t sms_rest_y; 38 int16_t sms_rest_z; 39 struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1]; 40 struct sysctl_oid *sc_temp_tree; 41 struct sysctl_oid *sc_sms_tree; 42 struct sysctl_oid *sc_light_tree; 43 struct asmc_model *sc_model; 44 int sc_rid_port; 45 int sc_rid_irq; 46 struct resource *sc_ioport; 47 struct resource *sc_irq; 48 void *sc_cookie; 49 int sc_sms_intrtype; 50 struct taskqueue *sc_sms_tq; 51 struct task sc_sms_task; 52 uint8_t sc_sms_intr_works; 53}; 54 55/* 56 * Data port. 57 */ 58#define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00) 59#define ASMC_DATAPORT_WRITE(sc, val) \ 60 bus_write_1(sc->sc_ioport, 0x00, val) 61#define ASMC_STATUS_MASK 0x0f 62 63/* 64 * Command port. 65 */ 66#define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04) 67#define ASMC_CMDPORT_WRITE(sc, val) \ 68 bus_write_1(sc->sc_ioport, 0x04, val) 69#define ASMC_CMDREAD 0x10 70#define ASMC_CMDWRITE 0x11 71 72/* 73 * Interrupt port. 74 */ 75#define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f) 76 77 78/* Number of keys */ 79#define ASMC_NKEYS "#KEY" /* RO; 4 bytes */ 80 81/* 82 * Fan control via SMC. 83 */ 84#define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */ 85#define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */ 86#define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */ 87#define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */ 88#define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */ 89#define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */ 90#define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */ 91#define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */ 92 93/* 94 * Sudden Motion Sensor (SMS). 95 */ 96#define ASMC_SMS_INIT1 0xe0 97#define ASMC_SMS_INIT2 0xf8 98#define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */ 99#define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */ 100#define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */ 101#define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */ 102#define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */ 103#define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */ 104#define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */ 105#define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */ 106#define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */ 107#define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */ 108#define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */ 109#define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */ 110 111/* 112 * Keyboard backlight. 113 */ 114#define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */ 115#define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */ 116#define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */ 117 118/* 119 * Clamshell. 120 */ 121#define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */ 122 123/* 124 * Interrupt keys. 125 */ 126#define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */ 127 128/* 129 * Temperatures. 130 * 131 * First for MacBook, second for MacBook Pro, third for Intel Mac Mini, 132 * fourth the Mac Pro 8-core and finally the MacBook Air. 133 * 134 */ 135/* maximum array size for temperatures including the last NULL */ 136#define ASMC_TEMP_MAX 80 137#define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \ 138 "TM0P", NULL } 139#define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \ 140 "northbridge2", "heatsink1", \ 141 "heatsink2", "memory", } 142#define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \ 143 "Northbridge Point 1", \ 144 "Northbridge Point 2", "Heatsink 1", \ 145 "Heatsink 2", "Memory Bank A", } 146 147#define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \ 148 "TM0P", NULL } 149 150#define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \ 151 "heatsink1", "heatsink2", \ 152 "memory", } 153 154#define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \ 155 "Northbridge Point 1", \ 156 "Heatsink 1","Heatsink 2" \ 157 "Memory Bank A", } 158 159#define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \ 160 "TG0H", "TG0P", "TG0T", NULL } 161 162#define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \ 163 "heatsink2", "memory", "graphics", \ 164 "graphicssink", "unknown", } 165 166#define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \ 167 "Heatsink 1", "Heatsink 2", \ 168 "Memory Controller", \ 169 "Graphics Chip", "Graphics Heatsink", \ 170 "Unknown", } 171 172#define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \ 173 "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \ 174 "TTF0", "TW0P", NULL } 175 176#define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \ 177 "heatsink3", "memory", "graphicssink", \ 178 "graphics", "cpu", "cpu2", "unknown1", \ 179 "unknown2", "wireless", } 180 181#define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \ 182 "Main Heatsink 1", "Main Heatsink 2", \ 183 "Main Heatsink 3", \ 184 "Memory Controller", \ 185 "Graphics Chip Heatsink", \ 186 "Graphics Chip Diode", \ 187 "CPU Temperature Diode", "CPU Point 2", \ 188 "Unknown", "Unknown", \ 189 "Wireless Module", } 190 191#define ASMC_MBP5_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \ 192 "TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \ 193 "TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \ 194 "TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \ 195 NULL } 196 197#define ASMC_MBP5_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \ 198 "enclosure_bottom_2", "enclosure_bottom_3", \ 199 "cpu_diode", "cpu", \ 200 "cpu_pin", "gpu_diode", \ 201 "gpu", "gpu_heatsink", \ 202 "gpu_pin", "gpu_transistor", \ 203 "gpu_2_heatsink", "northbridge_diode", \ 204 "northbridge_pin", "unknown", \ 205 "heatsink_2", "memory_controller", \ 206 "pci_express_slot_pin", "pci_express_slot_unk" } 207 208#define ASMC_MBP5_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \ 209 "Enclosure Bottom 2", "Enclosure Bottom 3", \ 210 "CPU Diode", "CPU ???", \ 211 "CPU Pin", "GPU Diode", \ 212 "GPU ???", "GPU Heatsink", \ 213 "GPU Pin", "GPU Transistor", \ 214 "GPU 2 Heatsink", "Northbridge Diode", \ 215 "Northbridge Pin", "Unknown", \ 216 "Heatsink 2", "Memory Controller", \ 217 "PCI Express Slot Pin", "PCI Express Slot (unk)" } 218 219#define ASMC_MBP8_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \ 220 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 221 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 222 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 223 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 224 "Th2H", "Tm0P", "Ts0P", "Ts0S", NULL } 225 226#define ASMC_MBP8_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \ 227 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 228 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 229 "TCTD", "graphics", "TG0P", "THSP", "TM0S", \ 230 "TMBS", "TP0P", "TPCD", "wireless", "Th1H", \ 231 "Th2H", "memory", "Ts0P", "Ts0S" } 232 233#define ASMC_MBP8_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \ 234 "TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \ 235 "TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \ 236 "TCTD", "TG0D", "TG0P", "THSP", "TM0S", \ 237 "TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \ 238 "Th2H", "Tm0P", "Ts0P", "Ts0S" } 239 240#define ASMC_MBP11_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 241 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 242 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 243 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 244 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 245 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 246 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 247 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 248 "Ts1S", NULL } 249 250#define ASMC_MBP11_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 251 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 252 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 253 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 254 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 255 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 256 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 257 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 258 "Ts1S" } 259 260#define ASMC_MBP11_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \ 261 "TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \ 262 "TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \ 263 "TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \ 264 "TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \ 265 "TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \ 266 "TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \ 267 "TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \ 268 "Ts1S" } 269 270#define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL } 271#define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" } 272#define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \ 273 "Northbridge Point 2" } 274 275#define ASMC_MM31_TEMPS { "TC0D", "TC0H", \ 276 "TC0P", "TH0P", \ 277 "TN0D", "TN0P", \ 278 "TW0P", NULL } 279 280#define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \ 281 "cpu0_proximity", "hdd_bay", \ 282 "northbridge_die", \ 283 "northbridge_proximity", \ 284 "wireless_module", } 285 286#define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \ 287 "CPU0 Heatsink Temperature", \ 288 "CPU0 Proximity Temperature", \ 289 "HDD Bay Temperature", \ 290 "Northbridge Die Core Temperature", \ 291 "Northbridge Proximity Temperature", \ 292 "Wireless Module Temperature", } 293 294#define ASMC_MP_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 295 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 296 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 297 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 298 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 299 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 300 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \ 301 NULL } 302 303#define ASMC_MP_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 304 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 305 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 306 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 307 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 308 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 309 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 310 311#define ASMC_MP_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \ 312 "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \ 313 "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \ 314 "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \ 315 "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \ 316 "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \ 317 "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", } 318 319#define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 320 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 321 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 322 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 323 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 324 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 325 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 326 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 327 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 328 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 329 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 330 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 331 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 332 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 333 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \ 334 NULL } 335 336#define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \ 337 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 338 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 339 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 340 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 341 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 342 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 343 "TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \ 344 "ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \ 345 "ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \ 346 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 347 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 348 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 349 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 350 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 351 352#define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \ 353 "TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \ 354 "TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \ 355 "TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \ 356 "TH4F", "TH4P", "TH4V", "THPS", "THTG", \ 357 "TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \ 358 "TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \ 359 "TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \ 360 "TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \ 361 "TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \ 362 "TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \ 363 "Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \ 364 "Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \ 365 "Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \ 366 "TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", } 367 368#define ASMC_MBA_TEMPS { "TB0T", NULL } 369#define ASMC_MBA_TEMPNAMES { "enclosure" } 370#define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" } 371 372#define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \ 373 "TC0D", "TC0E", "TC0P", NULL } 374 375#define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \ 376 "TC0D", "TC0E", "TC0P" } 377 378#define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \ 379 "TC0D", "TC0E", "TC0P" } 380 381#define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \ 382 "TC0D", "TC0E", "TC0F", "TC0P", \ 383 "TC1C", "TC2C", "TCGC", "TCSA", \ 384 "TCXC", "THSP", "TM0P", "TPCD", \ 385 "Ta0P", "Th1H", "Tm0P", "Tm1P", \ 386 "Ts0P", "Ts0S", NULL } 387 388#define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \ 389 "cpudiode", "cputemp1", "cputemp2", "cpuproximity", \ 390 "cpucore1", "cpucore2", "cpupeci", "pecisa", \ 391 "TCXC", "THSP", "memorybank", "pchdie", \ 392 "Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \ 393 "palmrest", "memoryproximity" } 394 395#define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\ 396 "CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \ 397 "CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \ 398 "TCXC", "THSP", "Memory Bank A", "PCH Die", \ 399 "Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \ 400 "Palm Rest", "Memory Proximity" } 401