ahareg.h revision 39225
139225Sgibbs/* 239225Sgibbs * Generic register and struct definitions for the Adaptech 154x/164x 339225Sgibbs * SCSI host adapters. Product specific probe and attach routines can 439225Sgibbs * be found in: 539225Sgibbs * <fill in list here> 639225Sgibbs * 739225Sgibbs * Derived from bt.c written by: 839225Sgibbs * 939225Sgibbs * Copyright (c) 1998 Justin T. Gibbs. 1039225Sgibbs * All rights reserved. 1139225Sgibbs * 1239225Sgibbs * Redistribution and use in source and binary forms, with or without 1339225Sgibbs * modification, are permitted provided that the following conditions 1439225Sgibbs * are met: 1539225Sgibbs * 1. Redistributions of source code must retain the above copyright 1639225Sgibbs * notice, this list of conditions, and the following disclaimer, 1739225Sgibbs * without modification, immediately at the beginning of the file. 1839225Sgibbs * 2. The name of the author may not be used to endorse or promote products 1939225Sgibbs * derived from this software without specific prior written permission. 2039225Sgibbs * 2139225Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2239225Sgibbs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2339225Sgibbs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2439225Sgibbs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2539225Sgibbs * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2639225Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2739225Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2839225Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2939225Sgibbs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3039225Sgibbs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3139225Sgibbs * SUCH DAMAGE. 3239225Sgibbs * 3339225Sgibbs * $Id$ 3439225Sgibbs */ 3539225Sgibbs 3639225Sgibbs#ifndef _AHAREG_H_ 3739225Sgibbs#define _AHAREG_H_ 3839225Sgibbs 3939225Sgibbs#include "aha.h" 4039225Sgibbs 4139225Sgibbs#include <sys/queue.h> 4239225Sgibbs#include <cam/scsi/scsi_all.h> 4339225Sgibbs 4439225Sgibbs#define AHA_MAXTRANSFER_SIZE 0xffffff /* limited by 24bit counter */ 4539225Sgibbs#define AHA_NSEG 17 /* The number of dma segments 4639225Sgibbs * supported. */ 4739225Sgibbs#define ALL_TARGETS (~0) 4839225Sgibbs 4939225Sgibbs/* 5039225Sgibbs * Control Register pp. 1-8, 1-9 (Write Only) 5139225Sgibbs */ 5239225Sgibbs#define CONTROL_REG 0x00 5339225Sgibbs#define HARD_RESET 0x80 /* Hard Reset - return to POST state */ 5439225Sgibbs#define SOFT_RESET 0x40 /* Soft Reset - Clears Adapter state */ 5539225Sgibbs#define RESET_INTR 0x20 /* Reset/Ack Interrupt */ 5639225Sgibbs#define RESET_SBUS 0x10 /* Drive SCSI bus reset signal */ 5739225Sgibbs 5839225Sgibbs/* 5939225Sgibbs * Status Register pp. 1-9, 1-10 (Read Only) 6039225Sgibbs */ 6139225Sgibbs#define STATUS_REG 0x00 6239225Sgibbs#define DIAG_ACTIVE 0x80 /* Performing Internal Diags */ 6339225Sgibbs#define DIAG_FAIL 0x40 /* Internal Diags failed */ 6439225Sgibbs#define INIT_REQUIRED 0x20 /* MBOXes need initialization */ 6539225Sgibbs#define HA_READY 0x10 /* HA ready for new commands */ 6639225Sgibbs#define CMD_REG_BUSY 0x08 /* HA busy with last cmd byte */ 6739225Sgibbs#define DATAIN_REG_READY 0x04 /* Data-in Byte available */ 6839225Sgibbs#define STATUS_REG_RSVD 0x02 6939225Sgibbs#define CMD_INVALID 0x01 /* Invalid Command detected */ 7039225Sgibbs 7139225Sgibbs/* 7239225Sgibbs * Command/Parameter Register pp. 1-10, 1-11 (Write Only) 7339225Sgibbs */ 7439225Sgibbs#define COMMAND_REG 0x01 7539225Sgibbs 7639225Sgibbs/* 7739225Sgibbs * Data in Register p. 1-11 (Read Only) 7839225Sgibbs */ 7939225Sgibbs#define DATAIN_REG 0x01 8039225Sgibbs 8139225Sgibbs/* 8239225Sgibbs * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only) 8339225Sgibbs */ 8439225Sgibbs#define INTSTAT_REG 0x02 8539225Sgibbs#define INTR_PENDING 0x80 /* There is a pending INTR */ 8639225Sgibbs#define INTSTAT_REG_RSVD 0x70 8739225Sgibbs#define SCSI_BUS_RESET 0x08 /* Bus Reset detected */ 8839225Sgibbs#define CMD_COMPLETE 0x04 8939225Sgibbs#define OMB_READY 0x02 /* Outgoin Mailbox Ready */ 9039225Sgibbs#define IMB_LOADED 0x01 /* Incoming Mailbox loaded */ 9139225Sgibbs 9239225Sgibbs/* 9339225Sgibbs * Definitions for the "undocumented" geometry register 9439225Sgibbs */ 9539225Sgibbstypedef enum { 9639225Sgibbs GEOM_NODISK, 9739225Sgibbs GEOM_64x32, 9839225Sgibbs GEOM_128x32, 9939225Sgibbs GEOM_255x32 10039225Sgibbs} disk_geom_t; 10139225Sgibbs 10239225Sgibbs#define GEOMETRY_REG 0x03 10339225Sgibbs#define DISK0_GEOMETRY 0x03 10439225Sgibbs#define DISK1_GEOMETRY 0x0c 10539225Sgibbs#define EXTENDED_TRANSLATION 0x10 10639225Sgibbs#define GEOMETRY_DISK0(g_reg) (greg & DISK0_GEOMETRY) 10739225Sgibbs#define GEOMETRY_DISK1(g_reg) ((greg & DISK1_GEOMETRY) >> 2) 10839225Sgibbs 10939225Sgibbs#define AHA_NREGS (4) 11039225Sgibbs 11139225Sgibbs/* 11239225Sgibbs * Opcodes for Adapter commands. 11339225Sgibbs */ 11439225Sgibbstypedef enum { 11539225Sgibbs BOP_NOP = 0x00, 11639225Sgibbs BOP_INITIALIZE_MBOX = 0x01, 11739225Sgibbs BOP_START_MBOX = 0x02, 11839225Sgibbs BOP_EXECUTE_BIOS_CMD = 0x03, 11939225Sgibbs BOP_INQUIRE_BOARD_ID = 0x04, 12039225Sgibbs BOP_ENABLE_OMBR_INT = 0x05, 12139225Sgibbs BOP_SET_SEL_TIMOUT = 0x06, 12239225Sgibbs BOP_SET_TIME_ON_BUS = 0x07, 12339225Sgibbs BOP_SET_TIME_OFF_BUS = 0x08, 12439225Sgibbs BOP_SET_BUS_TRANS_RATE = 0x09, 12539225Sgibbs BOP_INQUIRE_INST_LDEVS = 0x0A, 12639225Sgibbs BOP_INQUIRE_CONFIG = 0x0B, 12739225Sgibbs BOP_ENABLE_TARGET_MODE = 0x0C, 12839225Sgibbs BOP_INQUIRE_SETUP_INFO = 0x0D, 12939225Sgibbs BOP_WRITE_LRAM = 0x1A, 13039225Sgibbs BOP_READ_LRAM = 0x1B, 13139225Sgibbs BOP_WRITE_CHIP_FIFO = 0x1C, 13239225Sgibbs BOP_READ_CHIP_FIFO = 0x1D, 13339225Sgibbs BOP_ECHO_DATA_BYTE = 0x1F, 13439225Sgibbs BOP_ADAPTER_DIAGNOSTICS = 0x20, 13539225Sgibbs BOP_SET_ADAPTER_OPTIONS = 0x21, 13639225Sgibbs BOP_SET_EEPROM = 0x22, 13739225Sgibbs BOP_RETURN_EEPROM = 0x23, 13839225Sgibbs BOP_ENABLE_SHADOW_RAM = 0x24, 13939225Sgibbs BOP_INIT_BIOS_MBOX = 0x25, 14039225Sgibbs BOP_SET_BIOS_BANK_1 = 0x26, 14139225Sgibbs BOP_SET_BIOS_BANK_2 = 0x27, 14239225Sgibbs BOP_RETURN_EXT_BIOS_INFO= 0x28, 14339225Sgibbs BOP_MBOX_IF_ENABLE = 0x29, 14439225Sgibbs BOP_SCSI_TERM_STATUS = 0x2C, 14539225Sgibbs BOP_INQUIRE_SCAM_DEV = 0x2D, 14639225Sgibbs BOP_SCSI_DEV_TABLE = 0x2E, 14739225Sgibbs BOP_SCAM_OP = 0x2F, 14839225Sgibbs BOP_START_BIOS_CMD = 0x82, 14939225Sgibbs BOP_INQUIRE_ESETUP_INFO = 0x8D 15039225Sgibbs} aha_op_t; 15139225Sgibbs 15239225Sgibbs/************** Definitions of Multi-byte commands and responses ************/ 15339225Sgibbs 15439225Sgibbsstruct aha_extbios 15539225Sgibbs{ 15639225Sgibbs u_int8_t flags; /* Bit 3 == 1 extended bios enabled */ 15739225Sgibbs u_int8_t mailboxlock; /* mail box lock code to unlock it */ 15839225Sgibbs}; 15939225Sgibbs 16039225Sgibbs/* This is really a bustech command, but we use it to differentiate between */ 16139225Sgibbs/* the aha and bt */ 16239225Sgibbstypedef struct { 16339225Sgibbs u_int8_t bus_type; 16439225Sgibbs u_int8_t bios_addr; 16539225Sgibbs u_int16_t max_sg; 16639225Sgibbs u_int8_t num_mboxes; 16739225Sgibbs u_int8_t mbox_base[4]; 16839225Sgibbs u_int8_t :2, 16939225Sgibbs sync_neg10MB :1, 17039225Sgibbs floppy_disable :1, 17139225Sgibbs floppy_secondary_port :1, 17239225Sgibbs burst_mode_enabled :1, 17339225Sgibbs level_trigger_ints :1, 17439225Sgibbs :1; 17539225Sgibbs u_int8_t fw_ver_bytes_2_to_4[3]; 17639225Sgibbs u_int8_t wide_bus :1, 17739225Sgibbs diff_bus :1, 17839225Sgibbs scam_capable :1, 17939225Sgibbs ultra_scsi :1, 18039225Sgibbs auto_term :1, 18139225Sgibbs :3; 18239225Sgibbs} esetup_info_data_t; 18339225Sgibbs 18439225Sgibbstypedef struct { 18539225Sgibbs u_int8_t num_mboxes; 18639225Sgibbs u_int8_t base_addr[3]; 18739225Sgibbs} init_24b_mbox_params_t; 18839225Sgibbs 18939225Sgibbstypedef struct { 19039225Sgibbs u_int8_t board_type; 19139225Sgibbs/* These values are mostly from the aha-1540CP technical reference, but */ 19239225Sgibbs/* with other values from the old aha1542.c driver. */ 19339225Sgibbs#define BOARD_1540_16HEAD_BIOS 0x00 19439225Sgibbs#define BOARD_1540_64HEAD_BIOS 0x30 19539225Sgibbs#define BOARD_1542 0x41 /* aha-1540/1542 w/64-h bios */ 19639225Sgibbs#define BOARD_1640 0x42 /* aha-1640 */ 19739225Sgibbs#define BOARD_1740 0x43 /* aha-1740A/1742A/1744 */ 19839225Sgibbs#define BOARD_1542C 0x44 /* aha-1542C */ 19939225Sgibbs#define BOARD_1542CF 0x45 /* aha-1542CF */ 20039225Sgibbs#define BOARD_1542CP 0x46 /* aha-1542CP, plug and play */ 20139225Sgibbs u_int8_t cust_features; 20239225Sgibbs#define FEATURES_STANDARD 0x30 20339225Sgibbs u_int8_t firmware_rev_major; 20439225Sgibbs u_int8_t firmware_rev_minor; 20539225Sgibbs} board_id_data_t; 20639225Sgibbs 20739225Sgibbstypedef struct { 20839225Sgibbs u_int8_t dma_chan; 20939225Sgibbs#define DMA_CHAN_5 0x20 21039225Sgibbs#define DMA_CHAN_6 0x40 21139225Sgibbs#define DMA_CHAN_7 0x80 21239225Sgibbs u_int8_t irq; 21339225Sgibbs#define IRQ_9 0x01 21439225Sgibbs#define IRQ_10 0x02 21539225Sgibbs#define IRQ_11 0x04 21639225Sgibbs#define IRQ_12 0x08 21739225Sgibbs#define IRQ_14 0x20 21839225Sgibbs#define IRQ_15 0x40 21939225Sgibbs u_int8_t scsi_id; 22039225Sgibbs} config_data_t; 22139225Sgibbs 22239225Sgibbstypedef struct { 22339225Sgibbs u_int8_t enable; 22439225Sgibbs} target_mode_params_t; 22539225Sgibbs 22639225Sgibbstypedef struct { 22739225Sgibbs u_int8_t offset : 4, 22839225Sgibbs period : 3, 22939225Sgibbs sync : 1; 23039225Sgibbs} targ_syncinfo_t; 23139225Sgibbs 23239225Sgibbstypedef struct { 23339225Sgibbs u_int8_t initiate_sync : 1, 23439225Sgibbs parity_enable : 1, 23539225Sgibbs : 6; 23639225Sgibbs 23739225Sgibbs u_int8_t bus_transfer_rate; 23839225Sgibbs u_int8_t time_on_bus; 23939225Sgibbs u_int8_t time_off_bus; 24039225Sgibbs u_int8_t num_mboxes; 24139225Sgibbs u_int8_t mbox_base_addr[3]; 24239225Sgibbs targ_syncinfo_t syncinfo[8]; 24339225Sgibbs u_int8_t discinfo; 24439225Sgibbs u_int8_t customer_sig[20]; 24539225Sgibbs u_int8_t auto_retry; 24639225Sgibbs u_int8_t board_switches; 24739225Sgibbs u_int8_t firmware_cksum[2]; 24839225Sgibbs u_int8_t bios_mbox_addr[3]; 24939225Sgibbs} setup_data_t; 25039225Sgibbs 25139225Sgibbsstruct aha_isa_port { 25239225Sgibbs u_int16_t addr; 25339225Sgibbs u_int8_t probed; 25439225Sgibbs}; 25539225Sgibbs 25639225Sgibbsextern struct aha_isa_port aha_isa_ports[]; 25739225Sgibbs 25839225Sgibbs#define AHA_NUM_ISAPORTS 6 25939225Sgibbs 26039225Sgibbstypedef enum { 26139225Sgibbs BIO_330 = 0, 26239225Sgibbs BIO_334 = 1, 26339225Sgibbs BIO_230 = 2, 26439225Sgibbs BIO_234 = 3, 26539225Sgibbs BIO_130 = 4, 26639225Sgibbs BIO_134 = 5, 26739225Sgibbs BIO_DISABLED = 6, 26839225Sgibbs BIO_DISABLED2 = 7 26939225Sgibbs} isa_compat_io_t; 27039225Sgibbs 27139225Sgibbstypedef struct { 27239225Sgibbs u_int8_t sync_rate[16]; /* Sync in 10ns units */ 27339225Sgibbs} target_sync_info_data_t; 27439225Sgibbs 27539225Sgibbstypedef struct { 27639225Sgibbs u_int8_t len[3]; 27739225Sgibbs u_int8_t addr[3]; 27839225Sgibbs} aha_sg_t; 27939225Sgibbs 28039225Sgibbs/********************** Mail Box definitions *******************************/ 28139225Sgibbs 28239225Sgibbstypedef enum { 28339225Sgibbs BMBO_FREE = 0x0, /* MBO intry is free */ 28439225Sgibbs BMBO_START = 0x1, /* MBO activate entry */ 28539225Sgibbs BMBO_ABORT = 0x2 /* MBO abort entry */ 28639225Sgibbs} aha_mbo_action_code_t; 28739225Sgibbs 28839225Sgibbstypedef struct aha_mbox_out { 28939225Sgibbs u_int8_t action_code; 29039225Sgibbs u_int8_t ccb_addr[3]; 29139225Sgibbs} aha_mbox_out_t; 29239225Sgibbs 29339225Sgibbstypedef enum { 29439225Sgibbs BMBI_FREE = 0x0, /* MBI entry is free */ 29539225Sgibbs BMBI_OK = 0x1, /* completed without error */ 29639225Sgibbs BMBI_ABORT = 0x2, /* aborted ccb */ 29739225Sgibbs BMBI_NOT_FOUND = 0x3, /* Tried to abort invalid CCB */ 29839225Sgibbs BMBI_ERROR = 0x4 /* Completed with error */ 29939225Sgibbs} aha_mbi_comp_code_t; 30039225Sgibbs 30139225Sgibbstypedef struct aha_mbox_in { 30239225Sgibbs u_int8_t comp_code; 30339225Sgibbs u_int8_t ccb_addr[3]; 30439225Sgibbs} aha_mbox_in_t; 30539225Sgibbs 30639225Sgibbs/****************** Hardware CCB definition *********************************/ 30739225Sgibbstypedef enum { 30839225Sgibbs INITIATOR_CCB = 0x00, 30939225Sgibbs INITIATOR_SG_CCB = 0x02, 31039225Sgibbs INITIATOR_CCB_WRESID = 0x03, 31139225Sgibbs INITIATOR_SG_CCB_WRESID = 0x04, 31239225Sgibbs INITIATOR_BUS_DEV_RESET = 0x81 31339225Sgibbs} aha_ccb_opcode_t; 31439225Sgibbs 31539225Sgibbstypedef enum { 31639225Sgibbs AHASTAT_NOERROR = 0x00, 31739225Sgibbs AHASTAT_SELTIMEOUT = 0x11, 31839225Sgibbs AHASTAT_DATARUN_ERROR = 0x12, 31939225Sgibbs AHASTAT_UNEXPECTED_BUSFREE = 0x13, 32039225Sgibbs AHASTAT_INVALID_PHASE = 0x14, 32139225Sgibbs AHASTAT_INVALID_ACTION_CODE = 0x15, 32239225Sgibbs AHASTAT_INVALID_OPCODE = 0x16, 32339225Sgibbs AHASTAT_LINKED_CCB_LUN_MISMATCH = 0x17, 32439225Sgibbs AHASTAT_INVALID_CCB_OR_SG_PARAM = 0x1A, 32539225Sgibbs AHASTAT_HA_SCSI_BUS_RESET = 0x22, /* stolen from bt */ 32639225Sgibbs AHASTAT_HA_BDR = 0x25 /* Stolen from bt */ 32739225Sgibbs} ahastat_t; 32839225Sgibbs 32939225Sgibbsstruct aha_hccb { 33039225Sgibbs u_int8_t opcode; /* 0 */ 33139225Sgibbs u_int8_t lun : 3, /* 1 */ 33239225Sgibbs datain : 1, 33339225Sgibbs dataout : 1, 33439225Sgibbs target : 3; 33539225Sgibbs u_int8_t cmd_len; /* 2 */ 33639225Sgibbs u_int8_t sense_len; /* 3 */ 33739225Sgibbs u_int8_t data_len[3]; /* 4 */ 33839225Sgibbs u_int8_t data_addr[3]; /* 7 */ 33939225Sgibbs u_int8_t link_ptr[3]; /* 10 */ 34039225Sgibbs u_int8_t link_id; /* 13 */ 34139225Sgibbs u_int8_t ahastat; /* 14 */ 34239225Sgibbs u_int8_t sdstat; /* 15 */ 34339225Sgibbs u_int8_t reserved1; /* 16 */ 34439225Sgibbs u_int8_t reserved2; /* 17 */ 34539225Sgibbs u_int8_t scsi_cdb[16]; /* 18 */ 34639225Sgibbs u_int8_t sense_data[SSD_FULL_SIZE]; 34739225Sgibbs}; 34839225Sgibbs 34939225Sgibbstypedef enum { 35039225Sgibbs BCCB_FREE = 0x0, 35139225Sgibbs BCCB_ACTIVE = 0x1, 35239225Sgibbs BCCB_DEVICE_RESET = 0x2, 35339225Sgibbs BCCB_RELEASE_SIMQ = 0x4 35439225Sgibbs} bccb_flags_t; 35539225Sgibbs 35639225Sgibbsstruct aha_ccb { 35739225Sgibbs struct aha_hccb hccb; /* hccb assumed to be at 0 */ 35839225Sgibbs SLIST_ENTRY(aha_ccb) links; 35939225Sgibbs u_int32_t flags; 36039225Sgibbs union ccb *ccb; 36139225Sgibbs bus_dmamap_t dmamap; 36239225Sgibbs aha_sg_t *sg_list; 36339225Sgibbs u_int32_t sg_list_phys; 36439225Sgibbs}; 36539225Sgibbs 36639225Sgibbsstruct sg_map_node { 36739225Sgibbs bus_dmamap_t sg_dmamap; 36839225Sgibbs bus_addr_t sg_physaddr; 36939225Sgibbs aha_sg_t* sg_vaddr; 37039225Sgibbs SLIST_ENTRY(sg_map_node) links; 37139225Sgibbs}; 37239225Sgibbs 37339225Sgibbsstruct aha_softc { 37439225Sgibbs bus_space_tag_t tag; 37539225Sgibbs bus_space_handle_t bsh; 37639225Sgibbs struct cam_sim *sim; 37739225Sgibbs struct cam_path *path; 37839225Sgibbs aha_mbox_out_t *cur_outbox; 37939225Sgibbs aha_mbox_in_t *cur_inbox; 38039225Sgibbs aha_mbox_out_t *last_outbox; 38139225Sgibbs aha_mbox_in_t *last_inbox; 38239225Sgibbs struct aha_ccb *aha_ccb_array; 38339225Sgibbs SLIST_HEAD(,aha_ccb) free_aha_ccbs; 38439225Sgibbs LIST_HEAD(,ccb_hdr) pending_ccbs; 38539225Sgibbs u_int32_t aha_ccb_physbase; 38639225Sgibbs aha_mbox_in_t *in_boxes; 38739225Sgibbs aha_mbox_out_t *out_boxes; 38839225Sgibbs struct scsi_sense_data *sense_buffers; 38939225Sgibbs u_int32_t sense_buffers_physbase; 39039225Sgibbs struct aha_ccb *recovery_bccb; 39139225Sgibbs u_int num_boxes; 39239225Sgibbs bus_dma_tag_t parent_dmat; /* 39339225Sgibbs * All dmat's derive from 39439225Sgibbs * the dmat defined by our 39539225Sgibbs * bus. 39639225Sgibbs */ 39739225Sgibbs bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 39839225Sgibbs bus_dma_tag_t mailbox_dmat; /* dmat for our mailboxes */ 39939225Sgibbs bus_dmamap_t mailbox_dmamap; 40039225Sgibbs bus_dma_tag_t ccb_dmat; /* dmat for our ccb array */ 40139225Sgibbs bus_dmamap_t ccb_dmamap; 40239225Sgibbs bus_dma_tag_t sg_dmat; /* dmat for our sg maps */ 40339225Sgibbs SLIST_HEAD(, sg_map_node) sg_maps; 40439225Sgibbs bus_addr_t mailbox_physbase; 40539225Sgibbs u_int num_ccbs; /* Number of CCBs malloc'd */ 40639225Sgibbs u_int max_ccbs; /* Maximum allocatable CCBs */ 40739225Sgibbs u_int max_sg; 40839225Sgibbs u_int unit; 40939225Sgibbs u_int scsi_id; 41039225Sgibbs u_int32_t extended_trans :1, 41139225Sgibbs wide_bus :1, 41239225Sgibbs diff_bus :1, 41339225Sgibbs ultra_scsi :1, 41439225Sgibbs extended_lun :1, 41539225Sgibbs strict_rr :1, 41639225Sgibbs tag_capable :1, 41739225Sgibbs wide_lun_ccb :1, 41839225Sgibbs resource_shortage:1, 41939225Sgibbs :23; 42039225Sgibbs u_int16_t tags_permitted; 42139225Sgibbs u_int16_t disc_permitted; 42239225Sgibbs u_int16_t sync_permitted; 42339225Sgibbs u_int16_t fast_permitted; 42439225Sgibbs u_int16_t ultra_permitted; 42539225Sgibbs u_int16_t wide_permitted; 42639225Sgibbs u_int8_t init_level; 42739225Sgibbs volatile u_int8_t command_cmp; 42839225Sgibbs volatile u_int8_t latched_status; 42939225Sgibbs u_int32_t bios_addr; 43039225Sgibbs char firmware_ver[6]; 43139225Sgibbs char model[32]; 43239225Sgibbs u_int8_t boardid; 43339225Sgibbs}; 43439225Sgibbs 43539225Sgibbsextern struct aha_softc *aha_softcs[]; /* XXX Config should handle this */ 43639225Sgibbsextern u_long aha_unit; 43739225Sgibbs 43839225Sgibbs#define AHA_TEMP_UNIT 0xFF /* Unit for probes */ 43939225Sgibbsstruct aha_softc* aha_alloc(int unit, bus_space_tag_t tag, 44039225Sgibbs bus_space_handle_t bsh); 44139225Sgibbsvoid aha_free(struct aha_softc *aha); 44239225Sgibbsint aha_probe(struct aha_softc *aha); 44339225Sgibbsint aha_fetch_adapter_info(struct aha_softc *aha); 44439225Sgibbsint aha_init(struct aha_softc *aha); 44539225Sgibbsint aha_attach(struct aha_softc *aha); 44639225Sgibbsvoid aha_intr(void *arg); 44739225Sgibbschar * aha_name(struct aha_softc *aha); 44839225Sgibbsint aha_check_probed_iop(u_int ioport); 44939225Sgibbsvoid aha_mark_probed_bio(isa_compat_io_t port); 45039225Sgibbsvoid aha_mark_probed_iop(u_int ioport); 45139225Sgibbs 45239225Sgibbs#define DEFAULT_CMD_TIMEOUT 10000 /* 1 sec */ 45339225Sgibbsint aha_cmd(struct aha_softc *aha, aha_op_t opcode, 45439225Sgibbs u_int8_t *params, u_int param_len, 45539225Sgibbs u_int8_t *reply_data, u_int reply_len, 45639225Sgibbs u_int cmd_timeout); 45739225Sgibbs 45839225Sgibbs#define aha_inb(aha, port) \ 45939225Sgibbs bus_space_read_1((aha)->tag, (aha)->bsh, port) 46039225Sgibbs 46139225Sgibbs#define aha_outb(aha, port, value) \ 46239225Sgibbs bus_space_write_1((aha)->tag, (aha)->bsh, port, value) 46339225Sgibbs 46439225Sgibbs#endif /* _AHA_H_ */ 465