1139749Simp/*- 2122359Simp * Generic register and struct definitions for the Adaptech 1540, 1542, 3122359Simp * 1640, 1642 SCSI host adapters. Product specific probe and attach 4122359Simp * routines can be found in: 5122359Simp * aha_isa.c, aha_mca.c 639225Sgibbs * 739225Sgibbs * Derived from bt.c written by: 839225Sgibbs * 939225Sgibbs * Copyright (c) 1998 Justin T. Gibbs. 1039225Sgibbs * All rights reserved. 1139225Sgibbs * 1239225Sgibbs * Redistribution and use in source and binary forms, with or without 1339225Sgibbs * modification, are permitted provided that the following conditions 1439225Sgibbs * are met: 1539225Sgibbs * 1. Redistributions of source code must retain the above copyright 1639225Sgibbs * notice, this list of conditions, and the following disclaimer, 1739225Sgibbs * without modification, immediately at the beginning of the file. 1839225Sgibbs * 2. The name of the author may not be used to endorse or promote products 1939225Sgibbs * derived from this software without specific prior written permission. 2039225Sgibbs * 2139225Sgibbs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2239225Sgibbs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2339225Sgibbs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2439225Sgibbs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 2539225Sgibbs * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2639225Sgibbs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2739225Sgibbs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2839225Sgibbs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2939225Sgibbs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3039225Sgibbs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3139225Sgibbs * SUCH DAMAGE. 3239225Sgibbs * 3350477Speter * $FreeBSD: releng/11.0/sys/dev/aha/ahareg.h 241603 2012-10-16 08:40:09Z glebius $ 3439225Sgibbs */ 3539225Sgibbs 3639225Sgibbs#ifndef _AHAREG_H_ 3739225Sgibbs#define _AHAREG_H_ 3839225Sgibbs 3939225Sgibbs#include <sys/queue.h> 4039225Sgibbs#include <cam/scsi/scsi_all.h> 4139225Sgibbs 4239225Sgibbs#define AHA_MAXTRANSFER_SIZE 0xffffff /* limited by 24bit counter */ 4339225Sgibbs#define AHA_NSEG 17 /* The number of dma segments 4439225Sgibbs * supported. */ 4539225Sgibbs#define ALL_TARGETS (~0) 4639225Sgibbs 4739225Sgibbs/* 4839225Sgibbs * Control Register pp. 1-8, 1-9 (Write Only) 4939225Sgibbs */ 5039225Sgibbs#define CONTROL_REG 0x00 5139225Sgibbs#define HARD_RESET 0x80 /* Hard Reset - return to POST state */ 5239225Sgibbs#define SOFT_RESET 0x40 /* Soft Reset - Clears Adapter state */ 5339225Sgibbs#define RESET_INTR 0x20 /* Reset/Ack Interrupt */ 5439225Sgibbs#define RESET_SBUS 0x10 /* Drive SCSI bus reset signal */ 5539225Sgibbs 5639225Sgibbs/* 5739225Sgibbs * Status Register pp. 1-9, 1-10 (Read Only) 5839225Sgibbs */ 5939225Sgibbs#define STATUS_REG 0x00 6039225Sgibbs#define DIAG_ACTIVE 0x80 /* Performing Internal Diags */ 6139225Sgibbs#define DIAG_FAIL 0x40 /* Internal Diags failed */ 6239225Sgibbs#define INIT_REQUIRED 0x20 /* MBOXes need initialization */ 6339225Sgibbs#define HA_READY 0x10 /* HA ready for new commands */ 6439225Sgibbs#define CMD_REG_BUSY 0x08 /* HA busy with last cmd byte */ 6539225Sgibbs#define DATAIN_REG_READY 0x04 /* Data-in Byte available */ 6639225Sgibbs#define STATUS_REG_RSVD 0x02 6739225Sgibbs#define CMD_INVALID 0x01 /* Invalid Command detected */ 6839225Sgibbs 6939225Sgibbs/* 7039225Sgibbs * Command/Parameter Register pp. 1-10, 1-11 (Write Only) 7139225Sgibbs */ 7239225Sgibbs#define COMMAND_REG 0x01 7339225Sgibbs 7439225Sgibbs/* 7539225Sgibbs * Data in Register p. 1-11 (Read Only) 7639225Sgibbs */ 7739225Sgibbs#define DATAIN_REG 0x01 7839225Sgibbs 7939225Sgibbs/* 8039225Sgibbs * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only) 8139225Sgibbs */ 8239225Sgibbs#define INTSTAT_REG 0x02 8339225Sgibbs#define INTR_PENDING 0x80 /* There is a pending INTR */ 8439225Sgibbs#define INTSTAT_REG_RSVD 0x70 8539225Sgibbs#define SCSI_BUS_RESET 0x08 /* Bus Reset detected */ 8639225Sgibbs#define CMD_COMPLETE 0x04 8739225Sgibbs#define OMB_READY 0x02 /* Outgoin Mailbox Ready */ 8839225Sgibbs#define IMB_LOADED 0x01 /* Incoming Mailbox loaded */ 8939225Sgibbs 9039225Sgibbs/* 9139881Simp * Definitions for the "undocumented" geometry register, we just need 9239881Simp * its location. 9339225Sgibbs */ 9439225Sgibbs#define GEOMETRY_REG 0x03 9539225Sgibbs 9639225Sgibbs#define AHA_NREGS (4) 9739225Sgibbs 9839225Sgibbs/* 9939225Sgibbs * Opcodes for Adapter commands. 10039225Sgibbs */ 10139225Sgibbstypedef enum { 10241047Sgibbs AOP_NOP = 0x00, 10341047Sgibbs AOP_INITIALIZE_MBOX = 0x01, 10441047Sgibbs AOP_START_MBOX = 0x02, 10541047Sgibbs AOP_EXECUTE_BIOS_CMD = 0x03, 10641047Sgibbs AOP_INQUIRE_BOARD_ID = 0x04, 10741047Sgibbs AOP_ENABLE_OMBR_INT = 0x05, 10841047Sgibbs AOP_SET_SEL_TIMOUT = 0x06, 10941047Sgibbs AOP_SET_TIME_ON_BUS = 0x07, 11041047Sgibbs AOP_SET_TIME_OFF_BUS = 0x08, 11141047Sgibbs AOP_SET_BUS_TRANS_RATE = 0x09, 11241047Sgibbs AOP_INQUIRE_INST_LDEVS = 0x0A, 11341047Sgibbs AOP_INQUIRE_CONFIG = 0x0B, 11441047Sgibbs AOP_ENABLE_TARGET_MODE = 0x0C, 11541047Sgibbs AOP_INQUIRE_SETUP_INFO = 0x0D, 11641047Sgibbs AOP_WRITE_LRAM = 0x1A, 11741047Sgibbs AOP_READ_LRAM = 0x1B, 11841047Sgibbs AOP_WRITE_CHIP_FIFO = 0x1C, 11941047Sgibbs AOP_READ_CHIP_FIFO = 0x1D, 12041047Sgibbs AOP_ECHO_DATA_BYTE = 0x1F, 12141047Sgibbs AOP_ADAPTER_DIAGNOSTICS = 0x20, 12241047Sgibbs AOP_SET_ADAPTER_OPTIONS = 0x21, 12341047Sgibbs AOP_SET_EEPROM = 0x22, 12441047Sgibbs AOP_RETURN_EEPROM = 0x23, 12541047Sgibbs AOP_ENABLE_SHADOW_RAM = 0x24, 12641047Sgibbs AOP_INIT_BIOS_MBOX = 0x25, 12741047Sgibbs AOP_SET_BIOS_BANK_1 = 0x26, 12841047Sgibbs AOP_SET_BIOS_BANK_2 = 0x27, 12941047Sgibbs AOP_RETURN_EXT_BIOS_INFO= 0x28, 13041047Sgibbs AOP_MBOX_IF_ENABLE = 0x29, 13141047Sgibbs AOP_SCSI_TERM_STATUS = 0x2C, 13241047Sgibbs AOP_INQUIRE_SCAM_DEV = 0x2D, 13341047Sgibbs AOP_SCSI_DEV_TABLE = 0x2E, 13441047Sgibbs AOP_SCAM_OP = 0x2F, 13541047Sgibbs AOP_START_BIOS_CMD = 0x82, 13641047Sgibbs AOP_INQUIRE_ESETUP_INFO = 0x8D 13739225Sgibbs} aha_op_t; 13839225Sgibbs 13939225Sgibbs/************** Definitions of Multi-byte commands and responses ************/ 14039225Sgibbs 14139225Sgibbsstruct aha_extbios 14239225Sgibbs{ 143122340Simp uint8_t flags; /* Bit 3 == 1 extended bios enabled */ 144122340Simp uint8_t mailboxlock; /* mail box lock code to unlock it */ 14539225Sgibbs}; 14639225Sgibbs 14739225Sgibbstypedef struct { 148122340Simp uint8_t num_mboxes; 149122340Simp uint8_t base_addr[3]; 15039225Sgibbs} init_24b_mbox_params_t; 15139225Sgibbs 15239225Sgibbstypedef struct { 153122340Simp uint8_t board_type; 15439225Sgibbs/* These values are mostly from the aha-1540CP technical reference, but */ 15539881Simp/* with other values from the old aha1542.c driver. The values from the */ 15639881Simp/* aha-1540CP technical manual are used where conflicts arise */ 15739225Sgibbs#define BOARD_1540_16HEAD_BIOS 0x00 15839225Sgibbs#define BOARD_1540_64HEAD_BIOS 0x30 15939225Sgibbs#define BOARD_1542 0x41 /* aha-1540/1542 w/64-h bios */ 16039225Sgibbs#define BOARD_1640 0x42 /* aha-1640 */ 16139225Sgibbs#define BOARD_1740 0x43 /* aha-1740A/1742A/1744 */ 16239225Sgibbs#define BOARD_1542C 0x44 /* aha-1542C */ 16339225Sgibbs#define BOARD_1542CF 0x45 /* aha-1542CF */ 16439225Sgibbs#define BOARD_1542CP 0x46 /* aha-1542CP, plug and play */ 165122340Simp uint8_t cust_features; 16639225Sgibbs#define FEATURES_STANDARD 0x30 167122340Simp uint8_t firmware_rev_major; 168122340Simp uint8_t firmware_rev_minor; 16939225Sgibbs} board_id_data_t; 17039225Sgibbs 17139225Sgibbstypedef struct { 172122340Simp uint8_t dma_chan; 17339225Sgibbs#define DMA_CHAN_5 0x20 17439225Sgibbs#define DMA_CHAN_6 0x40 17539225Sgibbs#define DMA_CHAN_7 0x80 176122340Simp uint8_t irq; 17739225Sgibbs#define IRQ_9 0x01 17839225Sgibbs#define IRQ_10 0x02 17939225Sgibbs#define IRQ_11 0x04 18039225Sgibbs#define IRQ_12 0x08 18139225Sgibbs#define IRQ_14 0x20 18239225Sgibbs#define IRQ_15 0x40 183122340Simp uint8_t scsi_id; 18439225Sgibbs} config_data_t; 18539225Sgibbs 18639225Sgibbstypedef struct { 187122340Simp uint8_t offset : 4, 18839225Sgibbs period : 3, 18939225Sgibbs sync : 1; 19039225Sgibbs} targ_syncinfo_t; 19139225Sgibbs 19239225Sgibbstypedef struct { 193122340Simp uint8_t initiate_sync : 1, 19439225Sgibbs parity_enable : 1, 19539225Sgibbs : 6; 19639225Sgibbs 197122340Simp uint8_t bus_transfer_rate; 198122340Simp uint8_t time_on_bus; 199122340Simp uint8_t time_off_bus; 200122340Simp uint8_t num_mboxes; 201122340Simp uint8_t mbox_base_addr[3]; 20239225Sgibbs targ_syncinfo_t syncinfo[8]; 203122340Simp uint8_t discinfo; 204122340Simp uint8_t customer_sig[20]; 205122340Simp uint8_t auto_retry; 206122340Simp uint8_t board_switches; 207122340Simp uint8_t firmware_cksum[2]; 208122340Simp uint8_t bios_mbox_addr[3]; 20939225Sgibbs} setup_data_t; 21039225Sgibbs 21139225Sgibbs#define AHA_NUM_ISAPORTS 6 21239225Sgibbs 21339225Sgibbstypedef struct { 214122340Simp uint8_t len[3]; 215122340Simp uint8_t addr[3]; 21639225Sgibbs} aha_sg_t; 21739225Sgibbs 21839225Sgibbs/********************** Mail Box definitions *******************************/ 21939225Sgibbs 22039225Sgibbstypedef enum { 22141047Sgibbs AMBO_FREE = 0x0, /* MBO intry is free */ 22241047Sgibbs AMBO_START = 0x1, /* MBO activate entry */ 22341047Sgibbs AMBO_ABORT = 0x2 /* MBO abort entry */ 22439225Sgibbs} aha_mbo_action_code_t; 22539225Sgibbs 22639225Sgibbstypedef struct aha_mbox_out { 227122340Simp uint8_t action_code; 228122340Simp uint8_t ccb_addr[3]; 22939225Sgibbs} aha_mbox_out_t; 23039225Sgibbs 23139225Sgibbstypedef enum { 23241047Sgibbs AMBI_FREE = 0x0, /* MBI entry is free */ 23341047Sgibbs AMBI_OK = 0x1, /* completed without error */ 23441047Sgibbs AMBI_ABORT = 0x2, /* aborted ccb */ 23541047Sgibbs AMBI_NOT_FOUND = 0x3, /* Tried to abort invalid CCB */ 23641047Sgibbs AMBI_ERROR = 0x4 /* Completed with error */ 23739225Sgibbs} aha_mbi_comp_code_t; 23839225Sgibbs 23939225Sgibbstypedef struct aha_mbox_in { 240122340Simp uint8_t comp_code; 241122340Simp uint8_t ccb_addr[3]; 24239225Sgibbs} aha_mbox_in_t; 24339225Sgibbs 24439225Sgibbs/****************** Hardware CCB definition *********************************/ 24539225Sgibbstypedef enum { 24639225Sgibbs INITIATOR_CCB = 0x00, 24739225Sgibbs INITIATOR_SG_CCB = 0x02, 24839225Sgibbs INITIATOR_CCB_WRESID = 0x03, 24939225Sgibbs INITIATOR_SG_CCB_WRESID = 0x04, 25039225Sgibbs INITIATOR_BUS_DEV_RESET = 0x81 25139225Sgibbs} aha_ccb_opcode_t; 25239225Sgibbs 25339225Sgibbstypedef enum { 25439225Sgibbs AHASTAT_NOERROR = 0x00, 25539225Sgibbs AHASTAT_SELTIMEOUT = 0x11, 25639225Sgibbs AHASTAT_DATARUN_ERROR = 0x12, 25739225Sgibbs AHASTAT_UNEXPECTED_BUSFREE = 0x13, 25839225Sgibbs AHASTAT_INVALID_PHASE = 0x14, 25939225Sgibbs AHASTAT_INVALID_ACTION_CODE = 0x15, 26039225Sgibbs AHASTAT_INVALID_OPCODE = 0x16, 26139225Sgibbs AHASTAT_LINKED_CCB_LUN_MISMATCH = 0x17, 26239225Sgibbs AHASTAT_INVALID_CCB_OR_SG_PARAM = 0x1A, 26339225Sgibbs AHASTAT_HA_SCSI_BUS_RESET = 0x22, /* stolen from bt */ 26439225Sgibbs AHASTAT_HA_BDR = 0x25 /* Stolen from bt */ 26539225Sgibbs} ahastat_t; 26639225Sgibbs 26739225Sgibbsstruct aha_hccb { 268122340Simp uint8_t opcode; /* 0 */ 269122340Simp uint8_t lun : 3, /* 1 */ 27039225Sgibbs datain : 1, 27139225Sgibbs dataout : 1, 27239225Sgibbs target : 3; 273122340Simp uint8_t cmd_len; /* 2 */ 274122340Simp uint8_t sense_len; /* 3 */ 275122340Simp uint8_t data_len[3]; /* 4 */ 276122340Simp uint8_t data_addr[3]; /* 7 */ 277122340Simp uint8_t link_ptr[3]; /* 10 */ 278122340Simp uint8_t link_id; /* 13 */ 279122340Simp uint8_t ahastat; /* 14 */ 280122340Simp uint8_t sdstat; /* 15 */ 281122340Simp uint8_t reserved1; /* 16 */ 282122340Simp uint8_t reserved2; /* 17 */ 283122340Simp uint8_t scsi_cdb[16]; /* 18 */ 284122340Simp uint8_t sense_data[SSD_FULL_SIZE]; 28539225Sgibbs}; 28639225Sgibbs 28739225Sgibbstypedef enum { 28841047Sgibbs ACCB_FREE = 0x0, 28941047Sgibbs ACCB_ACTIVE = 0x1, 29041047Sgibbs ACCB_DEVICE_RESET = 0x2, 29141047Sgibbs ACCB_RELEASE_SIMQ = 0x4 29241047Sgibbs} accb_flags_t; 29339225Sgibbs 29439225Sgibbsstruct aha_ccb { 29539225Sgibbs struct aha_hccb hccb; /* hccb assumed to be at 0 */ 29660938Sjake SLIST_ENTRY(aha_ccb) links; 297122340Simp uint32_t flags; 29839225Sgibbs union ccb *ccb; 29939225Sgibbs bus_dmamap_t dmamap; 300241589Sjhb struct callout timer; 30139225Sgibbs aha_sg_t *sg_list; 302122340Simp uint32_t sg_list_phys; 30339225Sgibbs}; 30439225Sgibbs 30539225Sgibbsstruct sg_map_node { 30639225Sgibbs bus_dmamap_t sg_dmamap; 30739225Sgibbs bus_addr_t sg_physaddr; 30839225Sgibbs aha_sg_t* sg_vaddr; 30960938Sjake SLIST_ENTRY(sg_map_node) links; 31039225Sgibbs}; 31139225Sgibbs 31239225Sgibbsstruct aha_softc { 31339225Sgibbs struct cam_sim *sim; 31439225Sgibbs struct cam_path *path; 31539225Sgibbs aha_mbox_out_t *cur_outbox; 31639225Sgibbs aha_mbox_in_t *cur_inbox; 31739225Sgibbs aha_mbox_out_t *last_outbox; 31839225Sgibbs aha_mbox_in_t *last_inbox; 31939225Sgibbs struct aha_ccb *aha_ccb_array; 32060938Sjake SLIST_HEAD(,aha_ccb) free_aha_ccbs; 32160938Sjake LIST_HEAD(,ccb_hdr) pending_ccbs; 32241047Sgibbs u_int active_ccbs; 323122340Simp uint32_t aha_ccb_physbase; 32442887Simp aha_ccb_opcode_t ccb_sg_opcode; 32542887Simp aha_ccb_opcode_t ccb_ccb_opcode; 32639225Sgibbs aha_mbox_in_t *in_boxes; 32739225Sgibbs aha_mbox_out_t *out_boxes; 32839225Sgibbs struct scsi_sense_data *sense_buffers; 329122340Simp uint32_t sense_buffers_physbase; 33041047Sgibbs struct aha_ccb *recovery_accb; 33139225Sgibbs u_int num_boxes; 33239225Sgibbs bus_dma_tag_t parent_dmat; /* 33339225Sgibbs * All dmat's derive from 33439225Sgibbs * the dmat defined by our 33539225Sgibbs * bus. 33639225Sgibbs */ 33739225Sgibbs bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 33839225Sgibbs bus_dma_tag_t mailbox_dmat; /* dmat for our mailboxes */ 33939225Sgibbs bus_dmamap_t mailbox_dmamap; 34039225Sgibbs bus_dma_tag_t ccb_dmat; /* dmat for our ccb array */ 34139225Sgibbs bus_dmamap_t ccb_dmamap; 34239225Sgibbs bus_dma_tag_t sg_dmat; /* dmat for our sg maps */ 34360938Sjake SLIST_HEAD(, sg_map_node) sg_maps; 34439225Sgibbs bus_addr_t mailbox_physbase; 34539225Sgibbs u_int num_ccbs; /* Number of CCBs malloc'd */ 34639225Sgibbs u_int max_ccbs; /* Maximum allocatable CCBs */ 34739225Sgibbs u_int max_sg; 34839225Sgibbs u_int unit; 34939225Sgibbs u_int scsi_id; 350122340Simp uint32_t extended_trans :1, 35139225Sgibbs diff_bus :1, 35239225Sgibbs extended_lun :1, 35339225Sgibbs strict_rr :1, 35439225Sgibbs tag_capable :1, 35539225Sgibbs resource_shortage:1, 35639852Simp :26; 357122340Simp uint16_t disc_permitted; 358122340Simp uint16_t sync_permitted; 359122340Simp uint8_t init_level; 360122340Simp volatile uint8_t command_cmp; 361122340Simp volatile uint8_t latched_status; 362122340Simp uint32_t bios_addr; 363122340Simp uint8_t fw_major; 364122340Simp uint8_t fw_minor; 36539225Sgibbs char model[32]; 366122340Simp uint8_t boardid; 36756504Simp struct resource *irq; 36856504Simp struct resource *port; 36956504Simp struct resource *drq; 370241589Sjhb int irqrid; 371241589Sjhb int portrid; 372241589Sjhb int drqrid; 373241603Sglebius void *ih; 374122597Simp device_t dev; 375241589Sjhb struct mtx lock; 37639225Sgibbs}; 37739225Sgibbs 378241603Sglebiusvoid aha_alloc(struct aha_softc *); 379122361Simpint aha_attach(struct aha_softc *); 380122361Simpint aha_cmd(struct aha_softc *, aha_op_t, uint8_t *, u_int, uint8_t *, u_int, 381122361Simp u_int); 382122361Simpint aha_detach(struct aha_softc *); 383122361Simpint aha_fetch_adapter_info(struct aha_softc *); 384122361Simpvoid aha_find_probe_range(int, int *, int *); 385122361Simpvoid aha_free(struct aha_softc *); 386122361Simpint aha_init(struct aha_softc *); 387122361Simpvoid aha_intr(void *); 388122361Simpint aha_probe(struct aha_softc *); 38939225Sgibbs 39039225Sgibbs#define DEFAULT_CMD_TIMEOUT 10000 /* 1 sec */ 39139225Sgibbs 392241603Sglebius#define aha_inb(aha, reg) \ 393241603Sglebius bus_read_1((aha)->port, reg) 39439225Sgibbs 395241603Sglebius#define aha_outb(aha, reg, value) \ 396241603Sglebius bus_write_1((aha)->port, reg, value) 39739225Sgibbs 39858544Simp#define ADP0100_PNP 0x00019004 /* ADP0100 */ 39958544Simp#define AHA1540_PNP 0x40159004 /* ADP1540 */ 40042887Simp#define AHA1542_PNP 0x42159004 /* ADP1542 */ 40142887Simp#define AHA1542_PNPCOMPAT 0xA000D040 /* PNP00A0 */ 40258544Simp#define ICU0091_PNP 0X91005AA4 /* ICU0091 */ 40342887Simp 404122535Simp#endif /* _AHAREG_H_ */ 405