octeon-pci-console.c revision 232812
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46#define CVMX_USE_1_TO_1_TLB_MAPPINGS 0 47#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 48#include <linux/kernel.h> 49#include <asm/octeon/cvmx.h> 50#include <asm/octeon/cvmx-spinlock.h> 51#include <asm/octeon/octeon-pci-console.h> 52 53#define MIN(a,b) min((a),(b)) 54 55#else 56#include "cvmx-platform.h" 57 58#include "cvmx.h" 59#include "cvmx-spinlock.h" 60#ifndef MIN 61# define MIN(a,b) (((a)<(b))?(a):(b)) 62#endif 63 64#include "cvmx-bootmem.h" 65#include "octeon-pci-console.h" 66#endif 67#ifdef __U_BOOT__ 68#include <watchdog.h> 69#endif 70 71#if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET) 72#include "octeon-pci.h" 73#endif 74 75 76/* The following code is only used in standalone CVMX applications. It does 77 not apply for kernel or Linux programming */ 78#if defined(OCTEON_TARGET) && !defined(__linux__) 79 80static int cvmx_pci_console_num = 0; 81static int per_core_pci_consoles = 0; 82static uint64_t pci_console_desc_addr = 0; 83/* This function for simple executive internal use only - do not use in any application */ 84int __cvmx_pci_console_write (int fd, char *buf, int nbytes) 85{ 86 int console_num; 87 if (fd >= 0x10000000) 88 { 89 console_num = fd & 0xFFFF; 90 } 91 else if (per_core_pci_consoles) 92 { 93 console_num = cvmx_get_core_num(); 94 } 95 else 96 console_num = cvmx_pci_console_num; 97 98 if (!pci_console_desc_addr) 99 { 100 const cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(OCTEON_PCI_CONSOLE_BLOCK_NAME); 101 pci_console_desc_addr = block_desc->base_addr; 102 } 103 104 105 return octeon_pci_console_write(pci_console_desc_addr, console_num, buf, nbytes, 0); 106 107} 108 109#endif 110 111 112#if !defined(CONFIG_OCTEON_U_BOOT) || (defined(CONFIG_OCTEON_U_BOOT) && (defined(CFG_PCI_CONSOLE) || defined(CONFIG_SYS_PCI_CONSOLE))) 113int octeon_pci_console_buffer_free_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx) 114{ 115 if (rd_idx >= buffer_size || wr_idx >= buffer_size) 116 return -1; 117 118 return (((buffer_size -1) - (wr_idx - rd_idx))%buffer_size); 119} 120int octeon_pci_console_buffer_avail_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx) 121{ 122 if (rd_idx >= buffer_size || wr_idx >= buffer_size) 123 return -1; 124 125 return (buffer_size - 1 - octeon_pci_console_buffer_free_bytes(buffer_size, wr_idx, rd_idx)); 126} 127#endif 128 129 130 131/* The following code is only used under Linux userspace when you are using 132 CVMX */ 133#if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET) 134int octeon_pci_console_host_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int write_reqest_size, uint32_t flags) 135{ 136 if (!console_desc_addr) 137 return -1; 138 139 /* Get global pci console information and look up specific console structure. */ 140 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles)); 141// printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size); 142 if (console_num >= num_consoles) 143 { 144 printf("ERROR: attempting to read non-existant console: %d\n", console_num); 145 return(-1); 146 } 147 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8); 148// printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr); 149 150 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size)); 151 /* Check to see if any data is available */ 152 uint32_t rd_idx, wr_idx; 153 uint64_t base_addr; 154 155 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, input_base_addr)); 156 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_read_index)); 157 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index)); 158 159// printf("Input base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx); 160 int bytes_to_write = octeon_pci_console_buffer_free_bytes(console_buffer_size, wr_idx, rd_idx); 161 if (bytes_to_write <= 0) 162 return bytes_to_write; 163 bytes_to_write = MIN(bytes_to_write, write_reqest_size); 164 /* Check to see if what we want to write is not contiguous, and limit ourselves to the contiguous block*/ 165 if (wr_idx + bytes_to_write >= console_buffer_size) 166 bytes_to_write = console_buffer_size - wr_idx; 167 168// printf("Attempting to write %d bytes, (buf size: %d)\n", bytes_to_write, write_reqest_size); 169 170 octeon_pci_write_mem(base_addr + wr_idx, buffer, bytes_to_write, OCTEON_PCI_ENDIAN_64BIT_SWAP); 171 octeon_write_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index), (wr_idx + bytes_to_write)%console_buffer_size); 172 173 return bytes_to_write; 174 175} 176 177int octeon_pci_console_host_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buf_size, uint32_t flags) 178{ 179 if (!console_desc_addr) 180 return -1; 181 182 /* Get global pci console information and look up specific console structure. */ 183 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles)); 184// printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size); 185 if (console_num >= num_consoles) 186 { 187 printf("ERROR: attempting to read non-existant console: %d\n", console_num); 188 return(-1); 189 } 190 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8); 191 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size)); 192// printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr); 193 194 /* Check to see if any data is available */ 195 uint32_t rd_idx, wr_idx; 196 uint64_t base_addr; 197 198 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, output_base_addr)); 199 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index)); 200 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_write_index)); 201 202// printf("Read buffer base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx); 203 int bytes_to_read = octeon_pci_console_buffer_avail_bytes(console_buffer_size, wr_idx, rd_idx); 204 if (bytes_to_read <= 0) 205 return bytes_to_read; 206 207 208 bytes_to_read = MIN(bytes_to_read, buf_size); 209 /* Check to see if what we want to read is not contiguous, and limit ourselves to the contiguous block*/ 210 if (rd_idx + bytes_to_read >= console_buffer_size) 211 bytes_to_read = console_buffer_size - rd_idx; 212 213 214 octeon_pci_read_mem(buffer, base_addr + rd_idx, bytes_to_read,OCTEON_PCI_ENDIAN_64BIT_SWAP); 215 octeon_write_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index), (rd_idx + bytes_to_read)%console_buffer_size); 216 217 return bytes_to_read; 218} 219 220 221int octeon_pci_console_host_write_avail(uint64_t console_desc_addr, unsigned int console_num) 222{ 223 if (!console_desc_addr) 224 return -1; 225 226 /* Get global pci console information and look up specific console structure. */ 227 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles)); 228// printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size); 229 if (console_num >= num_consoles) 230 { 231 printf("ERROR: attempting to read non-existant console: %d\n", console_num); 232 return -1; 233 } 234 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8); 235// printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr); 236 237 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size)); 238 /* Check to see if any data is available */ 239 uint32_t rd_idx, wr_idx; 240 uint64_t base_addr; 241 242 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, input_base_addr)); 243 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_read_index)); 244 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index)); 245 246// printf("Input base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx); 247 return octeon_pci_console_buffer_free_bytes(console_buffer_size, wr_idx, rd_idx); 248} 249 250 251int octeon_pci_console_host_read_avail(uint64_t console_desc_addr, unsigned int console_num) 252{ 253 if (!console_desc_addr) 254 return -1; 255 256 /* Get global pci console information and look up specific console structure. */ 257 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles)); 258// printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size); 259 if (console_num >= num_consoles) 260 { 261 printf("ERROR: attempting to read non-existant console: %d\n", console_num); 262 return(-1); 263 } 264 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8); 265 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size)); 266// printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr); 267 268 /* Check to see if any data is available */ 269 uint32_t rd_idx, wr_idx; 270 uint64_t base_addr; 271 272 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, output_base_addr)); 273 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index)); 274 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_write_index)); 275 276// printf("Read buffer base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx); 277 return octeon_pci_console_buffer_avail_bytes(console_buffer_size, wr_idx, rd_idx); 278} 279 280 281#endif /* TARGET_HOST */ 282 283 284 285 286 287 288/* This code is only available in a kernel or CVMX standalone. It can't be used 289 from userspace */ 290#if (!defined(CONFIG_OCTEON_U_BOOT) && (!defined(__linux__) || defined(__KERNEL__))) || (defined(CONFIG_OCTEON_U_BOOT) && (defined(CFG_PCI_CONSOLE) || defined(CONFIG_SYS_PCI_CONSOLE))) 291 292static octeon_pci_console_t *octeon_pci_console_get_ptr(uint64_t console_desc_addr, unsigned int console_num) 293{ 294 octeon_pci_console_desc_t *cons_desc_ptr; 295 296 if (!console_desc_addr) 297 return NULL; 298 299 cons_desc_ptr = (octeon_pci_console_desc_t *)cvmx_phys_to_ptr(console_desc_addr); 300 if (console_num >= cons_desc_ptr->num_consoles) 301 return NULL; 302 303 return (octeon_pci_console_t *)cvmx_phys_to_ptr(cons_desc_ptr->console_addr_array[console_num]); 304} 305 306 307int octeon_pci_console_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int bytes_to_write, uint32_t flags) 308{ 309 octeon_pci_console_t *cons_ptr; 310 cvmx_spinlock_t *lock; 311 int bytes_available; 312 char *buf_ptr; 313 int bytes_written; 314 315 cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num); 316 if (!cons_ptr) 317 return -1; 318 319 lock = (cvmx_spinlock_t *)&cons_ptr->lock; 320 321 buf_ptr = (char*)cvmx_phys_to_ptr(cons_ptr->output_base_addr); 322 bytes_written = 0; 323 cvmx_spinlock_lock(lock); 324 while (bytes_to_write > 0) 325 { 326 bytes_available = octeon_pci_console_buffer_free_bytes(cons_ptr->buf_size, cons_ptr->output_write_index, cons_ptr->output_read_index); 327// printf("Console %d has %d bytes available for writes\n", console_num, bytes_available); 328 if (bytes_available > 0) 329 { 330 int write_size = MIN(bytes_available, bytes_to_write); 331 /* Limit ourselves to what we can output in a contiguous block */ 332 if (cons_ptr->output_write_index + write_size >= cons_ptr->buf_size) 333 write_size = cons_ptr->buf_size - cons_ptr->output_write_index; 334 335 memcpy(buf_ptr + cons_ptr->output_write_index, buffer + bytes_written, write_size); 336 CVMX_SYNCW; /* Make sure data is visible before changing write index */ 337 cons_ptr->output_write_index = (cons_ptr->output_write_index + write_size)%cons_ptr->buf_size; 338 bytes_to_write -= write_size; 339 bytes_written += write_size; 340 } 341 else if (bytes_available == 0) 342 { 343 /* Check to see if we should wait for room, or return after a partial write */ 344 if (flags & OCT_PCI_CON_FLAG_NONBLOCK) 345 goto done; 346 347#ifdef __U_BOOT__ 348 WATCHDOG_RESET(); 349#endif 350 cvmx_wait(1000000); /* Delay if we are spinning */ 351 } 352 else 353 { 354 bytes_written = -1; 355 goto done; 356 } 357 } 358 359done: 360 cvmx_spinlock_unlock(lock); 361 return(bytes_written); 362} 363 364int octeon_pci_console_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buffer_size, uint32_t flags) 365{ 366 int bytes_available; 367 char *buf_ptr; 368 cvmx_spinlock_t *lock; 369 int bytes_read; 370 int read_size; 371 octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num); 372 if (!cons_ptr) 373 return -1; 374 375 buf_ptr = (char*)cvmx_phys_to_ptr(cons_ptr->input_base_addr); 376 377 bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index); 378 if (bytes_available < 0) 379 return bytes_available; 380 381 lock = (cvmx_spinlock_t *)&cons_ptr->lock; 382 cvmx_spinlock_lock(lock); 383 384 if (!(flags & OCT_PCI_CON_FLAG_NONBLOCK)) 385 { 386 /* Wait for some data to be available */ 387 while (0 == (bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index))) 388 { 389 cvmx_wait(1000000); 390#ifdef __U_BOOT__ 391 WATCHDOG_RESET(); 392#endif 393 } 394 } 395 396 bytes_read = 0; 397// printf("Console %d has %d bytes available for writes\n", console_num, bytes_available); 398 399 /* Don't overflow the buffer passed to us */ 400 read_size = MIN(bytes_available, buffer_size); 401 402 /* Limit ourselves to what we can input in a contiguous block */ 403 if (cons_ptr->input_read_index + read_size >= cons_ptr->buf_size) 404 read_size = cons_ptr->buf_size - cons_ptr->input_read_index; 405 406 memcpy(buffer, buf_ptr + cons_ptr->input_read_index, read_size); 407 cons_ptr->input_read_index = (cons_ptr->input_read_index + read_size)%cons_ptr->buf_size; 408 bytes_read += read_size; 409 410 cvmx_spinlock_unlock(lock); 411 return(bytes_read); 412} 413 414 415int octeon_pci_console_write_avail(uint64_t console_desc_addr, unsigned int console_num) 416{ 417 int bytes_available; 418 octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num); 419 if (!cons_ptr) 420 return -1; 421 422 bytes_available = octeon_pci_console_buffer_free_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index); 423 if (bytes_available >= 0) 424 return(bytes_available); 425 else 426 return 0; 427} 428 429 430int octeon_pci_console_read_avail(uint64_t console_desc_addr, unsigned int console_num) 431{ 432 int bytes_available; 433 octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num); 434 if (!cons_ptr) 435 return -1; 436 437 bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index); 438 if (bytes_available >= 0) 439 return(bytes_available); 440 else 441 return 0; 442} 443 444#endif 445 446 447/* This code can only be used in the bootloader */ 448#if defined(CONFIG_OCTEON_U_BOOT) && (defined(CFG_PCI_CONSOLE) || defined(CONFIG_SYS_PCI_CONSOLE)) 449uint64_t octeon_pci_console_init(int num_consoles, int buffer_size) 450{ 451 octeon_pci_console_desc_t *cons_desc_ptr; 452 octeon_pci_console_t *cons_ptr; 453 454 /* Compute size required for pci console structure */ 455 int alloc_size = num_consoles * (buffer_size * 2 + sizeof(octeon_pci_console_t) + sizeof(uint64_t)) + sizeof(octeon_pci_console_desc_t); 456 457 /* Allocate memory for the consoles. This must be in the range addresssible by the bootloader. 458 ** Try to do so in a manner which minimizes fragmentation. We try to put it at the top of DDR0 or bottom of 459 ** DDR2 first, and only do generic allocation if those fail */ 460 int64_t console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, OCTEON_DDR0_SIZE - alloc_size - 128, OCTEON_DDR0_SIZE, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC); 461 if (console_block_addr < 0) 462 console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, OCTEON_DDR2_BASE + 1, OCTEON_DDR2_BASE + alloc_size + 128, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC); 463 if (console_block_addr < 0) 464 console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0, 0x7fffffff, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC); 465 if (console_block_addr < 0) 466 return 0; 467 468 cons_desc_ptr = (void *)(uint32_t)console_block_addr; 469 470 memset(cons_desc_ptr, 0, alloc_size); /* Clear entire alloc'ed memory */ 471 472 cons_desc_ptr->lock = 1; /* initialize as locked until we are done */ 473 CVMX_SYNCW; 474 cons_desc_ptr->num_consoles = num_consoles; 475 cons_desc_ptr->flags = 0; 476 cons_desc_ptr->major_version = OCTEON_PCI_CONSOLE_MAJOR_VERSION; 477 cons_desc_ptr->minor_version = OCTEON_PCI_CONSOLE_MINOR_VERSION; 478 479 int i; 480 uint64_t avail_addr = console_block_addr + sizeof(octeon_pci_console_desc_t) + num_consoles * sizeof(uint64_t); 481 for (i = 0; i < num_consoles;i++) 482 { 483 cons_desc_ptr->console_addr_array[i] = avail_addr; 484 cons_ptr = (void *)(uint32_t)cons_desc_ptr->console_addr_array[i]; 485 avail_addr += sizeof(octeon_pci_console_t); 486 cons_ptr->input_base_addr = avail_addr; 487 avail_addr += buffer_size; 488 cons_ptr->output_base_addr = avail_addr; 489 avail_addr += buffer_size; 490 cons_ptr->buf_size = buffer_size; 491 } 492 CVMX_SYNCW; 493 cons_desc_ptr->lock = 0; 494 495 return console_block_addr; 496 497 498} 499#endif 500