1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pcsxx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pcsxx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_PCSXX_DEFS_H__ 53232812Sjmallett#define __CVMX_PCSXX_DEFS_H__ 54215976Sjmallett 55215976Sjmallettstatic inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id) 56215976Sjmallett{ 57232812Sjmallett switch(cvmx_get_octeon_family()) { 58232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 59232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 60232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 61232812Sjmallett if ((block_id <= 1)) 62232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull; 63232812Sjmallett break; 64232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 65232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 66232812Sjmallett if ((block_id == 0)) 67232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 0) * 0x8000000ull; 68232812Sjmallett break; 69232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 70232812Sjmallett if ((block_id <= 4)) 71232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 7) * 0x1000000ull; 72232812Sjmallett break; 73232812Sjmallett } 74232812Sjmallett cvmx_warn("CVMX_PCSXX_10GBX_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id); 75232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 7) * 0x1000000ull; 76215976Sjmallett} 77215976Sjmallettstatic inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id) 78215976Sjmallett{ 79232812Sjmallett switch(cvmx_get_octeon_family()) { 80232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 81232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 82232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 83232812Sjmallett if ((block_id <= 1)) 84232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull; 85232812Sjmallett break; 86232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 87232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 88232812Sjmallett if ((block_id == 0)) 89232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 0) * 0x8000000ull; 90232812Sjmallett break; 91232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 92232812Sjmallett if ((block_id <= 4)) 93232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 7) * 0x1000000ull; 94232812Sjmallett break; 95232812Sjmallett } 96232812Sjmallett cvmx_warn("CVMX_PCSXX_BIST_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id); 97232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 7) * 0x1000000ull; 98215976Sjmallett} 99215976Sjmallettstatic inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id) 100215976Sjmallett{ 101232812Sjmallett switch(cvmx_get_octeon_family()) { 102232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 103232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 104232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 105232812Sjmallett if ((block_id <= 1)) 106232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull; 107232812Sjmallett break; 108232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 109232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 110232812Sjmallett if ((block_id == 0)) 111232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 0) * 0x8000000ull; 112232812Sjmallett break; 113232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 114232812Sjmallett if ((block_id <= 4)) 115232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 7) * 0x1000000ull; 116232812Sjmallett break; 117232812Sjmallett } 118232812Sjmallett cvmx_warn("CVMX_PCSXX_BIT_LOCK_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id); 119232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 7) * 0x1000000ull; 120215976Sjmallett} 121215976Sjmallettstatic inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id) 122215976Sjmallett{ 123232812Sjmallett switch(cvmx_get_octeon_family()) { 124232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 125232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 126232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 127232812Sjmallett if ((block_id <= 1)) 128232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 1) * 0x8000000ull; 129232812Sjmallett break; 130232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 131232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 132232812Sjmallett if ((block_id == 0)) 133232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 0) * 0x8000000ull; 134232812Sjmallett break; 135232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 136232812Sjmallett if ((block_id <= 4)) 137232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 7) * 0x1000000ull; 138232812Sjmallett break; 139232812Sjmallett } 140232812Sjmallett cvmx_warn("CVMX_PCSXX_CONTROL1_REG (block_id = %lu) not supported on this chip\n", block_id); 141232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 7) * 0x1000000ull; 142215976Sjmallett} 143215976Sjmallettstatic inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id) 144215976Sjmallett{ 145232812Sjmallett switch(cvmx_get_octeon_family()) { 146232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 147232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 148232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 149232812Sjmallett if ((block_id <= 1)) 150232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 1) * 0x8000000ull; 151232812Sjmallett break; 152232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 153232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 154232812Sjmallett if ((block_id == 0)) 155232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 0) * 0x8000000ull; 156232812Sjmallett break; 157232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 158232812Sjmallett if ((block_id <= 4)) 159232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 7) * 0x1000000ull; 160232812Sjmallett break; 161232812Sjmallett } 162232812Sjmallett cvmx_warn("CVMX_PCSXX_CONTROL2_REG (block_id = %lu) not supported on this chip\n", block_id); 163232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 7) * 0x1000000ull; 164215976Sjmallett} 165215976Sjmallettstatic inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id) 166215976Sjmallett{ 167232812Sjmallett switch(cvmx_get_octeon_family()) { 168232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 169232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 170232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 171232812Sjmallett if ((block_id <= 1)) 172232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 1) * 0x8000000ull; 173232812Sjmallett break; 174232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 175232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 176232812Sjmallett if ((block_id == 0)) 177232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 0) * 0x8000000ull; 178232812Sjmallett break; 179232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 180232812Sjmallett if ((block_id <= 4)) 181232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 7) * 0x1000000ull; 182232812Sjmallett break; 183232812Sjmallett } 184232812Sjmallett cvmx_warn("CVMX_PCSXX_INT_EN_REG (block_id = %lu) not supported on this chip\n", block_id); 185232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 7) * 0x1000000ull; 186215976Sjmallett} 187215976Sjmallettstatic inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id) 188215976Sjmallett{ 189232812Sjmallett switch(cvmx_get_octeon_family()) { 190232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 191232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 192232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 193232812Sjmallett if ((block_id <= 1)) 194232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 1) * 0x8000000ull; 195232812Sjmallett break; 196232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 197232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 198232812Sjmallett if ((block_id == 0)) 199232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 0) * 0x8000000ull; 200232812Sjmallett break; 201232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 202232812Sjmallett if ((block_id <= 4)) 203232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 7) * 0x1000000ull; 204232812Sjmallett break; 205232812Sjmallett } 206232812Sjmallett cvmx_warn("CVMX_PCSXX_INT_REG (block_id = %lu) not supported on this chip\n", block_id); 207232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 7) * 0x1000000ull; 208215976Sjmallett} 209215976Sjmallettstatic inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id) 210215976Sjmallett{ 211232812Sjmallett switch(cvmx_get_octeon_family()) { 212232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 213232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 214232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 215232812Sjmallett if ((block_id <= 1)) 216232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 1) * 0x8000000ull; 217232812Sjmallett break; 218232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 219232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 220232812Sjmallett if ((block_id == 0)) 221232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 0) * 0x8000000ull; 222232812Sjmallett break; 223232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 224232812Sjmallett if ((block_id <= 4)) 225232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 7) * 0x1000000ull; 226232812Sjmallett break; 227232812Sjmallett } 228232812Sjmallett cvmx_warn("CVMX_PCSXX_LOG_ANL_REG (block_id = %lu) not supported on this chip\n", block_id); 229232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 7) * 0x1000000ull; 230215976Sjmallett} 231215976Sjmallettstatic inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id) 232215976Sjmallett{ 233232812Sjmallett switch(cvmx_get_octeon_family()) { 234232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 235232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 236232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 237232812Sjmallett if ((block_id <= 1)) 238232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 1) * 0x8000000ull; 239232812Sjmallett break; 240232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 241232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 242232812Sjmallett if ((block_id == 0)) 243232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 0) * 0x8000000ull; 244232812Sjmallett break; 245232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 246232812Sjmallett if ((block_id <= 4)) 247232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 7) * 0x1000000ull; 248232812Sjmallett break; 249232812Sjmallett } 250232812Sjmallett cvmx_warn("CVMX_PCSXX_MISC_CTL_REG (block_id = %lu) not supported on this chip\n", block_id); 251232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 7) * 0x1000000ull; 252215976Sjmallett} 253215976Sjmallettstatic inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id) 254215976Sjmallett{ 255232812Sjmallett switch(cvmx_get_octeon_family()) { 256232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 257232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 258232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 259232812Sjmallett if ((block_id <= 1)) 260232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 1) * 0x8000000ull; 261232812Sjmallett break; 262232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 263232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 264232812Sjmallett if ((block_id == 0)) 265232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 0) * 0x8000000ull; 266232812Sjmallett break; 267232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 268232812Sjmallett if ((block_id <= 4)) 269232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 7) * 0x1000000ull; 270232812Sjmallett break; 271232812Sjmallett } 272232812Sjmallett cvmx_warn("CVMX_PCSXX_RX_SYNC_STATES_REG (block_id = %lu) not supported on this chip\n", block_id); 273232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 7) * 0x1000000ull; 274215976Sjmallett} 275215976Sjmallettstatic inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id) 276215976Sjmallett{ 277232812Sjmallett switch(cvmx_get_octeon_family()) { 278232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 279232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 280232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 281232812Sjmallett if ((block_id <= 1)) 282232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 1) * 0x8000000ull; 283232812Sjmallett break; 284232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 285232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 286232812Sjmallett if ((block_id == 0)) 287232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 0) * 0x8000000ull; 288232812Sjmallett break; 289232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 290232812Sjmallett if ((block_id <= 4)) 291232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 7) * 0x1000000ull; 292232812Sjmallett break; 293232812Sjmallett } 294232812Sjmallett cvmx_warn("CVMX_PCSXX_SPD_ABIL_REG (block_id = %lu) not supported on this chip\n", block_id); 295232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 7) * 0x1000000ull; 296215976Sjmallett} 297215976Sjmallettstatic inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id) 298215976Sjmallett{ 299232812Sjmallett switch(cvmx_get_octeon_family()) { 300232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 301232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 302232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 303232812Sjmallett if ((block_id <= 1)) 304232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 1) * 0x8000000ull; 305232812Sjmallett break; 306232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 307232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 308232812Sjmallett if ((block_id == 0)) 309232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 0) * 0x8000000ull; 310232812Sjmallett break; 311232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 312232812Sjmallett if ((block_id <= 4)) 313232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 7) * 0x1000000ull; 314232812Sjmallett break; 315232812Sjmallett } 316232812Sjmallett cvmx_warn("CVMX_PCSXX_STATUS1_REG (block_id = %lu) not supported on this chip\n", block_id); 317232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 7) * 0x1000000ull; 318215976Sjmallett} 319215976Sjmallettstatic inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id) 320215976Sjmallett{ 321232812Sjmallett switch(cvmx_get_octeon_family()) { 322232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 323232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 324232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 325232812Sjmallett if ((block_id <= 1)) 326232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 1) * 0x8000000ull; 327232812Sjmallett break; 328232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 329232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 330232812Sjmallett if ((block_id == 0)) 331232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 0) * 0x8000000ull; 332232812Sjmallett break; 333232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 334232812Sjmallett if ((block_id <= 4)) 335232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 7) * 0x1000000ull; 336232812Sjmallett break; 337232812Sjmallett } 338232812Sjmallett cvmx_warn("CVMX_PCSXX_STATUS2_REG (block_id = %lu) not supported on this chip\n", block_id); 339232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 7) * 0x1000000ull; 340215976Sjmallett} 341215976Sjmallettstatic inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id) 342215976Sjmallett{ 343232812Sjmallett switch(cvmx_get_octeon_family()) { 344232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 345232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 346232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 347232812Sjmallett if ((block_id <= 1)) 348232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 1) * 0x8000000ull; 349232812Sjmallett break; 350232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 351232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 352232812Sjmallett if ((block_id == 0)) 353232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 0) * 0x8000000ull; 354232812Sjmallett break; 355232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 356232812Sjmallett if ((block_id <= 4)) 357232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 7) * 0x1000000ull; 358232812Sjmallett break; 359232812Sjmallett } 360232812Sjmallett cvmx_warn("CVMX_PCSXX_TX_RX_POLARITY_REG (block_id = %lu) not supported on this chip\n", block_id); 361232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 7) * 0x1000000ull; 362215976Sjmallett} 363215976Sjmallettstatic inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id) 364215976Sjmallett{ 365232812Sjmallett switch(cvmx_get_octeon_family()) { 366232812Sjmallett case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 367232812Sjmallett case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 368232812Sjmallett case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 369232812Sjmallett if ((block_id <= 1)) 370232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 1) * 0x8000000ull; 371232812Sjmallett break; 372232812Sjmallett case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 373232812Sjmallett case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 374232812Sjmallett if ((block_id == 0)) 375232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 0) * 0x8000000ull; 376232812Sjmallett break; 377232812Sjmallett case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 378232812Sjmallett if ((block_id <= 4)) 379232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 7) * 0x1000000ull; 380232812Sjmallett break; 381232812Sjmallett } 382232812Sjmallett cvmx_warn("CVMX_PCSXX_TX_RX_STATES_REG (block_id = %lu) not supported on this chip\n", block_id); 383232812Sjmallett return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 7) * 0x1000000ull; 384215976Sjmallett} 385215976Sjmallett 386215976Sjmallett/** 387215976Sjmallett * cvmx_pcsx#_10gbx_status_reg 388215976Sjmallett * 389215976Sjmallett * PCSX_10GBX_STATUS_REG = 10gbx_status_reg 390215976Sjmallett * 391215976Sjmallett */ 392232812Sjmallettunion cvmx_pcsxx_10gbx_status_reg { 393215976Sjmallett uint64_t u64; 394232812Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s { 395232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 396215976Sjmallett uint64_t reserved_13_63 : 51; 397215976Sjmallett uint64_t alignd : 1; /**< 1=Lane alignment achieved, 0=Lanes not aligned */ 398215976Sjmallett uint64_t pattst : 1; /**< Always at 0, no pattern testing capability */ 399215976Sjmallett uint64_t reserved_4_10 : 7; 400215976Sjmallett uint64_t l3sync : 1; /**< 1=Rcv lane 3 code grp synchronized, 0=not sync'ed */ 401215976Sjmallett uint64_t l2sync : 1; /**< 1=Rcv lane 2 code grp synchronized, 0=not sync'ed */ 402215976Sjmallett uint64_t l1sync : 1; /**< 1=Rcv lane 1 code grp synchronized, 0=not sync'ed */ 403215976Sjmallett uint64_t l0sync : 1; /**< 1=Rcv lane 0 code grp synchronized, 0=not sync'ed */ 404215976Sjmallett#else 405215976Sjmallett uint64_t l0sync : 1; 406215976Sjmallett uint64_t l1sync : 1; 407215976Sjmallett uint64_t l2sync : 1; 408215976Sjmallett uint64_t l3sync : 1; 409215976Sjmallett uint64_t reserved_4_10 : 7; 410215976Sjmallett uint64_t pattst : 1; 411215976Sjmallett uint64_t alignd : 1; 412215976Sjmallett uint64_t reserved_13_63 : 51; 413215976Sjmallett#endif 414215976Sjmallett } s; 415215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; 416215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; 417215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; 418215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; 419232812Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn61xx; 420215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn63xx; 421215976Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1; 422232812Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn66xx; 423232812Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn68xx; 424232812Sjmallett struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1; 425215976Sjmallett}; 426215976Sjmalletttypedef union cvmx_pcsxx_10gbx_status_reg cvmx_pcsxx_10gbx_status_reg_t; 427215976Sjmallett 428215976Sjmallett/** 429215976Sjmallett * cvmx_pcsx#_bist_status_reg 430215976Sjmallett * 431215976Sjmallett * NOTE: Logic Analyzer is enabled with LA_EN for xaui only. PKT_SZ is effective only when LA_EN=1 432215976Sjmallett * For normal operation(xaui), this bit must be 0. The dropped lane is used to send rxc[3:0]. 433215976Sjmallett * See pcs.csr for sgmii/1000Base-X logic analyzer mode. 434215976Sjmallett * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt 435215976Sjmallett * 436215976Sjmallett * 437215976Sjmallett * PCSX Bist Status Register 438215976Sjmallett */ 439232812Sjmallettunion cvmx_pcsxx_bist_status_reg { 440215976Sjmallett uint64_t u64; 441232812Sjmallett struct cvmx_pcsxx_bist_status_reg_s { 442232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 443215976Sjmallett uint64_t reserved_1_63 : 63; 444215976Sjmallett uint64_t bist_status : 1; /**< 1=bist failure, 0=bisted memory ok or bist in progress 445215976Sjmallett pcsx.tx_sm.drf8x36m1_async_bist */ 446215976Sjmallett#else 447215976Sjmallett uint64_t bist_status : 1; 448215976Sjmallett uint64_t reserved_1_63 : 63; 449215976Sjmallett#endif 450215976Sjmallett } s; 451215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn52xx; 452215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; 453215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn56xx; 454215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; 455232812Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn61xx; 456215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn63xx; 457215976Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn63xxp1; 458232812Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn66xx; 459232812Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn68xx; 460232812Sjmallett struct cvmx_pcsxx_bist_status_reg_s cn68xxp1; 461215976Sjmallett}; 462215976Sjmalletttypedef union cvmx_pcsxx_bist_status_reg cvmx_pcsxx_bist_status_reg_t; 463215976Sjmallett 464215976Sjmallett/** 465215976Sjmallett * cvmx_pcsx#_bit_lock_status_reg 466215976Sjmallett * 467215976Sjmallett * LN_SWAP for XAUI is to simplify interconnection layout between devices 468215976Sjmallett * 469215976Sjmallett * 470215976Sjmallett * PCSX Bit Lock Status Register 471215976Sjmallett */ 472232812Sjmallettunion cvmx_pcsxx_bit_lock_status_reg { 473215976Sjmallett uint64_t u64; 474232812Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s { 475232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 476215976Sjmallett uint64_t reserved_4_63 : 60; 477215976Sjmallett uint64_t bitlck3 : 1; /**< Receive Lane 3 bit lock status */ 478215976Sjmallett uint64_t bitlck2 : 1; /**< Receive Lane 2 bit lock status */ 479215976Sjmallett uint64_t bitlck1 : 1; /**< Receive Lane 1 bit lock status */ 480215976Sjmallett uint64_t bitlck0 : 1; /**< Receive Lane 0 bit lock status */ 481215976Sjmallett#else 482215976Sjmallett uint64_t bitlck0 : 1; 483215976Sjmallett uint64_t bitlck1 : 1; 484215976Sjmallett uint64_t bitlck2 : 1; 485215976Sjmallett uint64_t bitlck3 : 1; 486215976Sjmallett uint64_t reserved_4_63 : 60; 487215976Sjmallett#endif 488215976Sjmallett } s; 489215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; 490215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; 491215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; 492215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; 493232812Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx; 494215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx; 495215976Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1; 496232812Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx; 497232812Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx; 498232812Sjmallett struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1; 499215976Sjmallett}; 500215976Sjmalletttypedef union cvmx_pcsxx_bit_lock_status_reg cvmx_pcsxx_bit_lock_status_reg_t; 501215976Sjmallett 502215976Sjmallett/** 503215976Sjmallett * cvmx_pcsx#_control1_reg 504215976Sjmallett * 505215976Sjmallett * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is effective only when LA_EN=1 506215976Sjmallett * For normal operation(sgmii or 1000Base-X), this bit must be 0. 507215976Sjmallett * See pcsx.csr for xaui logic analyzer mode. 508215976Sjmallett * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt 509215976Sjmallett * 510215976Sjmallett * 511215976Sjmallett * PCSX regs follow IEEE Std 802.3-2005, Section: 45.2.3 512215976Sjmallett * 513215976Sjmallett * 514215976Sjmallett * PCSX_CONTROL1_REG = Control Register1 515215976Sjmallett */ 516232812Sjmallettunion cvmx_pcsxx_control1_reg { 517215976Sjmallett uint64_t u64; 518232812Sjmallett struct cvmx_pcsxx_control1_reg_s { 519232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 520215976Sjmallett uint64_t reserved_16_63 : 48; 521215976Sjmallett uint64_t reset : 1; /**< 1=SW PCSX Reset, the bit will return to 0 after pcs 522215976Sjmallett has been reset. Takes 32 eclk cycles to reset pcs 523215976Sjmallett 0=Normal operation */ 524215976Sjmallett uint64_t loopbck1 : 1; /**< 0=normal operation, 1=internal loopback mode 525215976Sjmallett xgmii tx data received from gmx tx port is returned 526215976Sjmallett back into gmx, xgmii rx port. */ 527215976Sjmallett uint64_t spdsel1 : 1; /**< See bit 6 description */ 528215976Sjmallett uint64_t reserved_12_12 : 1; 529215976Sjmallett uint64_t lo_pwr : 1; /**< 1=Power Down(HW reset), 0=Normal operation */ 530215976Sjmallett uint64_t reserved_7_10 : 4; 531215976Sjmallett uint64_t spdsel0 : 1; /**< SPDSEL1 and SPDSEL0 are always at 1'b1. Write has 532215976Sjmallett no effect. 533215976Sjmallett [<6>, <13>]Link Speed selection 534215976Sjmallett 1 1 Bits 5:2 select speed */ 535215976Sjmallett uint64_t spd : 4; /**< Always select 10Gb/s, writes have no effect */ 536215976Sjmallett uint64_t reserved_0_1 : 2; 537215976Sjmallett#else 538215976Sjmallett uint64_t reserved_0_1 : 2; 539215976Sjmallett uint64_t spd : 4; 540215976Sjmallett uint64_t spdsel0 : 1; 541215976Sjmallett uint64_t reserved_7_10 : 4; 542215976Sjmallett uint64_t lo_pwr : 1; 543215976Sjmallett uint64_t reserved_12_12 : 1; 544215976Sjmallett uint64_t spdsel1 : 1; 545215976Sjmallett uint64_t loopbck1 : 1; 546215976Sjmallett uint64_t reset : 1; 547215976Sjmallett uint64_t reserved_16_63 : 48; 548215976Sjmallett#endif 549215976Sjmallett } s; 550215976Sjmallett struct cvmx_pcsxx_control1_reg_s cn52xx; 551215976Sjmallett struct cvmx_pcsxx_control1_reg_s cn52xxp1; 552215976Sjmallett struct cvmx_pcsxx_control1_reg_s cn56xx; 553215976Sjmallett struct cvmx_pcsxx_control1_reg_s cn56xxp1; 554232812Sjmallett struct cvmx_pcsxx_control1_reg_s cn61xx; 555215976Sjmallett struct cvmx_pcsxx_control1_reg_s cn63xx; 556215976Sjmallett struct cvmx_pcsxx_control1_reg_s cn63xxp1; 557232812Sjmallett struct cvmx_pcsxx_control1_reg_s cn66xx; 558232812Sjmallett struct cvmx_pcsxx_control1_reg_s cn68xx; 559232812Sjmallett struct cvmx_pcsxx_control1_reg_s cn68xxp1; 560215976Sjmallett}; 561215976Sjmalletttypedef union cvmx_pcsxx_control1_reg cvmx_pcsxx_control1_reg_t; 562215976Sjmallett 563215976Sjmallett/** 564215976Sjmallett * cvmx_pcsx#_control2_reg 565215976Sjmallett * 566215976Sjmallett * PCSX_CONTROL2_REG = Control Register2 567215976Sjmallett * 568215976Sjmallett */ 569232812Sjmallettunion cvmx_pcsxx_control2_reg { 570215976Sjmallett uint64_t u64; 571232812Sjmallett struct cvmx_pcsxx_control2_reg_s { 572232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 573215976Sjmallett uint64_t reserved_2_63 : 62; 574215976Sjmallett uint64_t type : 2; /**< Always 2'b01, 10GBASE-X only supported */ 575215976Sjmallett#else 576215976Sjmallett uint64_t type : 2; 577215976Sjmallett uint64_t reserved_2_63 : 62; 578215976Sjmallett#endif 579215976Sjmallett } s; 580215976Sjmallett struct cvmx_pcsxx_control2_reg_s cn52xx; 581215976Sjmallett struct cvmx_pcsxx_control2_reg_s cn52xxp1; 582215976Sjmallett struct cvmx_pcsxx_control2_reg_s cn56xx; 583215976Sjmallett struct cvmx_pcsxx_control2_reg_s cn56xxp1; 584232812Sjmallett struct cvmx_pcsxx_control2_reg_s cn61xx; 585215976Sjmallett struct cvmx_pcsxx_control2_reg_s cn63xx; 586215976Sjmallett struct cvmx_pcsxx_control2_reg_s cn63xxp1; 587232812Sjmallett struct cvmx_pcsxx_control2_reg_s cn66xx; 588232812Sjmallett struct cvmx_pcsxx_control2_reg_s cn68xx; 589232812Sjmallett struct cvmx_pcsxx_control2_reg_s cn68xxp1; 590215976Sjmallett}; 591215976Sjmalletttypedef union cvmx_pcsxx_control2_reg cvmx_pcsxx_control2_reg_t; 592215976Sjmallett 593215976Sjmallett/** 594215976Sjmallett * cvmx_pcsx#_int_en_reg 595215976Sjmallett * 596215976Sjmallett * Note: DBG_SYNC is a edge triggered interrupt. When set it indicates PCS Synchronization state machine in 597215976Sjmallett * Figure 48-7 state diagram in IEEE Std 802.3-2005 changes state SYNC_ACQUIRED_1 to SYNC_ACQUIRED_2 598215976Sjmallett * indicating an invalid code group was received on one of the 4 receive lanes. 599215976Sjmallett * This interrupt should be always disabled and used only for link problem debugging help. 600215976Sjmallett * 601215976Sjmallett * 602215976Sjmallett * PCSX Interrupt Enable Register 603215976Sjmallett */ 604232812Sjmallettunion cvmx_pcsxx_int_en_reg { 605215976Sjmallett uint64_t u64; 606232812Sjmallett struct cvmx_pcsxx_int_en_reg_s { 607232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 608215976Sjmallett uint64_t reserved_7_63 : 57; 609215976Sjmallett uint64_t dbg_sync_en : 1; /**< Code Group sync failure debug help */ 610215976Sjmallett uint64_t algnlos_en : 1; /**< Enable ALGNLOS interrupt */ 611215976Sjmallett uint64_t synlos_en : 1; /**< Enable SYNLOS interrupt */ 612215976Sjmallett uint64_t bitlckls_en : 1; /**< Enable BITLCKLS interrupt */ 613215976Sjmallett uint64_t rxsynbad_en : 1; /**< Enable RXSYNBAD interrupt */ 614215976Sjmallett uint64_t rxbad_en : 1; /**< Enable RXBAD interrupt */ 615215976Sjmallett uint64_t txflt_en : 1; /**< Enable TXFLT interrupt */ 616215976Sjmallett#else 617215976Sjmallett uint64_t txflt_en : 1; 618215976Sjmallett uint64_t rxbad_en : 1; 619215976Sjmallett uint64_t rxsynbad_en : 1; 620215976Sjmallett uint64_t bitlckls_en : 1; 621215976Sjmallett uint64_t synlos_en : 1; 622215976Sjmallett uint64_t algnlos_en : 1; 623215976Sjmallett uint64_t dbg_sync_en : 1; 624215976Sjmallett uint64_t reserved_7_63 : 57; 625215976Sjmallett#endif 626215976Sjmallett } s; 627232812Sjmallett struct cvmx_pcsxx_int_en_reg_cn52xx { 628232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 629215976Sjmallett uint64_t reserved_6_63 : 58; 630215976Sjmallett uint64_t algnlos_en : 1; /**< Enable ALGNLOS interrupt */ 631215976Sjmallett uint64_t synlos_en : 1; /**< Enable SYNLOS interrupt */ 632215976Sjmallett uint64_t bitlckls_en : 1; /**< Enable BITLCKLS interrupt */ 633215976Sjmallett uint64_t rxsynbad_en : 1; /**< Enable RXSYNBAD interrupt */ 634215976Sjmallett uint64_t rxbad_en : 1; /**< Enable RXBAD interrupt */ 635215976Sjmallett uint64_t txflt_en : 1; /**< Enable TXFLT interrupt */ 636215976Sjmallett#else 637215976Sjmallett uint64_t txflt_en : 1; 638215976Sjmallett uint64_t rxbad_en : 1; 639215976Sjmallett uint64_t rxsynbad_en : 1; 640215976Sjmallett uint64_t bitlckls_en : 1; 641215976Sjmallett uint64_t synlos_en : 1; 642215976Sjmallett uint64_t algnlos_en : 1; 643215976Sjmallett uint64_t reserved_6_63 : 58; 644215976Sjmallett#endif 645215976Sjmallett } cn52xx; 646215976Sjmallett struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1; 647215976Sjmallett struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx; 648215976Sjmallett struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1; 649232812Sjmallett struct cvmx_pcsxx_int_en_reg_s cn61xx; 650215976Sjmallett struct cvmx_pcsxx_int_en_reg_s cn63xx; 651215976Sjmallett struct cvmx_pcsxx_int_en_reg_s cn63xxp1; 652232812Sjmallett struct cvmx_pcsxx_int_en_reg_s cn66xx; 653232812Sjmallett struct cvmx_pcsxx_int_en_reg_s cn68xx; 654232812Sjmallett struct cvmx_pcsxx_int_en_reg_s cn68xxp1; 655215976Sjmallett}; 656215976Sjmalletttypedef union cvmx_pcsxx_int_en_reg cvmx_pcsxx_int_en_reg_t; 657215976Sjmallett 658215976Sjmallett/** 659215976Sjmallett * cvmx_pcsx#_int_reg 660215976Sjmallett * 661215976Sjmallett * PCSX Interrupt Register 662215976Sjmallett * 663215976Sjmallett */ 664232812Sjmallettunion cvmx_pcsxx_int_reg { 665215976Sjmallett uint64_t u64; 666232812Sjmallett struct cvmx_pcsxx_int_reg_s { 667232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 668215976Sjmallett uint64_t reserved_7_63 : 57; 669215976Sjmallett uint64_t dbg_sync : 1; /**< Code Group sync failure debug help, see Note below */ 670215976Sjmallett uint64_t algnlos : 1; /**< Set when XAUI lanes lose alignment */ 671215976Sjmallett uint64_t synlos : 1; /**< Set when Code group sync lost on 1 or more lanes */ 672215976Sjmallett uint64_t bitlckls : 1; /**< Set when Bit lock lost on 1 or more xaui lanes */ 673215976Sjmallett uint64_t rxsynbad : 1; /**< Set when RX code grp sync st machine in bad state 674215976Sjmallett in one of the 4 xaui lanes */ 675215976Sjmallett uint64_t rxbad : 1; /**< Set when RX state machine in bad state */ 676215976Sjmallett uint64_t txflt : 1; /**< None defined at this time, always 0x0 */ 677215976Sjmallett#else 678215976Sjmallett uint64_t txflt : 1; 679215976Sjmallett uint64_t rxbad : 1; 680215976Sjmallett uint64_t rxsynbad : 1; 681215976Sjmallett uint64_t bitlckls : 1; 682215976Sjmallett uint64_t synlos : 1; 683215976Sjmallett uint64_t algnlos : 1; 684215976Sjmallett uint64_t dbg_sync : 1; 685215976Sjmallett uint64_t reserved_7_63 : 57; 686215976Sjmallett#endif 687215976Sjmallett } s; 688232812Sjmallett struct cvmx_pcsxx_int_reg_cn52xx { 689232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 690215976Sjmallett uint64_t reserved_6_63 : 58; 691215976Sjmallett uint64_t algnlos : 1; /**< Set when XAUI lanes lose alignment */ 692215976Sjmallett uint64_t synlos : 1; /**< Set when Code group sync lost on 1 or more lanes */ 693215976Sjmallett uint64_t bitlckls : 1; /**< Set when Bit lock lost on 1 or more xaui lanes */ 694215976Sjmallett uint64_t rxsynbad : 1; /**< Set when RX code grp sync st machine in bad state 695215976Sjmallett in one of the 4 xaui lanes */ 696215976Sjmallett uint64_t rxbad : 1; /**< Set when RX state machine in bad state */ 697215976Sjmallett uint64_t txflt : 1; /**< None defined at this time, always 0x0 */ 698215976Sjmallett#else 699215976Sjmallett uint64_t txflt : 1; 700215976Sjmallett uint64_t rxbad : 1; 701215976Sjmallett uint64_t rxsynbad : 1; 702215976Sjmallett uint64_t bitlckls : 1; 703215976Sjmallett uint64_t synlos : 1; 704215976Sjmallett uint64_t algnlos : 1; 705215976Sjmallett uint64_t reserved_6_63 : 58; 706215976Sjmallett#endif 707215976Sjmallett } cn52xx; 708215976Sjmallett struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1; 709215976Sjmallett struct cvmx_pcsxx_int_reg_cn52xx cn56xx; 710215976Sjmallett struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1; 711232812Sjmallett struct cvmx_pcsxx_int_reg_s cn61xx; 712215976Sjmallett struct cvmx_pcsxx_int_reg_s cn63xx; 713215976Sjmallett struct cvmx_pcsxx_int_reg_s cn63xxp1; 714232812Sjmallett struct cvmx_pcsxx_int_reg_s cn66xx; 715232812Sjmallett struct cvmx_pcsxx_int_reg_s cn68xx; 716232812Sjmallett struct cvmx_pcsxx_int_reg_s cn68xxp1; 717215976Sjmallett}; 718215976Sjmalletttypedef union cvmx_pcsxx_int_reg cvmx_pcsxx_int_reg_t; 719215976Sjmallett 720215976Sjmallett/** 721215976Sjmallett * cvmx_pcsx#_log_anl_reg 722215976Sjmallett * 723215976Sjmallett * PCSX Logic Analyzer Register 724215976Sjmallett * 725215976Sjmallett */ 726232812Sjmallettunion cvmx_pcsxx_log_anl_reg { 727215976Sjmallett uint64_t u64; 728232812Sjmallett struct cvmx_pcsxx_log_anl_reg_s { 729232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 730215976Sjmallett uint64_t reserved_7_63 : 57; 731215976Sjmallett uint64_t enc_mode : 1; /**< 1=send xaui encoded data, 0=send xaui raw data to GMX 732215976Sjmallett See .../rtl/pcs/readme_logic_analyzer.txt for details */ 733215976Sjmallett uint64_t drop_ln : 2; /**< xaui lane# to drop from logic analyzer packets 734215976Sjmallett [<5>, <4>] Drop lane \# 735215976Sjmallett 0 0 Drop lane 0 data 736215976Sjmallett 0 1 Drop lane 1 data 737215976Sjmallett 1 0 Drop lane 2 data 738215976Sjmallett 1 1 Drop lane 3 data */ 739215976Sjmallett uint64_t lafifovfl : 1; /**< 1=logic analyser fif overflowed one or more times 740215976Sjmallett during packetization. 741215976Sjmallett Write 1 to clear this bit */ 742215976Sjmallett uint64_t la_en : 1; /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */ 743215976Sjmallett uint64_t pkt_sz : 2; /**< [<1>, <0>] Logic Analyzer Packet Size 744215976Sjmallett 0 0 Packet size 1k bytes 745215976Sjmallett 0 1 Packet size 4k bytes 746215976Sjmallett 1 0 Packet size 8k bytes 747215976Sjmallett 1 1 Packet size 16k bytes */ 748215976Sjmallett#else 749215976Sjmallett uint64_t pkt_sz : 2; 750215976Sjmallett uint64_t la_en : 1; 751215976Sjmallett uint64_t lafifovfl : 1; 752215976Sjmallett uint64_t drop_ln : 2; 753215976Sjmallett uint64_t enc_mode : 1; 754215976Sjmallett uint64_t reserved_7_63 : 57; 755215976Sjmallett#endif 756215976Sjmallett } s; 757215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn52xx; 758215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; 759215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn56xx; 760215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; 761232812Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn61xx; 762215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn63xx; 763215976Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn63xxp1; 764232812Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn66xx; 765232812Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn68xx; 766232812Sjmallett struct cvmx_pcsxx_log_anl_reg_s cn68xxp1; 767215976Sjmallett}; 768215976Sjmalletttypedef union cvmx_pcsxx_log_anl_reg cvmx_pcsxx_log_anl_reg_t; 769215976Sjmallett 770215976Sjmallett/** 771215976Sjmallett * cvmx_pcsx#_misc_ctl_reg 772215976Sjmallett * 773215976Sjmallett * RX lane polarity vector [3:0] = XOR_RXPLRT<9:6> ^ [4[RXPLRT<1>]]; 774215976Sjmallett * 775215976Sjmallett * TX lane polarity vector [3:0] = XOR_TXPLRT<5:2> ^ [4[TXPLRT<0>]]; 776215976Sjmallett * 777215976Sjmallett * In short keep <1:0> to 2'b00, and use <5:2> and <9:6> fields to define per lane polarities 778215976Sjmallett * 779215976Sjmallett * 780215976Sjmallett * 781215976Sjmallett * PCSX Misc Control Register 782215976Sjmallett */ 783232812Sjmallettunion cvmx_pcsxx_misc_ctl_reg { 784215976Sjmallett uint64_t u64; 785232812Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s { 786232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 787215976Sjmallett uint64_t reserved_4_63 : 60; 788215976Sjmallett uint64_t tx_swap : 1; /**< 0=do not swap xaui lanes going out to qlm's 789215976Sjmallett 1=swap lanes 3 <-> 0 and 2 <-> 1 */ 790215976Sjmallett uint64_t rx_swap : 1; /**< 0=do not swap xaui lanes coming in from qlm's 791215976Sjmallett 1=swap lanes 3 <-> 0 and 2 <-> 1 */ 792215976Sjmallett uint64_t xaui : 1; /**< 1=XAUI mode selected, 0=not XAUI mode selected 793215976Sjmallett This bit represents pi_qlm1/3_cfg[1:0] pin status */ 794215976Sjmallett uint64_t gmxeno : 1; /**< GMX port enable override, GMX en/dis status is held 795215976Sjmallett during data packet reception. */ 796215976Sjmallett#else 797215976Sjmallett uint64_t gmxeno : 1; 798215976Sjmallett uint64_t xaui : 1; 799215976Sjmallett uint64_t rx_swap : 1; 800215976Sjmallett uint64_t tx_swap : 1; 801215976Sjmallett uint64_t reserved_4_63 : 60; 802215976Sjmallett#endif 803215976Sjmallett } s; 804215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; 805215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; 806215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; 807215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; 808232812Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn61xx; 809215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn63xx; 810215976Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1; 811232812Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn66xx; 812232812Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn68xx; 813232812Sjmallett struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1; 814215976Sjmallett}; 815215976Sjmalletttypedef union cvmx_pcsxx_misc_ctl_reg cvmx_pcsxx_misc_ctl_reg_t; 816215976Sjmallett 817215976Sjmallett/** 818215976Sjmallett * cvmx_pcsx#_rx_sync_states_reg 819215976Sjmallett * 820215976Sjmallett * PCSX_RX_SYNC_STATES_REG = Receive Sync States Register 821215976Sjmallett * 822215976Sjmallett */ 823232812Sjmallettunion cvmx_pcsxx_rx_sync_states_reg { 824215976Sjmallett uint64_t u64; 825232812Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s { 826232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 827215976Sjmallett uint64_t reserved_16_63 : 48; 828215976Sjmallett uint64_t sync3st : 4; /**< Receive lane 3 code grp sync state machine state */ 829215976Sjmallett uint64_t sync2st : 4; /**< Receive lane 2 code grp sync state machine state */ 830215976Sjmallett uint64_t sync1st : 4; /**< Receive lane 1 code grp sync state machine state */ 831215976Sjmallett uint64_t sync0st : 4; /**< Receive lane 0 code grp sync state machine state */ 832215976Sjmallett#else 833215976Sjmallett uint64_t sync0st : 4; 834215976Sjmallett uint64_t sync1st : 4; 835215976Sjmallett uint64_t sync2st : 4; 836215976Sjmallett uint64_t sync3st : 4; 837215976Sjmallett uint64_t reserved_16_63 : 48; 838215976Sjmallett#endif 839215976Sjmallett } s; 840215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; 841215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; 842215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; 843215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; 844232812Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx; 845215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx; 846215976Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1; 847232812Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx; 848232812Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx; 849232812Sjmallett struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1; 850215976Sjmallett}; 851215976Sjmalletttypedef union cvmx_pcsxx_rx_sync_states_reg cvmx_pcsxx_rx_sync_states_reg_t; 852215976Sjmallett 853215976Sjmallett/** 854215976Sjmallett * cvmx_pcsx#_spd_abil_reg 855215976Sjmallett * 856215976Sjmallett * PCSX_SPD_ABIL_REG = Speed ability register 857215976Sjmallett * 858215976Sjmallett */ 859232812Sjmallettunion cvmx_pcsxx_spd_abil_reg { 860215976Sjmallett uint64_t u64; 861232812Sjmallett struct cvmx_pcsxx_spd_abil_reg_s { 862232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 863215976Sjmallett uint64_t reserved_2_63 : 62; 864215976Sjmallett uint64_t tenpasst : 1; /**< Always 0, no 10PASS-TS/2BASE-TL capability support */ 865215976Sjmallett uint64_t tengb : 1; /**< Always 1, 10Gb/s supported */ 866215976Sjmallett#else 867215976Sjmallett uint64_t tengb : 1; 868215976Sjmallett uint64_t tenpasst : 1; 869215976Sjmallett uint64_t reserved_2_63 : 62; 870215976Sjmallett#endif 871215976Sjmallett } s; 872215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn52xx; 873215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; 874215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn56xx; 875215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; 876232812Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn61xx; 877215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn63xx; 878215976Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1; 879232812Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn66xx; 880232812Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn68xx; 881232812Sjmallett struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1; 882215976Sjmallett}; 883215976Sjmalletttypedef union cvmx_pcsxx_spd_abil_reg cvmx_pcsxx_spd_abil_reg_t; 884215976Sjmallett 885215976Sjmallett/** 886215976Sjmallett * cvmx_pcsx#_status1_reg 887215976Sjmallett * 888215976Sjmallett * PCSX_STATUS1_REG = Status Register1 889215976Sjmallett * 890215976Sjmallett */ 891232812Sjmallettunion cvmx_pcsxx_status1_reg { 892215976Sjmallett uint64_t u64; 893232812Sjmallett struct cvmx_pcsxx_status1_reg_s { 894232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 895215976Sjmallett uint64_t reserved_8_63 : 56; 896215976Sjmallett uint64_t flt : 1; /**< 1=Fault condition detected, 0=No fault condition 897215976Sjmallett This bit is a logical OR of Status2 reg bits 11,10 */ 898215976Sjmallett uint64_t reserved_3_6 : 4; 899215976Sjmallett uint64_t rcv_lnk : 1; /**< 1=Receive Link up, 0=Receive Link down 900215976Sjmallett Latching Low version of r_10gbx_status_reg[12], 901215976Sjmallett Link down status continues until SW read. */ 902215976Sjmallett uint64_t lpable : 1; /**< Always set to 1 for Low Power ablility indication */ 903215976Sjmallett uint64_t reserved_0_0 : 1; 904215976Sjmallett#else 905215976Sjmallett uint64_t reserved_0_0 : 1; 906215976Sjmallett uint64_t lpable : 1; 907215976Sjmallett uint64_t rcv_lnk : 1; 908215976Sjmallett uint64_t reserved_3_6 : 4; 909215976Sjmallett uint64_t flt : 1; 910215976Sjmallett uint64_t reserved_8_63 : 56; 911215976Sjmallett#endif 912215976Sjmallett } s; 913215976Sjmallett struct cvmx_pcsxx_status1_reg_s cn52xx; 914215976Sjmallett struct cvmx_pcsxx_status1_reg_s cn52xxp1; 915215976Sjmallett struct cvmx_pcsxx_status1_reg_s cn56xx; 916215976Sjmallett struct cvmx_pcsxx_status1_reg_s cn56xxp1; 917232812Sjmallett struct cvmx_pcsxx_status1_reg_s cn61xx; 918215976Sjmallett struct cvmx_pcsxx_status1_reg_s cn63xx; 919215976Sjmallett struct cvmx_pcsxx_status1_reg_s cn63xxp1; 920232812Sjmallett struct cvmx_pcsxx_status1_reg_s cn66xx; 921232812Sjmallett struct cvmx_pcsxx_status1_reg_s cn68xx; 922232812Sjmallett struct cvmx_pcsxx_status1_reg_s cn68xxp1; 923215976Sjmallett}; 924215976Sjmalletttypedef union cvmx_pcsxx_status1_reg cvmx_pcsxx_status1_reg_t; 925215976Sjmallett 926215976Sjmallett/** 927215976Sjmallett * cvmx_pcsx#_status2_reg 928215976Sjmallett * 929215976Sjmallett * PCSX_STATUS2_REG = Status Register2 930215976Sjmallett * 931215976Sjmallett */ 932232812Sjmallettunion cvmx_pcsxx_status2_reg { 933215976Sjmallett uint64_t u64; 934232812Sjmallett struct cvmx_pcsxx_status2_reg_s { 935232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 936215976Sjmallett uint64_t reserved_16_63 : 48; 937215976Sjmallett uint64_t dev : 2; /**< Always at 2'b10, means a Device present at the addr */ 938215976Sjmallett uint64_t reserved_12_13 : 2; 939215976Sjmallett uint64_t xmtflt : 1; /**< 0=No xmit fault, 1=xmit fault. Implements latching 940215976Sjmallett High function until SW read. */ 941215976Sjmallett uint64_t rcvflt : 1; /**< 0=No rcv fault, 1=rcv fault. Implements latching 942215976Sjmallett High function until SW read */ 943215976Sjmallett uint64_t reserved_3_9 : 7; 944215976Sjmallett uint64_t tengb_w : 1; /**< Always 0, no 10GBASE-W capability */ 945215976Sjmallett uint64_t tengb_x : 1; /**< Always 1, 10GBASE-X capable */ 946215976Sjmallett uint64_t tengb_r : 1; /**< Always 0, no 10GBASE-R capability */ 947215976Sjmallett#else 948215976Sjmallett uint64_t tengb_r : 1; 949215976Sjmallett uint64_t tengb_x : 1; 950215976Sjmallett uint64_t tengb_w : 1; 951215976Sjmallett uint64_t reserved_3_9 : 7; 952215976Sjmallett uint64_t rcvflt : 1; 953215976Sjmallett uint64_t xmtflt : 1; 954215976Sjmallett uint64_t reserved_12_13 : 2; 955215976Sjmallett uint64_t dev : 2; 956215976Sjmallett uint64_t reserved_16_63 : 48; 957215976Sjmallett#endif 958215976Sjmallett } s; 959215976Sjmallett struct cvmx_pcsxx_status2_reg_s cn52xx; 960215976Sjmallett struct cvmx_pcsxx_status2_reg_s cn52xxp1; 961215976Sjmallett struct cvmx_pcsxx_status2_reg_s cn56xx; 962215976Sjmallett struct cvmx_pcsxx_status2_reg_s cn56xxp1; 963232812Sjmallett struct cvmx_pcsxx_status2_reg_s cn61xx; 964215976Sjmallett struct cvmx_pcsxx_status2_reg_s cn63xx; 965215976Sjmallett struct cvmx_pcsxx_status2_reg_s cn63xxp1; 966232812Sjmallett struct cvmx_pcsxx_status2_reg_s cn66xx; 967232812Sjmallett struct cvmx_pcsxx_status2_reg_s cn68xx; 968232812Sjmallett struct cvmx_pcsxx_status2_reg_s cn68xxp1; 969215976Sjmallett}; 970215976Sjmalletttypedef union cvmx_pcsxx_status2_reg cvmx_pcsxx_status2_reg_t; 971215976Sjmallett 972215976Sjmallett/** 973215976Sjmallett * cvmx_pcsx#_tx_rx_polarity_reg 974215976Sjmallett * 975215976Sjmallett * PCSX_POLARITY_REG = TX_RX polarity reg 976215976Sjmallett * 977215976Sjmallett */ 978232812Sjmallettunion cvmx_pcsxx_tx_rx_polarity_reg { 979215976Sjmallett uint64_t u64; 980232812Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s { 981232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 982215976Sjmallett uint64_t reserved_10_63 : 54; 983215976Sjmallett uint64_t xor_rxplrt : 4; /**< Per lane RX polarity control */ 984215976Sjmallett uint64_t xor_txplrt : 4; /**< Per lane TX polarity control */ 985215976Sjmallett uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 986215976Sjmallett uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 987215976Sjmallett#else 988215976Sjmallett uint64_t txplrt : 1; 989215976Sjmallett uint64_t rxplrt : 1; 990215976Sjmallett uint64_t xor_txplrt : 4; 991215976Sjmallett uint64_t xor_rxplrt : 4; 992215976Sjmallett uint64_t reserved_10_63 : 54; 993215976Sjmallett#endif 994215976Sjmallett } s; 995215976Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; 996232812Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { 997232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 998215976Sjmallett uint64_t reserved_2_63 : 62; 999215976Sjmallett uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 1000215976Sjmallett uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */ 1001215976Sjmallett#else 1002215976Sjmallett uint64_t txplrt : 1; 1003215976Sjmallett uint64_t rxplrt : 1; 1004215976Sjmallett uint64_t reserved_2_63 : 62; 1005215976Sjmallett#endif 1006215976Sjmallett } cn52xxp1; 1007215976Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; 1008215976Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; 1009232812Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx; 1010215976Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx; 1011215976Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1; 1012232812Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx; 1013232812Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx; 1014232812Sjmallett struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1; 1015215976Sjmallett}; 1016215976Sjmalletttypedef union cvmx_pcsxx_tx_rx_polarity_reg cvmx_pcsxx_tx_rx_polarity_reg_t; 1017215976Sjmallett 1018215976Sjmallett/** 1019215976Sjmallett * cvmx_pcsx#_tx_rx_states_reg 1020215976Sjmallett * 1021215976Sjmallett * PCSX_TX_RX_STATES_REG = Transmit Receive States Register 1022215976Sjmallett * 1023215976Sjmallett */ 1024232812Sjmallettunion cvmx_pcsxx_tx_rx_states_reg { 1025215976Sjmallett uint64_t u64; 1026232812Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s { 1027232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1028215976Sjmallett uint64_t reserved_14_63 : 50; 1029215976Sjmallett uint64_t term_err : 1; /**< 1=Check end function detected error in packet 1030215976Sjmallett terminate ||T|| column or the one after it */ 1031215976Sjmallett uint64_t syn3bad : 1; /**< 1=lane 3 code grp sync state machine in bad state */ 1032215976Sjmallett uint64_t syn2bad : 1; /**< 1=lane 2 code grp sync state machine in bad state */ 1033215976Sjmallett uint64_t syn1bad : 1; /**< 1=lane 1 code grp sync state machine in bad state */ 1034215976Sjmallett uint64_t syn0bad : 1; /**< 1=lane 0 code grp sync state machine in bad state */ 1035215976Sjmallett uint64_t rxbad : 1; /**< 1=Rcv state machine in a bad state, HW malfunction */ 1036215976Sjmallett uint64_t algn_st : 3; /**< Lane alignment state machine state state */ 1037215976Sjmallett uint64_t rx_st : 2; /**< Receive state machine state state */ 1038215976Sjmallett uint64_t tx_st : 3; /**< Transmit state machine state state */ 1039215976Sjmallett#else 1040215976Sjmallett uint64_t tx_st : 3; 1041215976Sjmallett uint64_t rx_st : 2; 1042215976Sjmallett uint64_t algn_st : 3; 1043215976Sjmallett uint64_t rxbad : 1; 1044215976Sjmallett uint64_t syn0bad : 1; 1045215976Sjmallett uint64_t syn1bad : 1; 1046215976Sjmallett uint64_t syn2bad : 1; 1047215976Sjmallett uint64_t syn3bad : 1; 1048215976Sjmallett uint64_t term_err : 1; 1049215976Sjmallett uint64_t reserved_14_63 : 50; 1050215976Sjmallett#endif 1051215976Sjmallett } s; 1052215976Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; 1053232812Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { 1054232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1055215976Sjmallett uint64_t reserved_13_63 : 51; 1056215976Sjmallett uint64_t syn3bad : 1; /**< 1=lane 3 code grp sync state machine in bad state */ 1057215976Sjmallett uint64_t syn2bad : 1; /**< 1=lane 2 code grp sync state machine in bad state */ 1058215976Sjmallett uint64_t syn1bad : 1; /**< 1=lane 1 code grp sync state machine in bad state */ 1059215976Sjmallett uint64_t syn0bad : 1; /**< 1=lane 0 code grp sync state machine in bad state */ 1060215976Sjmallett uint64_t rxbad : 1; /**< 1=Rcv state machine in a bad state, HW malfunction */ 1061215976Sjmallett uint64_t algn_st : 3; /**< Lane alignment state machine state state */ 1062215976Sjmallett uint64_t rx_st : 2; /**< Receive state machine state state */ 1063215976Sjmallett uint64_t tx_st : 3; /**< Transmit state machine state state */ 1064215976Sjmallett#else 1065215976Sjmallett uint64_t tx_st : 3; 1066215976Sjmallett uint64_t rx_st : 2; 1067215976Sjmallett uint64_t algn_st : 3; 1068215976Sjmallett uint64_t rxbad : 1; 1069215976Sjmallett uint64_t syn0bad : 1; 1070215976Sjmallett uint64_t syn1bad : 1; 1071215976Sjmallett uint64_t syn2bad : 1; 1072215976Sjmallett uint64_t syn3bad : 1; 1073215976Sjmallett uint64_t reserved_13_63 : 51; 1074215976Sjmallett#endif 1075215976Sjmallett } cn52xxp1; 1076215976Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; 1077215976Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; 1078232812Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx; 1079215976Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx; 1080215976Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1; 1081232812Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx; 1082232812Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx; 1083232812Sjmallett struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1; 1084215976Sjmallett}; 1085215976Sjmalletttypedef union cvmx_pcsxx_tx_rx_states_reg cvmx_pcsxx_tx_rx_states_reg_t; 1086215976Sjmallett 1087215976Sjmallett#endif 1088