1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-led-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon led. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_LED_DEFS_H__ 53232812Sjmallett#define __CVMX_LED_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallett#define CVMX_LED_BLINK CVMX_LED_BLINK_FUNC() 57215976Sjmallettstatic inline uint64_t CVMX_LED_BLINK_FUNC(void) 58215976Sjmallett{ 59215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 60215976Sjmallett cvmx_warn("CVMX_LED_BLINK not supported on this chip\n"); 61215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001A48ull); 62215976Sjmallett} 63215976Sjmallett#else 64215976Sjmallett#define CVMX_LED_BLINK (CVMX_ADD_IO_SEG(0x0001180000001A48ull)) 65215976Sjmallett#endif 66215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67215976Sjmallett#define CVMX_LED_CLK_PHASE CVMX_LED_CLK_PHASE_FUNC() 68215976Sjmallettstatic inline uint64_t CVMX_LED_CLK_PHASE_FUNC(void) 69215976Sjmallett{ 70215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 71215976Sjmallett cvmx_warn("CVMX_LED_CLK_PHASE not supported on this chip\n"); 72215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001A08ull); 73215976Sjmallett} 74215976Sjmallett#else 75215976Sjmallett#define CVMX_LED_CLK_PHASE (CVMX_ADD_IO_SEG(0x0001180000001A08ull)) 76215976Sjmallett#endif 77215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78215976Sjmallett#define CVMX_LED_CYLON CVMX_LED_CYLON_FUNC() 79215976Sjmallettstatic inline uint64_t CVMX_LED_CYLON_FUNC(void) 80215976Sjmallett{ 81215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 82215976Sjmallett cvmx_warn("CVMX_LED_CYLON not supported on this chip\n"); 83215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001AF8ull); 84215976Sjmallett} 85215976Sjmallett#else 86215976Sjmallett#define CVMX_LED_CYLON (CVMX_ADD_IO_SEG(0x0001180000001AF8ull)) 87215976Sjmallett#endif 88215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 89215976Sjmallett#define CVMX_LED_DBG CVMX_LED_DBG_FUNC() 90215976Sjmallettstatic inline uint64_t CVMX_LED_DBG_FUNC(void) 91215976Sjmallett{ 92215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 93215976Sjmallett cvmx_warn("CVMX_LED_DBG not supported on this chip\n"); 94215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001A18ull); 95215976Sjmallett} 96215976Sjmallett#else 97215976Sjmallett#define CVMX_LED_DBG (CVMX_ADD_IO_SEG(0x0001180000001A18ull)) 98215976Sjmallett#endif 99215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100215976Sjmallett#define CVMX_LED_EN CVMX_LED_EN_FUNC() 101215976Sjmallettstatic inline uint64_t CVMX_LED_EN_FUNC(void) 102215976Sjmallett{ 103215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 104215976Sjmallett cvmx_warn("CVMX_LED_EN not supported on this chip\n"); 105215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001A00ull); 106215976Sjmallett} 107215976Sjmallett#else 108215976Sjmallett#define CVMX_LED_EN (CVMX_ADD_IO_SEG(0x0001180000001A00ull)) 109215976Sjmallett#endif 110215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 111215976Sjmallett#define CVMX_LED_POLARITY CVMX_LED_POLARITY_FUNC() 112215976Sjmallettstatic inline uint64_t CVMX_LED_POLARITY_FUNC(void) 113215976Sjmallett{ 114215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 115215976Sjmallett cvmx_warn("CVMX_LED_POLARITY not supported on this chip\n"); 116215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001A50ull); 117215976Sjmallett} 118215976Sjmallett#else 119215976Sjmallett#define CVMX_LED_POLARITY (CVMX_ADD_IO_SEG(0x0001180000001A50ull)) 120215976Sjmallett#endif 121215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 122215976Sjmallett#define CVMX_LED_PRT CVMX_LED_PRT_FUNC() 123215976Sjmallettstatic inline uint64_t CVMX_LED_PRT_FUNC(void) 124215976Sjmallett{ 125215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 126215976Sjmallett cvmx_warn("CVMX_LED_PRT not supported on this chip\n"); 127215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001A10ull); 128215976Sjmallett} 129215976Sjmallett#else 130215976Sjmallett#define CVMX_LED_PRT (CVMX_ADD_IO_SEG(0x0001180000001A10ull)) 131215976Sjmallett#endif 132215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 133215976Sjmallett#define CVMX_LED_PRT_FMT CVMX_LED_PRT_FMT_FUNC() 134215976Sjmallettstatic inline uint64_t CVMX_LED_PRT_FMT_FUNC(void) 135215976Sjmallett{ 136215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 137215976Sjmallett cvmx_warn("CVMX_LED_PRT_FMT not supported on this chip\n"); 138215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001A30ull); 139215976Sjmallett} 140215976Sjmallett#else 141215976Sjmallett#define CVMX_LED_PRT_FMT (CVMX_ADD_IO_SEG(0x0001180000001A30ull)) 142215976Sjmallett#endif 143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 144215976Sjmallettstatic inline uint64_t CVMX_LED_PRT_STATUSX(unsigned long offset) 145215976Sjmallett{ 146215976Sjmallett if (!( 147215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) || 148215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) || 149215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))))) 150215976Sjmallett cvmx_warn("CVMX_LED_PRT_STATUSX(%lu) is invalid on this chip\n", offset); 151215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8; 152215976Sjmallett} 153215976Sjmallett#else 154215976Sjmallett#define CVMX_LED_PRT_STATUSX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A80ull) + ((offset) & 7) * 8) 155215976Sjmallett#endif 156215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 157215976Sjmallettstatic inline uint64_t CVMX_LED_UDD_CNTX(unsigned long offset) 158215976Sjmallett{ 159215976Sjmallett if (!( 160215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 161215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 162215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 163215976Sjmallett cvmx_warn("CVMX_LED_UDD_CNTX(%lu) is invalid on this chip\n", offset); 164215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8; 165215976Sjmallett} 166215976Sjmallett#else 167215976Sjmallett#define CVMX_LED_UDD_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A20ull) + ((offset) & 1) * 8) 168215976Sjmallett#endif 169215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 170215976Sjmallettstatic inline uint64_t CVMX_LED_UDD_DATX(unsigned long offset) 171215976Sjmallett{ 172215976Sjmallett if (!( 173215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 174215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 175215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 176215976Sjmallett cvmx_warn("CVMX_LED_UDD_DATX(%lu) is invalid on this chip\n", offset); 177215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8; 178215976Sjmallett} 179215976Sjmallett#else 180215976Sjmallett#define CVMX_LED_UDD_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001A38ull) + ((offset) & 1) * 8) 181215976Sjmallett#endif 182215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 183215976Sjmallettstatic inline uint64_t CVMX_LED_UDD_DAT_CLRX(unsigned long offset) 184215976Sjmallett{ 185215976Sjmallett if (!( 186215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 187215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 188215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 189215976Sjmallett cvmx_warn("CVMX_LED_UDD_DAT_CLRX(%lu) is invalid on this chip\n", offset); 190215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16; 191215976Sjmallett} 192215976Sjmallett#else 193215976Sjmallett#define CVMX_LED_UDD_DAT_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC8ull) + ((offset) & 1) * 16) 194215976Sjmallett#endif 195215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 196215976Sjmallettstatic inline uint64_t CVMX_LED_UDD_DAT_SETX(unsigned long offset) 197215976Sjmallett{ 198215976Sjmallett if (!( 199215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) || 200215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) || 201215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))))) 202215976Sjmallett cvmx_warn("CVMX_LED_UDD_DAT_SETX(%lu) is invalid on this chip\n", offset); 203215976Sjmallett return CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16; 204215976Sjmallett} 205215976Sjmallett#else 206215976Sjmallett#define CVMX_LED_UDD_DAT_SETX(offset) (CVMX_ADD_IO_SEG(0x0001180000001AC0ull) + ((offset) & 1) * 16) 207215976Sjmallett#endif 208215976Sjmallett 209215976Sjmallett/** 210215976Sjmallett * cvmx_led_blink 211215976Sjmallett * 212215976Sjmallett * LED_BLINK = LED Blink Rate (in led_clks) 213215976Sjmallett * 214215976Sjmallett */ 215232812Sjmallettunion cvmx_led_blink { 216215976Sjmallett uint64_t u64; 217232812Sjmallett struct cvmx_led_blink_s { 218232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 219215976Sjmallett uint64_t reserved_8_63 : 56; 220215976Sjmallett uint64_t rate : 8; /**< LED Blink rate in led_latch clks 221215976Sjmallett RATE must be > 0 */ 222215976Sjmallett#else 223215976Sjmallett uint64_t rate : 8; 224215976Sjmallett uint64_t reserved_8_63 : 56; 225215976Sjmallett#endif 226215976Sjmallett } s; 227215976Sjmallett struct cvmx_led_blink_s cn38xx; 228215976Sjmallett struct cvmx_led_blink_s cn38xxp2; 229215976Sjmallett struct cvmx_led_blink_s cn56xx; 230215976Sjmallett struct cvmx_led_blink_s cn56xxp1; 231215976Sjmallett struct cvmx_led_blink_s cn58xx; 232215976Sjmallett struct cvmx_led_blink_s cn58xxp1; 233215976Sjmallett}; 234215976Sjmalletttypedef union cvmx_led_blink cvmx_led_blink_t; 235215976Sjmallett 236215976Sjmallett/** 237215976Sjmallett * cvmx_led_clk_phase 238215976Sjmallett * 239215976Sjmallett * LED_CLK_PHASE = LED Clock Phase (in 64 eclks) 240215976Sjmallett * 241215976Sjmallett * 242215976Sjmallett * Notes: 243215976Sjmallett * Example: 244215976Sjmallett * Given a 2ns eclk, an LED_CLK_PHASE[PHASE] = 1, indicates that each 245215976Sjmallett * led_clk phase is 64 eclks, or 128ns. The led_clk period is 2*phase, 246215976Sjmallett * or 256ns which is 3.9MHz. The default value of 4, yields an led_clk 247215976Sjmallett * period of 64*4*2ns*2 = 1024ns or ~1MHz (977KHz). 248215976Sjmallett */ 249232812Sjmallettunion cvmx_led_clk_phase { 250215976Sjmallett uint64_t u64; 251232812Sjmallett struct cvmx_led_clk_phase_s { 252232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 253215976Sjmallett uint64_t reserved_7_63 : 57; 254215976Sjmallett uint64_t phase : 7; /**< Number of 64 eclks in order to create the led_clk */ 255215976Sjmallett#else 256215976Sjmallett uint64_t phase : 7; 257215976Sjmallett uint64_t reserved_7_63 : 57; 258215976Sjmallett#endif 259215976Sjmallett } s; 260215976Sjmallett struct cvmx_led_clk_phase_s cn38xx; 261215976Sjmallett struct cvmx_led_clk_phase_s cn38xxp2; 262215976Sjmallett struct cvmx_led_clk_phase_s cn56xx; 263215976Sjmallett struct cvmx_led_clk_phase_s cn56xxp1; 264215976Sjmallett struct cvmx_led_clk_phase_s cn58xx; 265215976Sjmallett struct cvmx_led_clk_phase_s cn58xxp1; 266215976Sjmallett}; 267215976Sjmalletttypedef union cvmx_led_clk_phase cvmx_led_clk_phase_t; 268215976Sjmallett 269215976Sjmallett/** 270215976Sjmallett * cvmx_led_cylon 271215976Sjmallett * 272215976Sjmallett * LED_CYLON = LED CYLON Effect (should remain undocumented) 273215976Sjmallett * 274215976Sjmallett */ 275232812Sjmallettunion cvmx_led_cylon { 276215976Sjmallett uint64_t u64; 277232812Sjmallett struct cvmx_led_cylon_s { 278232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 279215976Sjmallett uint64_t reserved_16_63 : 48; 280215976Sjmallett uint64_t rate : 16; /**< LED Cylon Effect when RATE!=0 281215976Sjmallett Changes at RATE*LATCH period */ 282215976Sjmallett#else 283215976Sjmallett uint64_t rate : 16; 284215976Sjmallett uint64_t reserved_16_63 : 48; 285215976Sjmallett#endif 286215976Sjmallett } s; 287215976Sjmallett struct cvmx_led_cylon_s cn38xx; 288215976Sjmallett struct cvmx_led_cylon_s cn38xxp2; 289215976Sjmallett struct cvmx_led_cylon_s cn56xx; 290215976Sjmallett struct cvmx_led_cylon_s cn56xxp1; 291215976Sjmallett struct cvmx_led_cylon_s cn58xx; 292215976Sjmallett struct cvmx_led_cylon_s cn58xxp1; 293215976Sjmallett}; 294215976Sjmalletttypedef union cvmx_led_cylon cvmx_led_cylon_t; 295215976Sjmallett 296215976Sjmallett/** 297215976Sjmallett * cvmx_led_dbg 298215976Sjmallett * 299215976Sjmallett * LED_DBG = LED Debug Port information 300215976Sjmallett * 301215976Sjmallett */ 302232812Sjmallettunion cvmx_led_dbg { 303215976Sjmallett uint64_t u64; 304232812Sjmallett struct cvmx_led_dbg_s { 305232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 306215976Sjmallett uint64_t reserved_1_63 : 63; 307215976Sjmallett uint64_t dbg_en : 1; /**< Add Debug Port Data to the LED shift chain 308215976Sjmallett Debug Data is shifted out LSB to MSB */ 309215976Sjmallett#else 310215976Sjmallett uint64_t dbg_en : 1; 311215976Sjmallett uint64_t reserved_1_63 : 63; 312215976Sjmallett#endif 313215976Sjmallett } s; 314215976Sjmallett struct cvmx_led_dbg_s cn38xx; 315215976Sjmallett struct cvmx_led_dbg_s cn38xxp2; 316215976Sjmallett struct cvmx_led_dbg_s cn56xx; 317215976Sjmallett struct cvmx_led_dbg_s cn56xxp1; 318215976Sjmallett struct cvmx_led_dbg_s cn58xx; 319215976Sjmallett struct cvmx_led_dbg_s cn58xxp1; 320215976Sjmallett}; 321215976Sjmalletttypedef union cvmx_led_dbg cvmx_led_dbg_t; 322215976Sjmallett 323215976Sjmallett/** 324215976Sjmallett * cvmx_led_en 325215976Sjmallett * 326215976Sjmallett * LED_EN = LED Interface Enable 327215976Sjmallett * 328215976Sjmallett * 329215976Sjmallett * Notes: 330215976Sjmallett * The LED interface is comprised of a shift chain with a parallel latch. LED 331215976Sjmallett * data is shifted out on each fallingg edge of led_clk and then captured by 332215976Sjmallett * led_lat. 333215976Sjmallett * 334215976Sjmallett * The LED shift chain is comprised of the following... 335215976Sjmallett * 336215976Sjmallett * 32 - UDD header 337215976Sjmallett * 6x8 - per port status 338215976Sjmallett * 17 - debug port 339215976Sjmallett * 32 - UDD trailer 340215976Sjmallett * 341215976Sjmallett * for a total of 129 bits. 342215976Sjmallett * 343215976Sjmallett * UDD header is programmable from 0-32 bits (LED_UDD_CNT0) and will shift out 344215976Sjmallett * LSB to MSB (LED_UDD_DAT0[0], LED_UDD_DAT0[1], 345215976Sjmallett * ... LED_UDD_DAT0[LED_UDD_CNT0]. 346215976Sjmallett * 347215976Sjmallett * The per port status is also variable. Systems can control which ports send 348215976Sjmallett * data (LED_PRT) as well as the status content (LED_PRT_FMT and 349215976Sjmallett * LED_PRT_STATUS*). When multiple ports are enabled, they come out in lowest 350215976Sjmallett * port to highest port (prt0, prt1, ...). 351215976Sjmallett * 352215976Sjmallett * The debug port data can also be added to the LED chain (LED_DBG). When 353215976Sjmallett * enabled, the debug data shifts out LSB to MSB. 354215976Sjmallett * 355215976Sjmallett * The UDD trailer data is identical to the header data, but uses LED_UDD_CNT1 356215976Sjmallett * and LED_UDD_DAT1. 357215976Sjmallett */ 358232812Sjmallettunion cvmx_led_en { 359215976Sjmallett uint64_t u64; 360232812Sjmallett struct cvmx_led_en_s { 361232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 362215976Sjmallett uint64_t reserved_1_63 : 63; 363215976Sjmallett uint64_t en : 1; /**< Enable the LED interface shift-chain */ 364215976Sjmallett#else 365215976Sjmallett uint64_t en : 1; 366215976Sjmallett uint64_t reserved_1_63 : 63; 367215976Sjmallett#endif 368215976Sjmallett } s; 369215976Sjmallett struct cvmx_led_en_s cn38xx; 370215976Sjmallett struct cvmx_led_en_s cn38xxp2; 371215976Sjmallett struct cvmx_led_en_s cn56xx; 372215976Sjmallett struct cvmx_led_en_s cn56xxp1; 373215976Sjmallett struct cvmx_led_en_s cn58xx; 374215976Sjmallett struct cvmx_led_en_s cn58xxp1; 375215976Sjmallett}; 376215976Sjmalletttypedef union cvmx_led_en cvmx_led_en_t; 377215976Sjmallett 378215976Sjmallett/** 379215976Sjmallett * cvmx_led_polarity 380215976Sjmallett * 381215976Sjmallett * LED_POLARITY = LED Polarity 382215976Sjmallett * 383215976Sjmallett */ 384232812Sjmallettunion cvmx_led_polarity { 385215976Sjmallett uint64_t u64; 386232812Sjmallett struct cvmx_led_polarity_s { 387232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 388215976Sjmallett uint64_t reserved_1_63 : 63; 389215976Sjmallett uint64_t polarity : 1; /**< LED active polarity 390215976Sjmallett 0 = active HIGH LED 391215976Sjmallett 1 = active LOW LED (invert led_dat) */ 392215976Sjmallett#else 393215976Sjmallett uint64_t polarity : 1; 394215976Sjmallett uint64_t reserved_1_63 : 63; 395215976Sjmallett#endif 396215976Sjmallett } s; 397215976Sjmallett struct cvmx_led_polarity_s cn38xx; 398215976Sjmallett struct cvmx_led_polarity_s cn38xxp2; 399215976Sjmallett struct cvmx_led_polarity_s cn56xx; 400215976Sjmallett struct cvmx_led_polarity_s cn56xxp1; 401215976Sjmallett struct cvmx_led_polarity_s cn58xx; 402215976Sjmallett struct cvmx_led_polarity_s cn58xxp1; 403215976Sjmallett}; 404215976Sjmalletttypedef union cvmx_led_polarity cvmx_led_polarity_t; 405215976Sjmallett 406215976Sjmallett/** 407215976Sjmallett * cvmx_led_prt 408215976Sjmallett * 409215976Sjmallett * LED_PRT = LED Port status information 410215976Sjmallett * 411215976Sjmallett * 412215976Sjmallett * Notes: 413215976Sjmallett * Note: 414215976Sjmallett * the PRT vector enables information of the 8 RGMII ports connected to 415215976Sjmallett * Octane. It does not reflect the actual programmed PHY addresses. 416215976Sjmallett */ 417232812Sjmallettunion cvmx_led_prt { 418215976Sjmallett uint64_t u64; 419232812Sjmallett struct cvmx_led_prt_s { 420232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 421215976Sjmallett uint64_t reserved_8_63 : 56; 422215976Sjmallett uint64_t prt_en : 8; /**< Which ports are enabled to display status 423215976Sjmallett PRT_EN<3:0> coresponds to RGMII ports 3-0 on int0 424215976Sjmallett PRT_EN<7:4> coresponds to RGMII ports 7-4 on int1 425215976Sjmallett Only applies when interface is in RGMII mode 426215976Sjmallett The status format is defined by LED_PRT_FMT */ 427215976Sjmallett#else 428215976Sjmallett uint64_t prt_en : 8; 429215976Sjmallett uint64_t reserved_8_63 : 56; 430215976Sjmallett#endif 431215976Sjmallett } s; 432215976Sjmallett struct cvmx_led_prt_s cn38xx; 433215976Sjmallett struct cvmx_led_prt_s cn38xxp2; 434215976Sjmallett struct cvmx_led_prt_s cn56xx; 435215976Sjmallett struct cvmx_led_prt_s cn56xxp1; 436215976Sjmallett struct cvmx_led_prt_s cn58xx; 437215976Sjmallett struct cvmx_led_prt_s cn58xxp1; 438215976Sjmallett}; 439215976Sjmalletttypedef union cvmx_led_prt cvmx_led_prt_t; 440215976Sjmallett 441215976Sjmallett/** 442215976Sjmallett * cvmx_led_prt_fmt 443215976Sjmallett * 444215976Sjmallett * LED_PRT_FMT = LED Port Status Infomation Format 445215976Sjmallett * 446215976Sjmallett * 447215976Sjmallett * Notes: 448215976Sjmallett * TX: RGMII TX block is sending packet data or extends on the port 449215976Sjmallett * RX: RGMII RX block has received non-idle cycle 450215976Sjmallett * 451215976Sjmallett * For short transfers, LEDs will remain on for at least one blink cycle 452215976Sjmallett */ 453232812Sjmallettunion cvmx_led_prt_fmt { 454215976Sjmallett uint64_t u64; 455232812Sjmallett struct cvmx_led_prt_fmt_s { 456232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 457215976Sjmallett uint64_t reserved_4_63 : 60; 458215976Sjmallett uint64_t format : 4; /**< Port Status Information for each enabled port in 459215976Sjmallett LED_PRT. The formats are below 460215976Sjmallett 0x0: [ LED_PRT_STATUS[0] ] 461215976Sjmallett 0x1: [ LED_PRT_STATUS[1:0] ] 462215976Sjmallett 0x2: [ LED_PRT_STATUS[3:0] ] 463215976Sjmallett 0x3: [ LED_PRT_STATUS[5:0] ] 464215976Sjmallett 0x4: [ (RX|TX), LED_PRT_STATUS[0] ] 465215976Sjmallett 0x5: [ (RX|TX), LED_PRT_STATUS[1:0] ] 466215976Sjmallett 0x6: [ (RX|TX), LED_PRT_STATUS[3:0] ] 467215976Sjmallett 0x8: [ Tx, Rx, LED_PRT_STATUS[0] ] 468215976Sjmallett 0x9: [ Tx, Rx, LED_PRT_STATUS[1:0] ] 469215976Sjmallett 0xa: [ Tx, Rx, LED_PRT_STATUS[3:0] ] */ 470215976Sjmallett#else 471215976Sjmallett uint64_t format : 4; 472215976Sjmallett uint64_t reserved_4_63 : 60; 473215976Sjmallett#endif 474215976Sjmallett } s; 475215976Sjmallett struct cvmx_led_prt_fmt_s cn38xx; 476215976Sjmallett struct cvmx_led_prt_fmt_s cn38xxp2; 477215976Sjmallett struct cvmx_led_prt_fmt_s cn56xx; 478215976Sjmallett struct cvmx_led_prt_fmt_s cn56xxp1; 479215976Sjmallett struct cvmx_led_prt_fmt_s cn58xx; 480215976Sjmallett struct cvmx_led_prt_fmt_s cn58xxp1; 481215976Sjmallett}; 482215976Sjmalletttypedef union cvmx_led_prt_fmt cvmx_led_prt_fmt_t; 483215976Sjmallett 484215976Sjmallett/** 485215976Sjmallett * cvmx_led_prt_status# 486215976Sjmallett * 487215976Sjmallett * LED_PRT_STATUS = LED Port Status information 488215976Sjmallett * 489215976Sjmallett */ 490232812Sjmallettunion cvmx_led_prt_statusx { 491215976Sjmallett uint64_t u64; 492232812Sjmallett struct cvmx_led_prt_statusx_s { 493232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 494215976Sjmallett uint64_t reserved_6_63 : 58; 495215976Sjmallett uint64_t status : 6; /**< Bits that software can set to be added to the 496215976Sjmallett LED shift chain - depending on LED_PRT_FMT 497215976Sjmallett LED_PRT_STATUS(3..0) corespond to RGMII ports 3-0 498215976Sjmallett on interface0 499215976Sjmallett LED_PRT_STATUS(7..4) corespond to RGMII ports 7-4 500215976Sjmallett on interface1 501215976Sjmallett Only applies when interface is in RGMII mode */ 502215976Sjmallett#else 503215976Sjmallett uint64_t status : 6; 504215976Sjmallett uint64_t reserved_6_63 : 58; 505215976Sjmallett#endif 506215976Sjmallett } s; 507215976Sjmallett struct cvmx_led_prt_statusx_s cn38xx; 508215976Sjmallett struct cvmx_led_prt_statusx_s cn38xxp2; 509215976Sjmallett struct cvmx_led_prt_statusx_s cn56xx; 510215976Sjmallett struct cvmx_led_prt_statusx_s cn56xxp1; 511215976Sjmallett struct cvmx_led_prt_statusx_s cn58xx; 512215976Sjmallett struct cvmx_led_prt_statusx_s cn58xxp1; 513215976Sjmallett}; 514215976Sjmalletttypedef union cvmx_led_prt_statusx cvmx_led_prt_statusx_t; 515215976Sjmallett 516215976Sjmallett/** 517215976Sjmallett * cvmx_led_udd_cnt# 518215976Sjmallett * 519215976Sjmallett * LED_UDD_CNT = LED UDD Counts 520215976Sjmallett * 521215976Sjmallett */ 522232812Sjmallettunion cvmx_led_udd_cntx { 523215976Sjmallett uint64_t u64; 524232812Sjmallett struct cvmx_led_udd_cntx_s { 525232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 526215976Sjmallett uint64_t reserved_6_63 : 58; 527215976Sjmallett uint64_t cnt : 6; /**< Number of bits of user-defined data to include in 528215976Sjmallett the LED shift chain. Legal values: 0-32. */ 529215976Sjmallett#else 530215976Sjmallett uint64_t cnt : 6; 531215976Sjmallett uint64_t reserved_6_63 : 58; 532215976Sjmallett#endif 533215976Sjmallett } s; 534215976Sjmallett struct cvmx_led_udd_cntx_s cn38xx; 535215976Sjmallett struct cvmx_led_udd_cntx_s cn38xxp2; 536215976Sjmallett struct cvmx_led_udd_cntx_s cn56xx; 537215976Sjmallett struct cvmx_led_udd_cntx_s cn56xxp1; 538215976Sjmallett struct cvmx_led_udd_cntx_s cn58xx; 539215976Sjmallett struct cvmx_led_udd_cntx_s cn58xxp1; 540215976Sjmallett}; 541215976Sjmalletttypedef union cvmx_led_udd_cntx cvmx_led_udd_cntx_t; 542215976Sjmallett 543215976Sjmallett/** 544215976Sjmallett * cvmx_led_udd_dat# 545215976Sjmallett * 546215976Sjmallett * LED_UDD_DAT = User defined data (header or trailer) 547215976Sjmallett * 548215976Sjmallett * 549215976Sjmallett * Notes: 550215976Sjmallett * Bits come out LSB to MSB on the shift chain. If LED_UDD_CNT is set to 4 551215976Sjmallett * then the bits comes out LED_UDD_DAT[0], LED_UDD_DAT[1], LED_UDD_DAT[2], 552215976Sjmallett * LED_UDD_DAT[3]. 553215976Sjmallett */ 554232812Sjmallettunion cvmx_led_udd_datx { 555215976Sjmallett uint64_t u64; 556232812Sjmallett struct cvmx_led_udd_datx_s { 557232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 558215976Sjmallett uint64_t reserved_32_63 : 32; 559215976Sjmallett uint64_t dat : 32; /**< Header or trailer UDD data to be displayed on 560215976Sjmallett the LED shift chain. Number of bits to include 561215976Sjmallett is controled by LED_UDD_CNT */ 562215976Sjmallett#else 563215976Sjmallett uint64_t dat : 32; 564215976Sjmallett uint64_t reserved_32_63 : 32; 565215976Sjmallett#endif 566215976Sjmallett } s; 567215976Sjmallett struct cvmx_led_udd_datx_s cn38xx; 568215976Sjmallett struct cvmx_led_udd_datx_s cn38xxp2; 569215976Sjmallett struct cvmx_led_udd_datx_s cn56xx; 570215976Sjmallett struct cvmx_led_udd_datx_s cn56xxp1; 571215976Sjmallett struct cvmx_led_udd_datx_s cn58xx; 572215976Sjmallett struct cvmx_led_udd_datx_s cn58xxp1; 573215976Sjmallett}; 574215976Sjmalletttypedef union cvmx_led_udd_datx cvmx_led_udd_datx_t; 575215976Sjmallett 576215976Sjmallett/** 577215976Sjmallett * cvmx_led_udd_dat_clr# 578215976Sjmallett * 579215976Sjmallett * LED_UDD_DAT_CLR = User defined data (header or trailer) 580215976Sjmallett * 581215976Sjmallett */ 582232812Sjmallettunion cvmx_led_udd_dat_clrx { 583215976Sjmallett uint64_t u64; 584232812Sjmallett struct cvmx_led_udd_dat_clrx_s { 585232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 586215976Sjmallett uint64_t reserved_32_63 : 32; 587215976Sjmallett uint64_t clr : 32; /**< Bitwise clear for the Header or trailer UDD data to 588215976Sjmallett be displayed on the LED shift chain. */ 589215976Sjmallett#else 590215976Sjmallett uint64_t clr : 32; 591215976Sjmallett uint64_t reserved_32_63 : 32; 592215976Sjmallett#endif 593215976Sjmallett } s; 594215976Sjmallett struct cvmx_led_udd_dat_clrx_s cn38xx; 595215976Sjmallett struct cvmx_led_udd_dat_clrx_s cn38xxp2; 596215976Sjmallett struct cvmx_led_udd_dat_clrx_s cn56xx; 597215976Sjmallett struct cvmx_led_udd_dat_clrx_s cn56xxp1; 598215976Sjmallett struct cvmx_led_udd_dat_clrx_s cn58xx; 599215976Sjmallett struct cvmx_led_udd_dat_clrx_s cn58xxp1; 600215976Sjmallett}; 601215976Sjmalletttypedef union cvmx_led_udd_dat_clrx cvmx_led_udd_dat_clrx_t; 602215976Sjmallett 603215976Sjmallett/** 604215976Sjmallett * cvmx_led_udd_dat_set# 605215976Sjmallett * 606215976Sjmallett * LED_UDD_DAT_SET = User defined data (header or trailer) 607215976Sjmallett * 608215976Sjmallett */ 609232812Sjmallettunion cvmx_led_udd_dat_setx { 610215976Sjmallett uint64_t u64; 611232812Sjmallett struct cvmx_led_udd_dat_setx_s { 612232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 613215976Sjmallett uint64_t reserved_32_63 : 32; 614215976Sjmallett uint64_t set : 32; /**< Bitwise set for the Header or trailer UDD data to 615215976Sjmallett be displayed on the LED shift chain. */ 616215976Sjmallett#else 617215976Sjmallett uint64_t set : 32; 618215976Sjmallett uint64_t reserved_32_63 : 32; 619215976Sjmallett#endif 620215976Sjmallett } s; 621215976Sjmallett struct cvmx_led_udd_dat_setx_s cn38xx; 622215976Sjmallett struct cvmx_led_udd_dat_setx_s cn38xxp2; 623215976Sjmallett struct cvmx_led_udd_dat_setx_s cn56xx; 624215976Sjmallett struct cvmx_led_udd_dat_setx_s cn56xxp1; 625215976Sjmallett struct cvmx_led_udd_dat_setx_s cn58xx; 626215976Sjmallett struct cvmx_led_udd_dat_setx_s cn58xxp1; 627215976Sjmallett}; 628215976Sjmalletttypedef union cvmx_led_udd_dat_setx cvmx_led_udd_dat_setx_t; 629215976Sjmallett 630215976Sjmallett#endif 631