11590Srgrimes/***********************license start*************** 21590Srgrimes * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 31590Srgrimes * reserved. 41590Srgrimes * 51590Srgrimes * 61590Srgrimes * Redistribution and use in source and binary forms, with or without 71590Srgrimes * modification, are permitted provided that the following conditions are 81590Srgrimes * met: 91590Srgrimes * 101590Srgrimes * * Redistributions of source code must retain the above copyright 111590Srgrimes * notice, this list of conditions and the following disclaimer. 121590Srgrimes * 131590Srgrimes * * Redistributions in binary form must reproduce the above 141590Srgrimes * copyright notice, this list of conditions and the following 151590Srgrimes * disclaimer in the documentation and/or other materials provided 161590Srgrimes * with the distribution. 171590Srgrimes 181590Srgrimes * * Neither the name of Cavium Inc. nor the names of 191590Srgrimes * its contributors may be used to endorse or promote products 201590Srgrimes * derived from this software without specific prior written 211590Srgrimes * permission. 221590Srgrimes 231590Srgrimes * This Software, including technical data, may be subject to U.S. export control 241590Srgrimes * laws, including the U.S. Export Administration Act and its associated 251590Srgrimes * regulations, and may be subject to export or import regulations in other 261590Srgrimes * countries. 271590Srgrimes 281590Srgrimes * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 291590Srgrimes * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 301590Srgrimes * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 311590Srgrimes * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 321590Srgrimes * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 331590Srgrimes * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 341590Srgrimes * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 351590Srgrimes * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 361590Srgrimes * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 371590Srgrimes * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 381590Srgrimes ***********************license end**************************************/ 391590Srgrimes 401590Srgrimes 411590Srgrimes/** 421590Srgrimes * cvmx-key-defs.h 431590Srgrimes * 4423695Speter * Configuration and status register (CSR) type definitions for 451590Srgrimes * Octeon key. 461590Srgrimes * 471590Srgrimes * This file is auto generated. Do not edit. 481590Srgrimes * 491590Srgrimes * <hr>$Revision$<hr> 501590Srgrimes * 511590Srgrimes */ 521590Srgrimes#ifndef __CVMX_KEY_DEFS_H__ 531590Srgrimes#define __CVMX_KEY_DEFS_H__ 5417534Sache 551590Srgrimes#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 561590Srgrimes#define CVMX_KEY_BIST_REG CVMX_KEY_BIST_REG_FUNC() 571590Srgrimesstatic inline uint64_t CVMX_KEY_BIST_REG_FUNC(void) 5823695Speter{ 591590Srgrimes if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 601590Srgrimes cvmx_warn("CVMX_KEY_BIST_REG not supported on this chip\n"); 611590Srgrimes return CVMX_ADD_IO_SEG(0x0001180020000018ull); 621590Srgrimes} 631590Srgrimes#else 641590Srgrimes#define CVMX_KEY_BIST_REG (CVMX_ADD_IO_SEG(0x0001180020000018ull)) 651590Srgrimes#endif 661590Srgrimes#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 671590Srgrimes#define CVMX_KEY_CTL_STATUS CVMX_KEY_CTL_STATUS_FUNC() 681590Srgrimesstatic inline uint64_t CVMX_KEY_CTL_STATUS_FUNC(void) 691590Srgrimes{ 701590Srgrimes if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 711590Srgrimes cvmx_warn("CVMX_KEY_CTL_STATUS not supported on this chip\n"); 721590Srgrimes return CVMX_ADD_IO_SEG(0x0001180020000010ull); 731590Srgrimes} 741590Srgrimes#else 751590Srgrimes#define CVMX_KEY_CTL_STATUS (CVMX_ADD_IO_SEG(0x0001180020000010ull)) 761590Srgrimes#endif 771590Srgrimes#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 781590Srgrimes#define CVMX_KEY_INT_ENB CVMX_KEY_INT_ENB_FUNC() 791590Srgrimesstatic inline uint64_t CVMX_KEY_INT_ENB_FUNC(void) 8017534Sache{ 8117534Sache if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 821590Srgrimes cvmx_warn("CVMX_KEY_INT_ENB not supported on this chip\n"); 831590Srgrimes return CVMX_ADD_IO_SEG(0x0001180020000008ull); 841590Srgrimes} 851590Srgrimes#else 861590Srgrimes#define CVMX_KEY_INT_ENB (CVMX_ADD_IO_SEG(0x0001180020000008ull)) 8724360Simp#endif 881590Srgrimes#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 891590Srgrimes#define CVMX_KEY_INT_SUM CVMX_KEY_INT_SUM_FUNC() 901590Srgrimesstatic inline uint64_t CVMX_KEY_INT_SUM_FUNC(void) 911590Srgrimes{ 921590Srgrimes if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))) 931590Srgrimes cvmx_warn("CVMX_KEY_INT_SUM not supported on this chip\n"); 941590Srgrimes return CVMX_ADD_IO_SEG(0x0001180020000000ull); 951590Srgrimes} 961590Srgrimes#else 971590Srgrimes#define CVMX_KEY_INT_SUM (CVMX_ADD_IO_SEG(0x0001180020000000ull)) 981590Srgrimes#endif 991590Srgrimes 1001590Srgrimes/** 1011590Srgrimes * cvmx_key_bist_reg 1021590Srgrimes * 1031590Srgrimes * KEY_BIST_REG = KEY's BIST Status Register 1041590Srgrimes * 1051590Srgrimes * The KEY's BIST status for memories. 1061590Srgrimes */ 1071590Srgrimesunion cvmx_key_bist_reg { 1081590Srgrimes uint64_t u64; 1091590Srgrimes struct cvmx_key_bist_reg_s { 1101590Srgrimes#ifdef __BIG_ENDIAN_BITFIELD 1111590Srgrimes uint64_t reserved_3_63 : 61; 1121590Srgrimes uint64_t rrc : 1; /**< RRC bist status. */ 1131590Srgrimes uint64_t mem1 : 1; /**< MEM - 1 bist status. */ 1141590Srgrimes uint64_t mem0 : 1; /**< MEM - 0 bist status. */ 1151590Srgrimes#else 1161590Srgrimes uint64_t mem0 : 1; 1171590Srgrimes uint64_t mem1 : 1; 1188874Srgrimes uint64_t rrc : 1; 1191590Srgrimes uint64_t reserved_3_63 : 61; 1201590Srgrimes#endif 1211590Srgrimes } s; 1221590Srgrimes struct cvmx_key_bist_reg_s cn38xx; 1231590Srgrimes struct cvmx_key_bist_reg_s cn38xxp2; 1241590Srgrimes struct cvmx_key_bist_reg_s cn56xx; 1251590Srgrimes struct cvmx_key_bist_reg_s cn56xxp1; 1261590Srgrimes struct cvmx_key_bist_reg_s cn58xx; 1271590Srgrimes struct cvmx_key_bist_reg_s cn58xxp1; 1281590Srgrimes struct cvmx_key_bist_reg_s cn61xx; 1291590Srgrimes struct cvmx_key_bist_reg_s cn63xx; 1301590Srgrimes struct cvmx_key_bist_reg_s cn63xxp1; 1311590Srgrimes struct cvmx_key_bist_reg_s cn66xx; 1321590Srgrimes struct cvmx_key_bist_reg_s cn68xx; 1331590Srgrimes struct cvmx_key_bist_reg_s cn68xxp1; 1341590Srgrimes struct cvmx_key_bist_reg_s cnf71xx; 1351590Srgrimes}; 1361590Srgrimestypedef union cvmx_key_bist_reg cvmx_key_bist_reg_t; 1371590Srgrimes 1381590Srgrimes/** 1391590Srgrimes * cvmx_key_ctl_status 1401590Srgrimes * 1411590Srgrimes * KEY_CTL_STATUS = KEY's Control/Status Register 1421590Srgrimes * 1431590Srgrimes * The KEY's interrupt enable register. 1441590Srgrimes */ 1451590Srgrimesunion cvmx_key_ctl_status { 1461590Srgrimes uint64_t u64; 1471590Srgrimes struct cvmx_key_ctl_status_s { 1481590Srgrimes#ifdef __BIG_ENDIAN_BITFIELD 1491590Srgrimes uint64_t reserved_14_63 : 50; 1501590Srgrimes uint64_t mem1_err : 7; /**< Causes a flip of the ECC bit associated 38:32 1511590Srgrimes respective to bit 13:7 of this field, for FPF 1521590Srgrimes FIFO 1. */ 1531590Srgrimes uint64_t mem0_err : 7; /**< Causes a flip of the ECC bit associated 38:32 1541590Srgrimes respective to bit 6:0 of this field, for FPF 1551590Srgrimes FIFO 0. */ 1561590Srgrimes#else 1571590Srgrimes uint64_t mem0_err : 7; 158 uint64_t mem1_err : 7; 159 uint64_t reserved_14_63 : 50; 160#endif 161 } s; 162 struct cvmx_key_ctl_status_s cn38xx; 163 struct cvmx_key_ctl_status_s cn38xxp2; 164 struct cvmx_key_ctl_status_s cn56xx; 165 struct cvmx_key_ctl_status_s cn56xxp1; 166 struct cvmx_key_ctl_status_s cn58xx; 167 struct cvmx_key_ctl_status_s cn58xxp1; 168 struct cvmx_key_ctl_status_s cn61xx; 169 struct cvmx_key_ctl_status_s cn63xx; 170 struct cvmx_key_ctl_status_s cn63xxp1; 171 struct cvmx_key_ctl_status_s cn66xx; 172 struct cvmx_key_ctl_status_s cn68xx; 173 struct cvmx_key_ctl_status_s cn68xxp1; 174 struct cvmx_key_ctl_status_s cnf71xx; 175}; 176typedef union cvmx_key_ctl_status cvmx_key_ctl_status_t; 177 178/** 179 * cvmx_key_int_enb 180 * 181 * KEY_INT_ENB = KEY's Interrupt Enable 182 * 183 * The KEY's interrupt enable register. 184 */ 185union cvmx_key_int_enb { 186 uint64_t u64; 187 struct cvmx_key_int_enb_s { 188#ifdef __BIG_ENDIAN_BITFIELD 189 uint64_t reserved_4_63 : 60; 190 uint64_t ked1_dbe : 1; /**< When set (1) and bit 3 of the KEY_INT_SUM 191 register is asserted the KEY will assert an 192 interrupt. */ 193 uint64_t ked1_sbe : 1; /**< When set (1) and bit 2 of the KEY_INT_SUM 194 register is asserted the KEY will assert an 195 interrupt. */ 196 uint64_t ked0_dbe : 1; /**< When set (1) and bit 1 of the KEY_INT_SUM 197 register is asserted the KEY will assert an 198 interrupt. */ 199 uint64_t ked0_sbe : 1; /**< When set (1) and bit 0 of the KEY_INT_SUM 200 register is asserted the KEY will assert an 201 interrupt. */ 202#else 203 uint64_t ked0_sbe : 1; 204 uint64_t ked0_dbe : 1; 205 uint64_t ked1_sbe : 1; 206 uint64_t ked1_dbe : 1; 207 uint64_t reserved_4_63 : 60; 208#endif 209 } s; 210 struct cvmx_key_int_enb_s cn38xx; 211 struct cvmx_key_int_enb_s cn38xxp2; 212 struct cvmx_key_int_enb_s cn56xx; 213 struct cvmx_key_int_enb_s cn56xxp1; 214 struct cvmx_key_int_enb_s cn58xx; 215 struct cvmx_key_int_enb_s cn58xxp1; 216 struct cvmx_key_int_enb_s cn61xx; 217 struct cvmx_key_int_enb_s cn63xx; 218 struct cvmx_key_int_enb_s cn63xxp1; 219 struct cvmx_key_int_enb_s cn66xx; 220 struct cvmx_key_int_enb_s cn68xx; 221 struct cvmx_key_int_enb_s cn68xxp1; 222 struct cvmx_key_int_enb_s cnf71xx; 223}; 224typedef union cvmx_key_int_enb cvmx_key_int_enb_t; 225 226/** 227 * cvmx_key_int_sum 228 * 229 * KEY_INT_SUM = KEY's Interrupt Summary Register 230 * 231 * Contains the diffrent interrupt summary bits of the KEY. 232 */ 233union cvmx_key_int_sum { 234 uint64_t u64; 235 struct cvmx_key_int_sum_s { 236#ifdef __BIG_ENDIAN_BITFIELD 237 uint64_t reserved_4_63 : 60; 238 uint64_t ked1_dbe : 1; 239 uint64_t ked1_sbe : 1; 240 uint64_t ked0_dbe : 1; 241 uint64_t ked0_sbe : 1; 242#else 243 uint64_t ked0_sbe : 1; 244 uint64_t ked0_dbe : 1; 245 uint64_t ked1_sbe : 1; 246 uint64_t ked1_dbe : 1; 247 uint64_t reserved_4_63 : 60; 248#endif 249 } s; 250 struct cvmx_key_int_sum_s cn38xx; 251 struct cvmx_key_int_sum_s cn38xxp2; 252 struct cvmx_key_int_sum_s cn56xx; 253 struct cvmx_key_int_sum_s cn56xxp1; 254 struct cvmx_key_int_sum_s cn58xx; 255 struct cvmx_key_int_sum_s cn58xxp1; 256 struct cvmx_key_int_sum_s cn61xx; 257 struct cvmx_key_int_sum_s cn63xx; 258 struct cvmx_key_int_sum_s cn63xxp1; 259 struct cvmx_key_int_sum_s cn66xx; 260 struct cvmx_key_int_sum_s cn68xx; 261 struct cvmx_key_int_sum_s cn68xxp1; 262 struct cvmx_key_int_sum_s cnf71xx; 263}; 264typedef union cvmx_key_int_sum cvmx_key_int_sum_t; 265 266#endif 267