cvmx-iob1-defs.h revision 302408
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MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-iob1-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon iob1. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_IOB1_DEFS_H__ 53#define __CVMX_IOB1_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_IOB1_BIST_STATUS CVMX_IOB1_BIST_STATUS_FUNC() 57static inline uint64_t CVMX_IOB1_BIST_STATUS_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 60 cvmx_warn("CVMX_IOB1_BIST_STATUS not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x00011800F00107F8ull); 62} 63#else 64#define CVMX_IOB1_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00107F8ull)) 65#endif 66#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67#define CVMX_IOB1_CTL_STATUS CVMX_IOB1_CTL_STATUS_FUNC() 68static inline uint64_t CVMX_IOB1_CTL_STATUS_FUNC(void) 69{ 70 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 71 cvmx_warn("CVMX_IOB1_CTL_STATUS not supported on this chip\n"); 72 return CVMX_ADD_IO_SEG(0x00011800F0010050ull); 73} 74#else 75#define CVMX_IOB1_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0010050ull)) 76#endif 77#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78#define CVMX_IOB1_TO_CMB_CREDITS CVMX_IOB1_TO_CMB_CREDITS_FUNC() 79static inline uint64_t CVMX_IOB1_TO_CMB_CREDITS_FUNC(void) 80{ 81 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 82 cvmx_warn("CVMX_IOB1_TO_CMB_CREDITS not supported on this chip\n"); 83 return CVMX_ADD_IO_SEG(0x00011800F00100B0ull); 84} 85#else 86#define CVMX_IOB1_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00100B0ull)) 87#endif 88 89/** 90 * cvmx_iob1_bist_status 91 * 92 * IOB_BIST_STATUS = BIST Status of IOB Memories 93 * 94 * The result of the BIST run on the IOB memories. 95 */ 96union cvmx_iob1_bist_status { 97 uint64_t u64; 98 struct cvmx_iob1_bist_status_s { 99#ifdef __BIG_ENDIAN_BITFIELD 100 uint64_t reserved_9_63 : 55; 101 uint64_t xmdfif : 1; /**< xmdfif_bist_status */ 102 uint64_t xmcfif : 1; /**< xmcfif_bist_status */ 103 uint64_t iorfif : 1; /**< iorfif_bist_status */ 104 uint64_t rsdfif : 1; /**< rsdfif_bist_status */ 105 uint64_t iocfif : 1; /**< iocfif_bist_status */ 106 uint64_t reserved_2_3 : 2; 107 uint64_t icrp0 : 1; /**< icr_pko_bist_mem0_status */ 108 uint64_t icrp1 : 1; /**< icr_pko_bist_mem1_status */ 109#else 110 uint64_t icrp1 : 1; 111 uint64_t icrp0 : 1; 112 uint64_t reserved_2_3 : 2; 113 uint64_t iocfif : 1; 114 uint64_t rsdfif : 1; 115 uint64_t iorfif : 1; 116 uint64_t xmcfif : 1; 117 uint64_t xmdfif : 1; 118 uint64_t reserved_9_63 : 55; 119#endif 120 } s; 121 struct cvmx_iob1_bist_status_s cn68xx; 122 struct cvmx_iob1_bist_status_s cn68xxp1; 123}; 124typedef union cvmx_iob1_bist_status cvmx_iob1_bist_status_t; 125 126/** 127 * cvmx_iob1_ctl_status 128 * 129 * IOB Control Status = IOB Control and Status Register 130 * 131 * Provides control for IOB functions. 132 */ 133union cvmx_iob1_ctl_status { 134 uint64_t u64; 135 struct cvmx_iob1_ctl_status_s { 136#ifdef __BIG_ENDIAN_BITFIELD 137 uint64_t reserved_11_63 : 53; 138 uint64_t fif_dly : 1; /**< Delay async FIFO counts to be used when clock ratio 139 is greater then 3:1. Writes should be followed by an 140 immediate read. */ 141 uint64_t xmc_per : 4; /**< IBC XMC PUSH EARLY */ 142 uint64_t reserved_0_5 : 6; 143#else 144 uint64_t reserved_0_5 : 6; 145 uint64_t xmc_per : 4; 146 uint64_t fif_dly : 1; 147 uint64_t reserved_11_63 : 53; 148#endif 149 } s; 150 struct cvmx_iob1_ctl_status_s cn68xx; 151 struct cvmx_iob1_ctl_status_s cn68xxp1; 152}; 153typedef union cvmx_iob1_ctl_status cvmx_iob1_ctl_status_t; 154 155/** 156 * cvmx_iob1_to_cmb_credits 157 * 158 * IOB_TO_CMB_CREDITS = IOB To CMB Credits 159 * 160 * Controls the number of reads and writes that may be outstanding to the L2C (via the CMB). 161 */ 162union cvmx_iob1_to_cmb_credits { 163 uint64_t u64; 164 struct cvmx_iob1_to_cmb_credits_s { 165#ifdef __BIG_ENDIAN_BITFIELD 166 uint64_t reserved_10_63 : 54; 167 uint64_t pko_rd : 4; /**< Number of PKO reads that can be out to L2C where 168 0 == 16-credits. */ 169 uint64_t reserved_3_5 : 3; 170 uint64_t ncb_wr : 3; /**< Number of NCB/PKI writes that can be out to L2C 171 where 0 == 8-credits. */ 172#else 173 uint64_t ncb_wr : 3; 174 uint64_t reserved_3_5 : 3; 175 uint64_t pko_rd : 4; 176 uint64_t reserved_10_63 : 54; 177#endif 178 } s; 179 struct cvmx_iob1_to_cmb_credits_s cn68xx; 180 struct cvmx_iob1_to_cmb_credits_s cn68xxp1; 181}; 182typedef union cvmx_iob1_to_cmb_credits cvmx_iob1_to_cmb_credits_t; 183 184#endif 185