1217309Snwhitehorn/***********************license start*************** 2251843Sbapt * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3220749Snwhitehorn * reserved. 4251843Sbapt * 5217309Snwhitehorn * 6220749Snwhitehorn * Redistribution and use in source and binary forms, with or without 7220749Snwhitehorn * modification, are permitted provided that the following conditions are 8220749Snwhitehorn * met: 9220749Snwhitehorn * 10220749Snwhitehorn * * Redistributions of source code must retain the above copyright 11220749Snwhitehorn * notice, this list of conditions and the following disclaimer. 12220749Snwhitehorn * 13220749Snwhitehorn * * Redistributions in binary form must reproduce the above 14220749Snwhitehorn * copyright notice, this list of conditions and the following 15220749Snwhitehorn * disclaimer in the documentation and/or other materials provided 16220749Snwhitehorn * with the distribution. 17220749Snwhitehorn 18220749Snwhitehorn * * Neither the name of Cavium Inc. nor the names of 19220749Snwhitehorn * its contributors may be used to endorse or promote products 20220749Snwhitehorn * derived from this software without specific prior written 21220749Snwhitehorn * permission. 22220749Snwhitehorn 23220749Snwhitehorn * This Software, including technical data, may be subject to U.S. export control 24220749Snwhitehorn * laws, including the U.S. Export Administration Act and its associated 25220749Snwhitehorn * regulations, and may be subject to export or import regulations in other 26220749Snwhitehorn * countries. 27220749Snwhitehorn 28220749Snwhitehorn * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29220749Snwhitehorn * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30217309Snwhitehorn * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31217309Snwhitehorn * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32217309Snwhitehorn * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33217309Snwhitehorn * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34251843Sbapt * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35217309Snwhitehorn * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36217309Snwhitehorn * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37217309Snwhitehorn * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38217309Snwhitehorn ***********************license end**************************************/ 39217309Snwhitehorn 40217309Snwhitehorn 41217309Snwhitehorn/** 42217309Snwhitehorn * cvmx-iob1-defs.h 43217309Snwhitehorn * 44217309Snwhitehorn * Configuration and status register (CSR) type definitions for 45217309Snwhitehorn * Octeon iob1. 46217309Snwhitehorn * 47217309Snwhitehorn * This file is auto generated. Do not edit. 48251843Sbapt * 49217309Snwhitehorn * <hr>$Revision$<hr> 50217309Snwhitehorn * 51217309Snwhitehorn */ 52217309Snwhitehorn#ifndef __CVMX_IOB1_DEFS_H__ 53217309Snwhitehorn#define __CVMX_IOB1_DEFS_H__ 54217309Snwhitehorn 55217309Snwhitehorn#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56217309Snwhitehorn#define CVMX_IOB1_BIST_STATUS CVMX_IOB1_BIST_STATUS_FUNC() 57217309Snwhitehornstatic inline uint64_t CVMX_IOB1_BIST_STATUS_FUNC(void) 58217309Snwhitehorn{ 59217309Snwhitehorn if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 60217309Snwhitehorn cvmx_warn("CVMX_IOB1_BIST_STATUS not supported on this chip\n"); 61217309Snwhitehorn return CVMX_ADD_IO_SEG(0x00011800F00107F8ull); 62217309Snwhitehorn} 63217309Snwhitehorn#else 64217309Snwhitehorn#define CVMX_IOB1_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00107F8ull)) 65217309Snwhitehorn#endif 66217309Snwhitehorn#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 67217309Snwhitehorn#define CVMX_IOB1_CTL_STATUS CVMX_IOB1_CTL_STATUS_FUNC() 68217309Snwhitehornstatic inline uint64_t CVMX_IOB1_CTL_STATUS_FUNC(void) 69217309Snwhitehorn{ 70217309Snwhitehorn if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 71217309Snwhitehorn cvmx_warn("CVMX_IOB1_CTL_STATUS not supported on this chip\n"); 72217309Snwhitehorn return CVMX_ADD_IO_SEG(0x00011800F0010050ull); 73217309Snwhitehorn} 74217309Snwhitehorn#else 75217309Snwhitehorn#define CVMX_IOB1_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0010050ull)) 76217309Snwhitehorn#endif 77217309Snwhitehorn#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 78217309Snwhitehorn#define CVMX_IOB1_TO_CMB_CREDITS CVMX_IOB1_TO_CMB_CREDITS_FUNC() 79217309Snwhitehornstatic inline uint64_t CVMX_IOB1_TO_CMB_CREDITS_FUNC(void) 80217309Snwhitehorn{ 81217309Snwhitehorn if (!(OCTEON_IS_MODEL(OCTEON_CN68XX))) 82217309Snwhitehorn cvmx_warn("CVMX_IOB1_TO_CMB_CREDITS not supported on this chip\n"); 83217309Snwhitehorn return CVMX_ADD_IO_SEG(0x00011800F00100B0ull); 84217309Snwhitehorn} 85217309Snwhitehorn#else 86217309Snwhitehorn#define CVMX_IOB1_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00100B0ull)) 87217309Snwhitehorn#endif 88217309Snwhitehorn 89217309Snwhitehorn/** 90217309Snwhitehorn * cvmx_iob1_bist_status 91217309Snwhitehorn * 92217309Snwhitehorn * IOB_BIST_STATUS = BIST Status of IOB Memories 93217309Snwhitehorn * 94217309Snwhitehorn * The result of the BIST run on the IOB memories. 95217309Snwhitehorn */ 96217309Snwhitehornunion cvmx_iob1_bist_status { 97217309Snwhitehorn uint64_t u64; 98217309Snwhitehorn struct cvmx_iob1_bist_status_s { 99217309Snwhitehorn#ifdef __BIG_ENDIAN_BITFIELD 100217309Snwhitehorn uint64_t reserved_9_63 : 55; 101217309Snwhitehorn uint64_t xmdfif : 1; /**< xmdfif_bist_status */ 102217309Snwhitehorn uint64_t xmcfif : 1; /**< xmcfif_bist_status */ 103217309Snwhitehorn uint64_t iorfif : 1; /**< iorfif_bist_status */ 104217309Snwhitehorn uint64_t rsdfif : 1; /**< rsdfif_bist_status */ 105217309Snwhitehorn uint64_t iocfif : 1; /**< iocfif_bist_status */ 106217309Snwhitehorn uint64_t reserved_2_3 : 2; 107217309Snwhitehorn uint64_t icrp0 : 1; /**< icr_pko_bist_mem0_status */ 108217309Snwhitehorn uint64_t icrp1 : 1; /**< icr_pko_bist_mem1_status */ 109217309Snwhitehorn#else 110217309Snwhitehorn uint64_t icrp1 : 1; 111217309Snwhitehorn uint64_t icrp0 : 1; 112217309Snwhitehorn uint64_t reserved_2_3 : 2; 113217309Snwhitehorn uint64_t iocfif : 1; 114217309Snwhitehorn uint64_t rsdfif : 1; 115217309Snwhitehorn uint64_t iorfif : 1; 116217309Snwhitehorn uint64_t xmcfif : 1; 117217309Snwhitehorn uint64_t xmdfif : 1; 118217309Snwhitehorn uint64_t reserved_9_63 : 55; 119217309Snwhitehorn#endif 120217309Snwhitehorn } s; 121217309Snwhitehorn struct cvmx_iob1_bist_status_s cn68xx; 122217309Snwhitehorn struct cvmx_iob1_bist_status_s cn68xxp1; 123217309Snwhitehorn}; 124217309Snwhitehorntypedef union cvmx_iob1_bist_status cvmx_iob1_bist_status_t; 125217309Snwhitehorn 126217309Snwhitehorn/** 127217309Snwhitehorn * cvmx_iob1_ctl_status 128217309Snwhitehorn * 129217309Snwhitehorn * IOB Control Status = IOB Control and Status Register 130217309Snwhitehorn * 131217309Snwhitehorn * Provides control for IOB functions. 132217309Snwhitehorn */ 133217309Snwhitehornunion cvmx_iob1_ctl_status { 134217309Snwhitehorn uint64_t u64; 135217309Snwhitehorn struct cvmx_iob1_ctl_status_s { 136217309Snwhitehorn#ifdef __BIG_ENDIAN_BITFIELD 137217309Snwhitehorn uint64_t reserved_11_63 : 53; 138217309Snwhitehorn uint64_t fif_dly : 1; /**< Delay async FIFO counts to be used when clock ratio 139217309Snwhitehorn is greater then 3:1. Writes should be followed by an 140217309Snwhitehorn immediate read. */ 141217309Snwhitehorn uint64_t xmc_per : 4; /**< IBC XMC PUSH EARLY */ 142217309Snwhitehorn uint64_t reserved_0_5 : 6; 143217309Snwhitehorn#else 144217309Snwhitehorn uint64_t reserved_0_5 : 6; 145217309Snwhitehorn uint64_t xmc_per : 4; 146217309Snwhitehorn uint64_t fif_dly : 1; 147217309Snwhitehorn uint64_t reserved_11_63 : 53; 148217309Snwhitehorn#endif 149217309Snwhitehorn } s; 150217309Snwhitehorn struct cvmx_iob1_ctl_status_s cn68xx; 151217309Snwhitehorn struct cvmx_iob1_ctl_status_s cn68xxp1; 152217309Snwhitehorn}; 153217309Snwhitehorntypedef union cvmx_iob1_ctl_status cvmx_iob1_ctl_status_t; 154217309Snwhitehorn 155217309Snwhitehorn/** 156217309Snwhitehorn * cvmx_iob1_to_cmb_credits 157217309Snwhitehorn * 158217309Snwhitehorn * IOB_TO_CMB_CREDITS = IOB To CMB Credits 159217309Snwhitehorn * 160217309Snwhitehorn * Controls the number of reads and writes that may be outstanding to the L2C (via the CMB). 161217309Snwhitehorn */ 162217309Snwhitehornunion cvmx_iob1_to_cmb_credits { 163217309Snwhitehorn uint64_t u64; 164217309Snwhitehorn struct cvmx_iob1_to_cmb_credits_s { 165217309Snwhitehorn#ifdef __BIG_ENDIAN_BITFIELD 166217309Snwhitehorn uint64_t reserved_10_63 : 54; 167217309Snwhitehorn uint64_t pko_rd : 4; /**< Number of PKO reads that can be out to L2C where 168217309Snwhitehorn 0 == 16-credits. */ 169217309Snwhitehorn uint64_t reserved_3_5 : 3; 170217309Snwhitehorn uint64_t ncb_wr : 3; /**< Number of NCB/PKI writes that can be out to L2C 171217309Snwhitehorn where 0 == 8-credits. */ 172217309Snwhitehorn#else 173217309Snwhitehorn uint64_t ncb_wr : 3; 174217309Snwhitehorn uint64_t reserved_3_5 : 3; 175217309Snwhitehorn uint64_t pko_rd : 4; 176217309Snwhitehorn uint64_t reserved_10_63 : 54; 177217309Snwhitehorn#endif 178217309Snwhitehorn } s; 179217309Snwhitehorn struct cvmx_iob1_to_cmb_credits_s cn68xx; 180217309Snwhitehorn struct cvmx_iob1_to_cmb_credits_s cn68xxp1; 181217309Snwhitehorn}; 182217309Snwhitehorntypedef union cvmx_iob1_to_cmb_credits cvmx_iob1_to_cmb_credits_t; 183217309Snwhitehorn 184217309Snwhitehorn#endif 185217309Snwhitehorn