1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17210284Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22210284Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27210284Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215990Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett/** 42210284Sjmallett * @file 43210284Sjmallett * 44210284Sjmallett * Interface to the hardware Fetch and Add Unit. 45210284Sjmallett * 46232812Sjmallett * <hr>$Revision: 70030 $<hr> 47210284Sjmallett */ 48210284Sjmallett 49210284Sjmallett#ifndef __CVMX_FAU_H__ 50210284Sjmallett#define __CVMX_FAU_H__ 51210284Sjmallett 52210284Sjmallett#ifndef CVMX_DONT_INCLUDE_CONFIG 53210284Sjmallett#include "cvmx-config.h" 54210284Sjmallett#else 55210284Sjmalletttypedef int cvmx_fau_reg_64_t; 56210284Sjmalletttypedef int cvmx_fau_reg_32_t; 57210284Sjmalletttypedef int cvmx_fau_reg_16_t; 58210284Sjmalletttypedef int cvmx_fau_reg_8_t; 59210284Sjmallett#endif 60210284Sjmallett 61210284Sjmallett#ifdef __cplusplus 62210284Sjmallettextern "C" { 63210284Sjmallett#endif 64210284Sjmallett 65210284Sjmallett/* 66210284Sjmallett * Octeon Fetch and Add Unit (FAU) 67210284Sjmallett */ 68210284Sjmallett 69210284Sjmallett#define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0) 70210284Sjmallett#define CVMX_FAU_BITS_SCRADDR 63,56 71210284Sjmallett#define CVMX_FAU_BITS_LEN 55,48 72210284Sjmallett#define CVMX_FAU_BITS_INEVAL 35,14 73210284Sjmallett#define CVMX_FAU_BITS_TAGWAIT 13,13 74210284Sjmallett#define CVMX_FAU_BITS_NOADD 13,13 75210284Sjmallett#define CVMX_FAU_BITS_SIZE 12,11 76210284Sjmallett#define CVMX_FAU_BITS_REGISTER 10,0 77210284Sjmallett 78210284Sjmallett 79210284Sjmalletttypedef enum { 80210284Sjmallett CVMX_FAU_OP_SIZE_8 = 0, 81210284Sjmallett CVMX_FAU_OP_SIZE_16 = 1, 82210284Sjmallett CVMX_FAU_OP_SIZE_32 = 2, 83210284Sjmallett CVMX_FAU_OP_SIZE_64 = 3 84210284Sjmallett} cvmx_fau_op_size_t; 85210284Sjmallett 86210284Sjmallett/** 87210284Sjmallett * Tagwait return definition. If a timeout occurs, the error 88210284Sjmallett * bit will be set. Otherwise the value of the register before 89210284Sjmallett * the update will be returned. 90210284Sjmallett */ 91210284Sjmalletttypedef struct 92210284Sjmallett{ 93210284Sjmallett uint64_t error : 1; 94210284Sjmallett int64_t value : 63; 95210284Sjmallett} cvmx_fau_tagwait64_t; 96210284Sjmallett 97210284Sjmallett/** 98210284Sjmallett * Tagwait return definition. If a timeout occurs, the error 99210284Sjmallett * bit will be set. Otherwise the value of the register before 100210284Sjmallett * the update will be returned. 101210284Sjmallett */ 102210284Sjmalletttypedef struct 103210284Sjmallett{ 104210284Sjmallett uint64_t error : 1; 105210284Sjmallett int32_t value : 31; 106210284Sjmallett} cvmx_fau_tagwait32_t; 107210284Sjmallett 108210284Sjmallett/** 109210284Sjmallett * Tagwait return definition. If a timeout occurs, the error 110210284Sjmallett * bit will be set. Otherwise the value of the register before 111210284Sjmallett * the update will be returned. 112210284Sjmallett */ 113210284Sjmalletttypedef struct 114210284Sjmallett{ 115210284Sjmallett uint64_t error : 1; 116210284Sjmallett int16_t value : 15; 117210284Sjmallett} cvmx_fau_tagwait16_t; 118210284Sjmallett 119210284Sjmallett/** 120210284Sjmallett * Tagwait return definition. If a timeout occurs, the error 121210284Sjmallett * bit will be set. Otherwise the value of the register before 122210284Sjmallett * the update will be returned. 123210284Sjmallett */ 124210284Sjmalletttypedef struct 125210284Sjmallett{ 126210284Sjmallett uint64_t error : 1; 127210284Sjmallett int8_t value : 7; 128210284Sjmallett} cvmx_fau_tagwait8_t; 129210284Sjmallett 130210284Sjmallett/** 131210284Sjmallett * Asynchronous tagwait return definition. If a timeout occurs, 132210284Sjmallett * the error bit will be set. Otherwise the value of the 133210284Sjmallett * register before the update will be returned. 134210284Sjmallett */ 135210284Sjmalletttypedef union { 136210284Sjmallett uint64_t u64; 137210284Sjmallett struct { 138210284Sjmallett uint64_t invalid: 1; 139215990Sjmallett uint64_t data :63; /* unpredictable if invalid is set */ 140210284Sjmallett } s; 141210284Sjmallett} cvmx_fau_async_tagwait_result_t; 142210284Sjmallett 143210284Sjmallett/** 144210284Sjmallett * @INTERNAL 145210284Sjmallett * Builds a store I/O address for writing to the FAU 146210284Sjmallett * 147210284Sjmallett * @param noadd 0 = Store value is atomically added to the current value 148210284Sjmallett * 1 = Store value is atomically written over the current value 149210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 150210284Sjmallett * - Step by 2 for 16 bit access. 151210284Sjmallett * - Step by 4 for 32 bit access. 152210284Sjmallett * - Step by 8 for 64 bit access. 153210284Sjmallett * @return Address to store for atomic update 154210284Sjmallett */ 155210284Sjmallettstatic inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) 156210284Sjmallett{ 157210284Sjmallett return (CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | 158210284Sjmallett cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) | 159210284Sjmallett cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg)); 160210284Sjmallett} 161210284Sjmallett 162210284Sjmallett/** 163210284Sjmallett * @INTERNAL 164210284Sjmallett * Builds a I/O address for accessing the FAU 165210284Sjmallett * 166210284Sjmallett * @param tagwait Should the atomic add wait for the current tag switch 167210284Sjmallett * operation to complete. 168210284Sjmallett * - 0 = Don't wait 169210284Sjmallett * - 1 = Wait for tag switch to complete 170210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 171210284Sjmallett * - Step by 2 for 16 bit access. 172210284Sjmallett * - Step by 4 for 32 bit access. 173210284Sjmallett * - Step by 8 for 64 bit access. 174210284Sjmallett * @param value Signed value to add. 175210284Sjmallett * Note: When performing 32 and 64 bit access, only the low 176210284Sjmallett * 22 bits are available. 177210284Sjmallett * @return Address to read from for atomic update 178210284Sjmallett */ 179210284Sjmallettstatic inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, int64_t value) 180210284Sjmallett{ 181210284Sjmallett return (CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | 182210284Sjmallett cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | 183210284Sjmallett cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | 184210284Sjmallett cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg)); 185210284Sjmallett} 186210284Sjmallett 187210284Sjmallett/** 188210284Sjmallett * Perform an atomic 64 bit add 189210284Sjmallett * 190210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 191210284Sjmallett * - Step by 8 for 64 bit access. 192210284Sjmallett * @param value Signed value to add. 193210284Sjmallett * Note: Only the low 22 bits are available. 194210284Sjmallett * @return Value of the register before the update 195210284Sjmallett */ 196210284Sjmallettstatic inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) 197210284Sjmallett{ 198210284Sjmallett return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); 199210284Sjmallett} 200210284Sjmallett 201210284Sjmallett/** 202210284Sjmallett * Perform an atomic 32 bit add 203210284Sjmallett * 204210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 205210284Sjmallett * - Step by 4 for 32 bit access. 206210284Sjmallett * @param value Signed value to add. 207210284Sjmallett * Note: Only the low 22 bits are available. 208210284Sjmallett * @return Value of the register before the update 209210284Sjmallett */ 210210284Sjmallettstatic inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) 211210284Sjmallett{ 212210284Sjmallett return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); 213210284Sjmallett} 214210284Sjmallett 215210284Sjmallett/** 216210284Sjmallett * Perform an atomic 16 bit add 217210284Sjmallett * 218210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 219210284Sjmallett * - Step by 2 for 16 bit access. 220210284Sjmallett * @param value Signed value to add. 221210284Sjmallett * @return Value of the register before the update 222210284Sjmallett */ 223210284Sjmallettstatic inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) 224210284Sjmallett{ 225210284Sjmallett return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value)); 226210284Sjmallett} 227210284Sjmallett 228210284Sjmallett/** 229210284Sjmallett * Perform an atomic 8 bit add 230210284Sjmallett * 231210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 232210284Sjmallett * @param value Signed value to add. 233210284Sjmallett * @return Value of the register before the update 234210284Sjmallett */ 235210284Sjmallettstatic inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) 236210284Sjmallett{ 237210284Sjmallett return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value)); 238210284Sjmallett} 239210284Sjmallett 240210284Sjmallett/** 241210284Sjmallett * Perform an atomic 64 bit add after the current tag switch 242210284Sjmallett * completes 243210284Sjmallett * 244210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 245210284Sjmallett * - Step by 8 for 64 bit access. 246210284Sjmallett * @param value Signed value to add. 247210284Sjmallett * Note: Only the low 22 bits are available. 248210284Sjmallett * @return If a timeout occurs, the error bit will be set. Otherwise 249210284Sjmallett * the value of the register before the update will be 250210284Sjmallett * returned 251210284Sjmallett */ 252210284Sjmallettstatic inline cvmx_fau_tagwait64_t cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) 253210284Sjmallett{ 254210284Sjmallett union 255210284Sjmallett { 256210284Sjmallett uint64_t i64; 257210284Sjmallett cvmx_fau_tagwait64_t t; 258210284Sjmallett } result; 259210284Sjmallett result.i64 = cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value)); 260210284Sjmallett return result.t; 261210284Sjmallett} 262210284Sjmallett 263210284Sjmallett/** 264210284Sjmallett * Perform an atomic 32 bit add after the current tag switch 265210284Sjmallett * completes 266210284Sjmallett * 267210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 268210284Sjmallett * - Step by 4 for 32 bit access. 269210284Sjmallett * @param value Signed value to add. 270210284Sjmallett * Note: Only the low 22 bits are available. 271210284Sjmallett * @return If a timeout occurs, the error bit will be set. Otherwise 272210284Sjmallett * the value of the register before the update will be 273210284Sjmallett * returned 274210284Sjmallett */ 275210284Sjmallettstatic inline cvmx_fau_tagwait32_t cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) 276210284Sjmallett{ 277210284Sjmallett union 278210284Sjmallett { 279210284Sjmallett uint64_t i32; 280210284Sjmallett cvmx_fau_tagwait32_t t; 281210284Sjmallett } result; 282210284Sjmallett result.i32 = cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value)); 283210284Sjmallett return result.t; 284210284Sjmallett} 285210284Sjmallett 286210284Sjmallett/** 287210284Sjmallett * Perform an atomic 16 bit add after the current tag switch 288210284Sjmallett * completes 289210284Sjmallett * 290210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 291210284Sjmallett * - Step by 2 for 16 bit access. 292210284Sjmallett * @param value Signed value to add. 293210284Sjmallett * @return If a timeout occurs, the error bit will be set. Otherwise 294210284Sjmallett * the value of the register before the update will be 295210284Sjmallett * returned 296210284Sjmallett */ 297210284Sjmallettstatic inline cvmx_fau_tagwait16_t cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) 298210284Sjmallett{ 299210284Sjmallett union 300210284Sjmallett { 301210284Sjmallett uint64_t i16; 302210284Sjmallett cvmx_fau_tagwait16_t t; 303210284Sjmallett } result; 304210284Sjmallett result.i16 = cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value)); 305210284Sjmallett return result.t; 306210284Sjmallett} 307210284Sjmallett 308210284Sjmallett/** 309210284Sjmallett * Perform an atomic 8 bit add after the current tag switch 310210284Sjmallett * completes 311210284Sjmallett * 312210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 313210284Sjmallett * @param value Signed value to add. 314210284Sjmallett * @return If a timeout occurs, the error bit will be set. Otherwise 315210284Sjmallett * the value of the register before the update will be 316210284Sjmallett * returned 317210284Sjmallett */ 318210284Sjmallettstatic inline cvmx_fau_tagwait8_t cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) 319210284Sjmallett{ 320210284Sjmallett union 321210284Sjmallett { 322210284Sjmallett uint64_t i8; 323210284Sjmallett cvmx_fau_tagwait8_t t; 324210284Sjmallett } result; 325210284Sjmallett result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value)); 326210284Sjmallett return result.t; 327210284Sjmallett} 328210284Sjmallett 329210284Sjmallett/** 330210284Sjmallett * @INTERNAL 331210284Sjmallett * Builds I/O data for async operations 332210284Sjmallett * 333210284Sjmallett * @param scraddr Scratch pad byte addres to write to. Must be 8 byte aligned 334210284Sjmallett * @param value Signed value to add. 335210284Sjmallett * Note: When performing 32 and 64 bit access, only the low 336210284Sjmallett * 22 bits are available. 337210284Sjmallett * @param tagwait Should the atomic add wait for the current tag switch 338210284Sjmallett * operation to complete. 339210284Sjmallett * - 0 = Don't wait 340210284Sjmallett * - 1 = Wait for tag switch to complete 341210284Sjmallett * @param size The size of the operation: 342210284Sjmallett * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits 343210284Sjmallett * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits 344210284Sjmallett * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits 345210284Sjmallett * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits 346210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 347210284Sjmallett * - Step by 2 for 16 bit access. 348210284Sjmallett * - Step by 4 for 32 bit access. 349210284Sjmallett * - Step by 8 for 64 bit access. 350210284Sjmallett * @return Data to write using cvmx_send_single 351210284Sjmallett */ 352210284Sjmallettstatic inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, uint64_t tagwait, 353210284Sjmallett cvmx_fau_op_size_t size, uint64_t reg) 354210284Sjmallett{ 355210284Sjmallett return (CVMX_FAU_LOAD_IO_ADDRESS | 356210284Sjmallett cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr>>3) | 357210284Sjmallett cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) | 358210284Sjmallett cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | 359210284Sjmallett cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | 360210284Sjmallett cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) | 361210284Sjmallett cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg)); 362210284Sjmallett} 363210284Sjmallett 364210284Sjmallett/** 365210284Sjmallett * Perform an async atomic 64 bit add. The old value is 366210284Sjmallett * placed in the scratch memory at byte address scraddr. 367210284Sjmallett * 368210284Sjmallett * @param scraddr Scratch memory byte address to put response in. 369210284Sjmallett * Must be 8 byte aligned. 370210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 371210284Sjmallett * - Step by 8 for 64 bit access. 372210284Sjmallett * @param value Signed value to add. 373210284Sjmallett * Note: Only the low 22 bits are available. 374210284Sjmallett * @return Placed in the scratch pad register 375210284Sjmallett */ 376210284Sjmallettstatic inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, cvmx_fau_reg_64_t reg, int64_t value) 377210284Sjmallett{ 378210284Sjmallett cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg)); 379210284Sjmallett} 380210284Sjmallett 381210284Sjmallett/** 382210284Sjmallett * Perform an async atomic 32 bit add. The old value is 383210284Sjmallett * placed in the scratch memory at byte address scraddr. 384210284Sjmallett * 385210284Sjmallett * @param scraddr Scratch memory byte address to put response in. 386210284Sjmallett * Must be 8 byte aligned. 387210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 388210284Sjmallett * - Step by 4 for 32 bit access. 389210284Sjmallett * @param value Signed value to add. 390210284Sjmallett * Note: Only the low 22 bits are available. 391210284Sjmallett * @return Placed in the scratch pad register 392210284Sjmallett */ 393210284Sjmallettstatic inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, cvmx_fau_reg_32_t reg, int32_t value) 394210284Sjmallett{ 395210284Sjmallett cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg)); 396210284Sjmallett} 397210284Sjmallett 398210284Sjmallett/** 399210284Sjmallett * Perform an async atomic 16 bit add. The old value is 400210284Sjmallett * placed in the scratch memory at byte address scraddr. 401210284Sjmallett * 402210284Sjmallett * @param scraddr Scratch memory byte address to put response in. 403210284Sjmallett * Must be 8 byte aligned. 404210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 405210284Sjmallett * - Step by 2 for 16 bit access. 406210284Sjmallett * @param value Signed value to add. 407210284Sjmallett * @return Placed in the scratch pad register 408210284Sjmallett */ 409210284Sjmallettstatic inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr, cvmx_fau_reg_16_t reg, int16_t value) 410210284Sjmallett{ 411210284Sjmallett cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg)); 412210284Sjmallett} 413210284Sjmallett 414210284Sjmallett/** 415210284Sjmallett * Perform an async atomic 8 bit add. The old value is 416210284Sjmallett * placed in the scratch memory at byte address scraddr. 417210284Sjmallett * 418210284Sjmallett * @param scraddr Scratch memory byte address to put response in. 419210284Sjmallett * Must be 8 byte aligned. 420210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 421210284Sjmallett * @param value Signed value to add. 422210284Sjmallett * @return Placed in the scratch pad register 423210284Sjmallett */ 424210284Sjmallettstatic inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr, cvmx_fau_reg_8_t reg, int8_t value) 425210284Sjmallett{ 426210284Sjmallett cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg)); 427210284Sjmallett} 428210284Sjmallett 429210284Sjmallett/** 430210284Sjmallett * Perform an async atomic 64 bit add after the current tag 431210284Sjmallett * switch completes. 432210284Sjmallett * 433210284Sjmallett * @param scraddr Scratch memory byte address to put response in. 434210284Sjmallett * Must be 8 byte aligned. 435210284Sjmallett * If a timeout occurs, the error bit (63) will be set. Otherwise 436210284Sjmallett * the value of the register before the update will be 437210284Sjmallett * returned 438210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 439210284Sjmallett * - Step by 8 for 64 bit access. 440210284Sjmallett * @param value Signed value to add. 441210284Sjmallett * Note: Only the low 22 bits are available. 442210284Sjmallett * @return Placed in the scratch pad register 443210284Sjmallett */ 444210284Sjmallettstatic inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, cvmx_fau_reg_64_t reg, int64_t value) 445210284Sjmallett{ 446210284Sjmallett cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg)); 447210284Sjmallett} 448210284Sjmallett 449210284Sjmallett/** 450210284Sjmallett * Perform an async atomic 32 bit add after the current tag 451210284Sjmallett * switch completes. 452210284Sjmallett * 453210284Sjmallett * @param scraddr Scratch memory byte address to put response in. 454210284Sjmallett * Must be 8 byte aligned. 455210284Sjmallett * If a timeout occurs, the error bit (63) will be set. Otherwise 456210284Sjmallett * the value of the register before the update will be 457210284Sjmallett * returned 458210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 459210284Sjmallett * - Step by 4 for 32 bit access. 460210284Sjmallett * @param value Signed value to add. 461210284Sjmallett * Note: Only the low 22 bits are available. 462210284Sjmallett * @return Placed in the scratch pad register 463210284Sjmallett */ 464210284Sjmallettstatic inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, cvmx_fau_reg_32_t reg, int32_t value) 465210284Sjmallett{ 466210284Sjmallett cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg)); 467210284Sjmallett} 468210284Sjmallett 469210284Sjmallett/** 470210284Sjmallett * Perform an async atomic 16 bit add after the current tag 471210284Sjmallett * switch completes. 472210284Sjmallett * 473210284Sjmallett * @param scraddr Scratch memory byte address to put response in. 474210284Sjmallett * Must be 8 byte aligned. 475210284Sjmallett * If a timeout occurs, the error bit (63) will be set. Otherwise 476210284Sjmallett * the value of the register before the update will be 477210284Sjmallett * returned 478210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 479210284Sjmallett * - Step by 2 for 16 bit access. 480210284Sjmallett * @param value Signed value to add. 481210284Sjmallett * @return Placed in the scratch pad register 482210284Sjmallett */ 483210284Sjmallettstatic inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, cvmx_fau_reg_16_t reg, int16_t value) 484210284Sjmallett{ 485210284Sjmallett cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg)); 486210284Sjmallett} 487210284Sjmallett 488210284Sjmallett/** 489210284Sjmallett * Perform an async atomic 8 bit add after the current tag 490210284Sjmallett * switch completes. 491210284Sjmallett * 492210284Sjmallett * @param scraddr Scratch memory byte address to put response in. 493210284Sjmallett * Must be 8 byte aligned. 494210284Sjmallett * If a timeout occurs, the error bit (63) will be set. Otherwise 495210284Sjmallett * the value of the register before the update will be 496210284Sjmallett * returned 497210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 498210284Sjmallett * @param value Signed value to add. 499210284Sjmallett * @return Placed in the scratch pad register 500210284Sjmallett */ 501210284Sjmallettstatic inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, cvmx_fau_reg_8_t reg, int8_t value) 502210284Sjmallett{ 503210284Sjmallett cvmx_send_single(__cvmx_fau_iobdma_data(scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg)); 504210284Sjmallett} 505210284Sjmallett 506210284Sjmallett/** 507210284Sjmallett * Perform an atomic 64 bit add 508210284Sjmallett * 509210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 510210284Sjmallett * - Step by 8 for 64 bit access. 511210284Sjmallett * @param value Signed value to add. 512210284Sjmallett */ 513210284Sjmallettstatic inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) 514210284Sjmallett{ 515210284Sjmallett cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value); 516210284Sjmallett} 517210284Sjmallett 518210284Sjmallett/** 519210284Sjmallett * Perform an atomic 32 bit add 520210284Sjmallett * 521210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 522210284Sjmallett * - Step by 4 for 32 bit access. 523210284Sjmallett * @param value Signed value to add. 524210284Sjmallett */ 525210284Sjmallettstatic inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) 526210284Sjmallett{ 527210284Sjmallett cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value); 528210284Sjmallett} 529210284Sjmallett 530210284Sjmallett/** 531210284Sjmallett * Perform an atomic 16 bit add 532210284Sjmallett * 533210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 534210284Sjmallett * - Step by 2 for 16 bit access. 535210284Sjmallett * @param value Signed value to add. 536210284Sjmallett */ 537210284Sjmallettstatic inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) 538210284Sjmallett{ 539210284Sjmallett cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value); 540210284Sjmallett} 541210284Sjmallett 542210284Sjmallett/** 543210284Sjmallett * Perform an atomic 8 bit add 544210284Sjmallett * 545210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 546210284Sjmallett * @param value Signed value to add. 547210284Sjmallett */ 548210284Sjmallettstatic inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) 549210284Sjmallett{ 550210284Sjmallett cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value); 551210284Sjmallett} 552210284Sjmallett 553210284Sjmallett/** 554210284Sjmallett * Perform an atomic 64 bit write 555210284Sjmallett * 556210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 557210284Sjmallett * - Step by 8 for 64 bit access. 558210284Sjmallett * @param value Signed value to write. 559210284Sjmallett */ 560210284Sjmallettstatic inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) 561210284Sjmallett{ 562210284Sjmallett cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value); 563210284Sjmallett} 564210284Sjmallett 565210284Sjmallett/** 566210284Sjmallett * Perform an atomic 32 bit write 567210284Sjmallett * 568210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 569210284Sjmallett * - Step by 4 for 32 bit access. 570210284Sjmallett * @param value Signed value to write. 571210284Sjmallett */ 572210284Sjmallettstatic inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) 573210284Sjmallett{ 574210284Sjmallett cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value); 575210284Sjmallett} 576210284Sjmallett 577210284Sjmallett/** 578210284Sjmallett * Perform an atomic 16 bit write 579210284Sjmallett * 580210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 581210284Sjmallett * - Step by 2 for 16 bit access. 582210284Sjmallett * @param value Signed value to write. 583210284Sjmallett */ 584210284Sjmallettstatic inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) 585210284Sjmallett{ 586210284Sjmallett cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value); 587210284Sjmallett} 588210284Sjmallett 589210284Sjmallett/** 590210284Sjmallett * Perform an atomic 8 bit write 591210284Sjmallett * 592210284Sjmallett * @param reg FAU atomic register to access. 0 <= reg < 2048. 593210284Sjmallett * @param value Signed value to write. 594210284Sjmallett */ 595210284Sjmallettstatic inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value) 596210284Sjmallett{ 597210284Sjmallett cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value); 598210284Sjmallett} 599210284Sjmallett 600210284Sjmallett#ifdef __cplusplus 601210284Sjmallett} 602210284Sjmallett#endif 603210284Sjmallett 604210284Sjmallett#endif /* __CVMX_FAU_H__ */ 605