cvmx-dbg-defs.h revision 215990
1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). 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THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-dbg-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon dbg. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_DBG_TYPEDEFS_H__ 53#define __CVMX_DBG_TYPEDEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56#define CVMX_DBG_DATA CVMX_DBG_DATA_FUNC() 57static inline uint64_t CVMX_DBG_DATA_FUNC(void) 58{ 59 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 60 cvmx_warn("CVMX_DBG_DATA not supported on this chip\n"); 61 return CVMX_ADD_IO_SEG(0x00011F00000001E8ull); 62} 63#else 64#define CVMX_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F00000001E8ull)) 65#endif 66 67/** 68 * cvmx_dbg_data 69 * 70 * DBG_DATA = Debug Data Register 71 * 72 * Value returned on the debug-data lines from the RSLs 73 */ 74union cvmx_dbg_data 75{ 76 uint64_t u64; 77 struct cvmx_dbg_data_s 78 { 79#if __BYTE_ORDER == __BIG_ENDIAN 80 uint64_t reserved_23_63 : 41; 81 uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */ 82 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 83 debug select value. */ 84 uint64_t data : 17; /**< Value on the debug data lines. */ 85#else 86 uint64_t data : 17; 87 uint64_t dsel_ext : 1; 88 uint64_t c_mul : 5; 89 uint64_t reserved_23_63 : 41; 90#endif 91 } s; 92 struct cvmx_dbg_data_cn30xx 93 { 94#if __BYTE_ORDER == __BIG_ENDIAN 95 uint64_t reserved_31_63 : 33; 96 uint64_t pll_mul : 3; /**< pll_mul pins sampled at DCOK assertion */ 97 uint64_t reserved_23_27 : 5; 98 uint64_t c_mul : 5; /**< Core PLL multiplier sampled at DCOK assertion */ 99 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 100 debug select value. */ 101 uint64_t data : 17; /**< Value on the debug data lines. */ 102#else 103 uint64_t data : 17; 104 uint64_t dsel_ext : 1; 105 uint64_t c_mul : 5; 106 uint64_t reserved_23_27 : 5; 107 uint64_t pll_mul : 3; 108 uint64_t reserved_31_63 : 33; 109#endif 110 } cn30xx; 111 struct cvmx_dbg_data_cn30xx cn31xx; 112 struct cvmx_dbg_data_cn38xx 113 { 114#if __BYTE_ORDER == __BIG_ENDIAN 115 uint64_t reserved_29_63 : 35; 116 uint64_t d_mul : 4; /**< D_MUL pins sampled on DCOK assertion */ 117 uint64_t dclk_mul2 : 1; /**< Should always be set for fast DDR-II operation */ 118 uint64_t cclk_div2 : 1; /**< Should always be clear for fast core clock */ 119 uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */ 120 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 121 debug select value. */ 122 uint64_t data : 17; /**< Value on the debug data lines. */ 123#else 124 uint64_t data : 17; 125 uint64_t dsel_ext : 1; 126 uint64_t c_mul : 5; 127 uint64_t cclk_div2 : 1; 128 uint64_t dclk_mul2 : 1; 129 uint64_t d_mul : 4; 130 uint64_t reserved_29_63 : 35; 131#endif 132 } cn38xx; 133 struct cvmx_dbg_data_cn38xx cn38xxp2; 134 struct cvmx_dbg_data_cn30xx cn50xx; 135 struct cvmx_dbg_data_cn58xx 136 { 137#if __BYTE_ORDER == __BIG_ENDIAN 138 uint64_t reserved_29_63 : 35; 139 uint64_t rem : 6; /**< Remaining debug_select pins sampled at DCOK */ 140 uint64_t c_mul : 5; /**< C_MUL pins sampled at DCOK assertion */ 141 uint64_t dsel_ext : 1; /**< Allows changes in the external pins to set the 142 debug select value. */ 143 uint64_t data : 17; /**< Value on the debug data lines. */ 144#else 145 uint64_t data : 17; 146 uint64_t dsel_ext : 1; 147 uint64_t c_mul : 5; 148 uint64_t rem : 6; 149 uint64_t reserved_29_63 : 35; 150#endif 151 } cn58xx; 152 struct cvmx_dbg_data_cn58xx cn58xxp1; 153}; 154typedef union cvmx_dbg_data cvmx_dbg_data_t; 155 156#endif 157