fm.h revision 296177
1/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc. 2 * All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/****************************************************************************** 34 @File fm.h 35 36 @Description FM internal structures and definitions. 37*//***************************************************************************/ 38#ifndef __FM_H 39#define __FM_H 40 41#include "error_ext.h" 42#include "std_ext.h" 43#include "fm_ext.h" 44#include "fm_ipc.h" 45 46 47#define __ERR_MODULE__ MODULE_FM 48 49#define FM_MAX_NUM_OF_HW_PORT_IDS 64 50#define FM_MAX_NUM_OF_GUESTS 100 51 52/**************************************************************************//** 53 @Description Exceptions 54*//***************************************************************************/ 55#define FM_EX_DMA_BUS_ERROR 0x80000000 /**< DMA bus error. */ 56#define FM_EX_DMA_READ_ECC 0x40000000 57#define FM_EX_DMA_SYSTEM_WRITE_ECC 0x20000000 58#define FM_EX_DMA_FM_WRITE_ECC 0x10000000 59#define FM_EX_FPM_STALL_ON_TASKS 0x08000000 /**< Stall of tasks on FPM */ 60#define FM_EX_FPM_SINGLE_ECC 0x04000000 /**< Single ECC on FPM */ 61#define FM_EX_FPM_DOUBLE_ECC 0x02000000 62#define FM_EX_QMI_SINGLE_ECC 0x01000000 /**< Single ECC on FPM */ 63#define FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID 0x00800000 /**< Dequeu from default queue id */ 64#define FM_EX_QMI_DOUBLE_ECC 0x00400000 65#define FM_EX_BMI_LIST_RAM_ECC 0x00200000 66#define FM_EX_BMI_PIPELINE_ECC 0x00100000 67#define FM_EX_BMI_STATISTICS_RAM_ECC 0x00080000 68#define FM_EX_IRAM_ECC 0x00040000 69#define FM_EX_NURAM_ECC 0x00020000 70#define FM_EX_BMI_DISPATCH_RAM_ECC 0x00010000 71 72#define GET_EXCEPTION_FLAG(bitMask, exception) switch(exception){ \ 73 case e_FM_EX_DMA_BUS_ERROR: \ 74 bitMask = FM_EX_DMA_BUS_ERROR; break; \ 75 case e_FM_EX_DMA_READ_ECC: \ 76 bitMask = FM_EX_DMA_READ_ECC; break; \ 77 case e_FM_EX_DMA_SYSTEM_WRITE_ECC: \ 78 bitMask = FM_EX_DMA_SYSTEM_WRITE_ECC; break; \ 79 case e_FM_EX_DMA_FM_WRITE_ECC: \ 80 bitMask = FM_EX_DMA_FM_WRITE_ECC; break; \ 81 case e_FM_EX_FPM_STALL_ON_TASKS: \ 82 bitMask = FM_EX_FPM_STALL_ON_TASKS; break; \ 83 case e_FM_EX_FPM_SINGLE_ECC: \ 84 bitMask = FM_EX_FPM_SINGLE_ECC; break; \ 85 case e_FM_EX_FPM_DOUBLE_ECC: \ 86 bitMask = FM_EX_FPM_DOUBLE_ECC; break; \ 87 case e_FM_EX_QMI_SINGLE_ECC: \ 88 bitMask = FM_EX_QMI_SINGLE_ECC; break; \ 89 case e_FM_EX_QMI_DOUBLE_ECC: \ 90 bitMask = FM_EX_QMI_DOUBLE_ECC; break; \ 91 case e_FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID: \ 92 bitMask = FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID; break; \ 93 case e_FM_EX_BMI_LIST_RAM_ECC: \ 94 bitMask = FM_EX_BMI_LIST_RAM_ECC; break; \ 95 case e_FM_EX_BMI_PIPELINE_ECC: \ 96 bitMask = FM_EX_BMI_PIPELINE_ECC; break; \ 97 case e_FM_EX_BMI_STATISTICS_RAM_ECC: \ 98 bitMask = FM_EX_BMI_STATISTICS_RAM_ECC; break; \ 99 case e_FM_EX_BMI_DISPATCH_RAM_ECC: \ 100 bitMask = FM_EX_BMI_DISPATCH_RAM_ECC; break; \ 101 case e_FM_EX_IRAM_ECC: \ 102 bitMask = FM_EX_IRAM_ECC; break; \ 103 case e_FM_EX_MURAM_ECC: \ 104 bitMask = FM_EX_NURAM_ECC; break; \ 105 default: bitMask = 0;break;} 106 107/**************************************************************************//** 108 @Description defaults 109*//***************************************************************************/ 110#define DEFAULT_exceptions (FM_EX_DMA_BUS_ERROR |\ 111 FM_EX_DMA_READ_ECC |\ 112 FM_EX_DMA_SYSTEM_WRITE_ECC |\ 113 FM_EX_DMA_FM_WRITE_ECC |\ 114 FM_EX_FPM_STALL_ON_TASKS |\ 115 FM_EX_FPM_SINGLE_ECC |\ 116 FM_EX_FPM_DOUBLE_ECC |\ 117 FM_EX_QMI_SINGLE_ECC |\ 118 FM_EX_QMI_DEQ_FROM_UNKNOWN_PORTID|\ 119 FM_EX_QMI_DOUBLE_ECC |\ 120 FM_EX_BMI_LIST_RAM_ECC |\ 121 FM_EX_BMI_PIPELINE_ECC |\ 122 FM_EX_BMI_STATISTICS_RAM_ECC |\ 123 FM_EX_BMI_DISPATCH_RAM_ECC |\ 124 FM_EX_IRAM_ECC |\ 125 FM_EX_NURAM_ECC ) 126#define DEFAULT_totalNumOfTasks (BMI_MAX_NUM_OF_TASKS*3/4) 127#define DEFAULT_totalFifoSize (BMI_MAX_FIFO_SIZE*3/4) 128#define DEFAULT_maxNumOfOpenDmas (BMI_MAX_NUM_OF_DMAS*3/4) 129#define DEFAULT_eccEnable FALSE 130#define DEFAULT_dispLimit 0 131#define DEFAULT_prsDispTh 16 132#define DEFAULT_plcrDispTh 16 133#define DEFAULT_kgDispTh 16 134#define DEFAULT_bmiDispTh 16 135#define DEFAULT_qmiEnqDispTh 16 136#define DEFAULT_qmiDeqDispTh 16 137#define DEFAULT_fmCtl1DispTh 16 138#define DEFAULT_fmCtl2DispTh 16 139#define DEFAULT_cacheOverride e_FM_DMA_NO_CACHE_OR 140#ifdef FM_PEDANTIC_DMA 141#define DEFAULT_aidOverride TRUE 142#else 143#define DEFAULT_aidOverride FALSE 144#endif /* FM_PEDANTIC_DMA */ 145#define DEFAULT_aidMode e_FM_DMA_AID_OUT_TNUM 146#define DEFAULT_dmaStopOnBusError FALSE 147#define DEFAULT_stopAtBusError FALSE 148#define DEFAULT_axiDbgNumOfBeats 1 149#define DEFAULT_dmaCamNumOfEntries 32 150#define DEFAULT_dmaCommQLow ((DMA_THRESH_MAX_COMMQ+1)/2) 151#define DEFAULT_dmaCommQHigh ((DMA_THRESH_MAX_COMMQ+1)*3/4) 152#define DEFAULT_dmaReadIntBufLow ((DMA_THRESH_MAX_BUF+1)/2) 153#define DEFAULT_dmaReadIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4) 154#define DEFAULT_dmaWriteIntBufLow ((DMA_THRESH_MAX_BUF+1)/2) 155#define DEFAULT_dmaWriteIntBufHigh ((DMA_THRESH_MAX_BUF+1)*3/4) 156#define DEFAULT_dmaSosEmergency 0 157#define DEFAULT_dmaDbgCntMode e_FM_DMA_DBG_NO_CNT 158#define DEFAULT_catastrophicErr e_FM_CATASTROPHIC_ERR_STALL_PORT 159#define DEFAULT_dmaErr e_FM_DMA_ERR_CATASTROPHIC 160#define DEFAULT_resetOnInit FALSE 161#define DEFAULT_haltOnExternalActivation FALSE /* do not change! if changed, must be disabled for rev1 ! */ 162#define DEFAULT_haltOnUnrecoverableEccError FALSE /* do not change! if changed, must be disabled for rev1 ! */ 163#define DEFAULT_externalEccRamsEnable FALSE 164#define DEFAULT_VerifyUcode FALSE 165#define DEFAULT_tnumAgingPeriod 0 166#define DEFAULT_dmaWatchdog 0 /* disabled */ 167#define DEFAULT_mtu 9600 168 169/**************************************************************************//** 170 @Description Modules registers offsets 171*//***************************************************************************/ 172#define FM_MM_MURAM 0x00000000 173#define FM_MM_BMI 0x00080000 174#define FM_MM_QMI 0x00080400 175#define FM_MM_PRS 0x000c7000 176#define FM_MM_KG 0x000C1000 177#define FM_MM_DMA 0x000C2000 178#define FM_MM_FPM 0x000C3000 179#define FM_MM_PLCR 0x000C0000 180#define FM_MM_IMEM 0x000C4000 181 182/**************************************************************************//** 183 @Description Interrupt Enable/Mask 184*//***************************************************************************/ 185 186/**************************************************************************//** 187 @Description Memory Mapped Registers 188*//***************************************************************************/ 189 190#if defined(__MWERKS__) && !defined(__GNUC__) 191#pragma pack(push,1) 192#endif /* defined(__MWERKS__) && ... */ 193#define MEM_MAP_START 194 195typedef _Packed struct 196{ 197 volatile uint32_t fpmtnc; /**< FPM TNUM Control */ 198 volatile uint32_t fpmpr; /**< FPM Port_ID FmCtl Association */ 199 volatile uint32_t brkc; /**< FPM Breakpoint Control */ 200 volatile uint32_t fpmflc; /**< FPM Flush Control */ 201 volatile uint32_t fpmdis1; /**< FPM Dispatch Thresholds1 */ 202 volatile uint32_t fpmdis2; /**< FPM Dispatch Thresholds2 */ 203 volatile uint32_t fmepi; /**< FM Error Pending Interrupts */ 204 volatile uint32_t fmrie; /**< FM Error Interrupt Enable */ 205 volatile uint32_t fmfpfcev[4]; /**< FPM FMan-Controller Event 1-4 */ 206 volatile uint8_t res1[16]; /**< reserved */ 207 volatile uint32_t fmfpfcee[4]; /**< PM FMan-Controller Event 1-4 */ 208 volatile uint8_t res2[16]; /**< reserved */ 209 volatile uint32_t fpmtsc1; /**< FPM TimeStamp Control1 */ 210 volatile uint32_t fpmtsc2; /**< FPM TimeStamp Control2 */ 211 volatile uint32_t fpmtsp; /**< FPM Time Stamp */ 212 volatile uint32_t fpmtsf; /**< FPM Time Stamp Fraction */ 213 volatile uint32_t fmrcr; /**< FM Rams Control */ 214 volatile uint32_t fpmextc; /**< FPM External Requests Control */ 215 volatile uint32_t fpmext1; /**< FPM External Requests Config1 */ 216 volatile uint32_t fpmext2; /**< FPM External Requests Config2 */ 217 volatile uint32_t fpmdrd[16]; /**< FPM Data_Ram Data 0-15 */ 218 volatile uint32_t fpmdra; /**< FPM Data Ram Access */ 219 volatile uint32_t fm_ip_rev_1; /**< FM IP Block Revision 1 */ 220 volatile uint32_t fm_ip_rev_2; /**< FM IP Block Revision 2 */ 221 volatile uint32_t fmrstc; /**< FM Reset Command */ 222 volatile uint32_t fmcld; /**< FM Classifier Debug */ 223 volatile uint32_t fmnpi; /**< FM Normal Pending Interrupts */ 224 volatile uint32_t fmfp_exte; /**< FPM External Requests Enable */ 225 volatile uint32_t fpmem; /**< FPM Event & Mask */ 226 volatile uint32_t fpmcev[4]; /**< FPM CPU Event 1-4 */ 227 volatile uint8_t res4[16]; /**< reserved */ 228 volatile uint32_t fmfp_ps[0x40]; /**< FPM Port Status */ 229 volatile uint8_t reserved1[0x260]; 230 volatile uint32_t fpmts[128]; /**< 0x400: FPM Task Status */ 231} _PackedType t_FmFpmRegs; 232 233#define NUM_OF_DBG_TRAPS 3 234 235typedef _Packed struct 236{ 237 volatile uint32_t fmbm_init; /**< BMI Initialization */ 238 volatile uint32_t fmbm_cfg1; /**< BMI Configuration 1 */ 239 volatile uint32_t fmbm_cfg2; /**< BMI Configuration 2 */ 240 volatile uint32_t reserved[5]; 241 volatile uint32_t fmbm_ievr; /**< Interrupt Event Register */ 242 volatile uint32_t fmbm_ier; /**< Interrupt Enable Register */ 243 volatile uint32_t fmbm_ifr; /**< Interrupt Force Register */ 244 volatile uint32_t reserved1[5]; 245 volatile uint32_t fmbm_arb[8]; /**< BMI Arbitration */ 246 volatile uint32_t reserved2[12]; 247 volatile uint32_t fmbm_dtc[NUM_OF_DBG_TRAPS]; /**< BMI Debug Trap Counter */ 248 volatile uint32_t reserved3; 249 volatile uint32_t fmbm_dcv[NUM_OF_DBG_TRAPS][4]; /**< BMI Debug Compare Value */ 250 volatile uint32_t fmbm_dcm[NUM_OF_DBG_TRAPS][4]; /**< BMI Debug Compare Mask */ 251 volatile uint32_t fmbm_gde; /**< BMI Global Debug Enable */ 252 volatile uint32_t fmbm_pp[63]; /**< BMI Port Parameters */ 253 volatile uint32_t reserved4; 254 volatile uint32_t fmbm_pfs[63]; /**< BMI Port FIFO Size */ 255 volatile uint32_t reserved5; 256 volatile uint32_t fmbm_ppid[63]; /**< Port Partition ID */ 257} _PackedType t_FmBmiRegs; 258 259typedef _Packed struct 260{ 261 volatile uint32_t fmqm_gc; /**< General Configuration Register */ 262 volatile uint32_t Reserved0; 263 volatile uint32_t fmqm_eie; /**< Error Interrupt Event Register */ 264 volatile uint32_t fmqm_eien; /**< Error Interrupt Enable Register */ 265 volatile uint32_t fmqm_eif; /**< Error Interrupt Force Register */ 266 volatile uint32_t fmqm_ie; /**< Interrupt Event Register */ 267 volatile uint32_t fmqm_ien; /**< Interrupt Enable Register */ 268 volatile uint32_t fmqm_if; /**< Interrupt Force Register */ 269 volatile uint32_t fmqm_gs; /**< Global Status Register */ 270 volatile uint32_t fmqm_ts; /**< Task Status Register */ 271 volatile uint32_t fmqm_etfc; /**< Enqueue Total Frame Counter */ 272 volatile uint32_t fmqm_dtfc; /**< Dequeue Total Frame Counter */ 273 volatile uint32_t fmqm_dc0; /**< Dequeue Counter 0 */ 274 volatile uint32_t fmqm_dc1; /**< Dequeue Counter 1 */ 275 volatile uint32_t fmqm_dc2; /**< Dequeue Counter 2 */ 276 volatile uint32_t fmqm_dc3; /**< Dequeue Counter 3 */ 277 volatile uint32_t fmqm_dfdc; /**< Dequeue FQID from Default Counter */ 278 volatile uint32_t fmqm_dfcc; /**< Dequeue FQID from Context Counter */ 279 volatile uint32_t fmqm_dffc; /**< Dequeue FQID from FD Counter */ 280 volatile uint32_t fmqm_dcc; /**< Dequeue Confirm Counter */ 281 volatile uint32_t Reserved1a[7]; 282 volatile uint32_t fmqm_tapc; /**< Tnum Aging Period Control */ 283 volatile uint32_t fmqm_dmcvc; /**< Dequeue MAC Command Valid Counter */ 284 volatile uint32_t fmqm_difdcc; /**< Dequeue Invalid FD Command Counter */ 285 volatile uint32_t fmqm_da1v; /**< Dequeue A1 Valid Counter */ 286 volatile uint32_t Reserved1b; 287 volatile uint32_t fmqm_dtc; /**< 0x0080 Debug Trap Counter */ 288 volatile uint32_t fmqm_efddd; /**< 0x0084 Enqueue Frame Descriptor Dynamic Debug */ 289 volatile uint32_t Reserved3[2]; 290 _Packed struct { 291 volatile uint32_t fmqm_dtcfg1; /**< 0x0090 Debug Trap Configuration 1 Register */ 292 volatile uint32_t fmqm_dtval1; /**< Debug Trap Value 1 Register */ 293 volatile uint32_t fmqm_dtm1; /**< Debug Trap Mask 1 Register */ 294 volatile uint32_t fmqm_dtc1; /**< Debug Trap Counter 1 Register */ 295 volatile uint32_t fmqm_dtcfg2; /**< Debug Trap Configuration 2 Register */ 296 volatile uint32_t fmqm_dtval2; /**< Debug Trap Value 2 Register */ 297 volatile uint32_t fmqm_dtm2; /**< Debug Trap Mask 2 Register */ 298 volatile uint32_t Reserved1; 299 } _PackedType dbgTraps[NUM_OF_DBG_TRAPS]; 300} _PackedType t_FmQmiRegs; 301 302typedef _Packed struct 303{ 304 volatile uint32_t fmdmsr; /**< FM DMA status register 0x04 */ 305 volatile uint32_t fmdmmr; /**< FM DMA mode register 0x08 */ 306 volatile uint32_t fmdmtr; /**< FM DMA bus threshold register 0x0c */ 307 volatile uint32_t fmdmhy; /**< FM DMA bus hysteresis register 0x10 */ 308 volatile uint32_t fmdmsetr; /**< FM DMA SOS emergency Threshold Register 0x14 */ 309 volatile uint32_t fmdmtah; /**< FM DMA transfer bus address high register 0x18 */ 310 volatile uint32_t fmdmtal; /**< FM DMA transfer bus address low register 0x1C */ 311 volatile uint32_t fmdmtcid; /**< FM DMA transfer bus communication ID register 0x20 */ 312 volatile uint32_t fmdmra; /**< FM DMA bus internal ram address register 0x24 */ 313 volatile uint32_t fmdmrd; /**< FM DMA bus internal ram data register 0x28 */ 314 volatile uint32_t fmdmwcr; /**< FM DMA CAM watchdog counter value 0x2C */ 315 volatile uint32_t fmdmebcr; /**< FM DMA CAM base in MURAM register 0x30 */ 316 volatile uint32_t fmdmccqdr; /**< FM DMA CAM and CMD Queue Debug register 0x34 */ 317 volatile uint32_t fmdmccqvr1; /**< FM DMA CAM and CMD Queue Value register #1 0x38 */ 318 volatile uint32_t fmdmccqvr2; /**< FM DMA CAM and CMD Queue Value register #2 0x3C */ 319 volatile uint32_t fmdmcqvr3; /**< FM DMA CMD Queue Value register #3 0x40 */ 320 volatile uint32_t fmdmcqvr4; /**< FM DMA CMD Queue Value register #4 0x44 */ 321 volatile uint32_t fmdmcqvr5; /**< FM DMA CMD Queue Value register #5 0x48 */ 322 volatile uint32_t fmdmsefrc; /**< FM DMA Semaphore Entry Full Reject Counter 0x50 */ 323 volatile uint32_t fmdmsqfrc; /**< FM DMA Semaphore Queue Full Reject Counter 0x54 */ 324 volatile uint32_t fmdmssrc; /**< FM DMA Semaphore SYNC Reject Counter 0x54 */ 325 volatile uint32_t fmdmdcr; /**< FM DMA Debug Counter */ 326 volatile uint32_t fmdmemsr; /**< FM DMA Emrgency Smoother Register */ 327 volatile uint32_t reserved; 328 volatile uint32_t fmdmplr[FM_SIZE_OF_LIODN_TABLE/2]; 329 /**< FM DMA PID-LIODN # register */ 330} _PackedType t_FmDmaRegs; 331 332typedef _Packed struct 333{ 334 volatile uint32_t iadd; /**< FM IRAM instruction address register */ 335 volatile uint32_t idata; /**< FM IRAM instruction data register */ 336 volatile uint32_t itcfg; /**< FM IRAM timing config register */ 337 volatile uint32_t iready; /**< FM IRAM ready register */ 338 volatile uint8_t res[0x80000-0x10]; 339} _PackedType t_FMIramRegs; 340 341#define MEM_MAP_END 342#if defined(__MWERKS__) && !defined(__GNUC__) 343#pragma pack(pop) 344#endif /* defined(__MWERKS__) && ... */ 345 346 347/**************************************************************************//** 348 @Description General defines 349*//***************************************************************************/ 350 351#define FM_DEBUG_STATUS_REGISTER_OFFSET 0x000d1084UL 352#define FM_UCODE_DEBUG_INSTRUCTION 0x6ffff805UL 353 354 355/**************************************************************************//** 356 @Description DMA definitions 357*//***************************************************************************/ 358 359/* masks */ 360#define DMA_MODE_AID_OR 0x20000000 361#define DMA_MODE_SBER 0x10000000 362#define DMA_MODE_BER 0x00200000 363#define DMA_MODE_ECC 0x00000020 364#define DMA_MODE_PRIVILEGE_PROT 0x00001000 365#define DMA_MODE_SECURE_PROT 0x00000800 366#define DMA_MODE_EMERGENCY_READ 0x00080000 367#define DMA_MODE_EMERGENCY_WRITE 0x00040000 368 369#define DMA_TRANSFER_PORTID_MASK 0xFF000000 370#define DMA_TRANSFER_TNUM_MASK 0x00FF0000 371#define DMA_TRANSFER_LIODN_MASK 0x00000FFF 372 373#define DMA_HIGH_LIODN_MASK 0x0FFF0000 374#define DMA_LOW_LIODN_MASK 0x00000FFF 375 376#define DMA_STATUS_CMD_QUEUE_NOT_EMPTY 0x10000000 377#define DMA_STATUS_BUS_ERR 0x08000000 378#define DMA_STATUS_READ_ECC 0x04000000 379#define DMA_STATUS_SYSTEM_WRITE_ECC 0x02000000 380#define DMA_STATUS_FM_WRITE_ECC 0x01000000 381#define DMA_STATUS_SYSTEM_DPEXT_ECC 0x00800000 382#define DMA_STATUS_FM_DPEXT_ECC 0x00400000 383#define DMA_STATUS_SYSTEM_DPDAT_ECC 0x00200000 384#define DMA_STATUS_FM_DPDAT_ECC 0x00100000 385#define DMA_STATUS_FM_SPDAT_ECC 0x00080000 386 387#define FM_LIODN_BASE_MASK 0x00000FFF 388 389/* shifts */ 390#define DMA_MODE_CACHE_OR_SHIFT 30 391#define DMA_MODE_BUS_PRI_SHIFT 16 392#define DMA_MODE_AXI_DBG_SHIFT 24 393#define DMA_MODE_CEN_SHIFT 13 394#define DMA_MODE_BUS_PROT_SHIFT 10 395#define DMA_MODE_DBG_SHIFT 7 396#define DMA_MODE_EMERGENCY_LEVEL_SHIFT 6 397#define DMA_MODE_AID_MODE_SHIFT 4 398#define DMA_MODE_MAX_AXI_DBG_NUM_OF_BEATS 16 399#define DMA_MODE_MAX_CAM_NUM_OF_ENTRIES 32 400 401#define DMA_THRESH_COMMQ_SHIFT 24 402#define DMA_THRESH_READ_INT_BUF_SHIFT 16 403 404#define DMA_LIODN_SHIFT 16 405 406#define DMA_TRANSFER_PORTID_SHIFT 24 407#define DMA_TRANSFER_TNUM_SHIFT 16 408 409/* sizes */ 410#define DMA_MAX_WATCHDOG 0xffffffff 411 412/* others */ 413#define DMA_CAM_SIZEOF_ENTRY 0x40 414#define DMA_CAM_ALIGN 0x1000 415#define DMA_CAM_UNITS 8 416 417 418/**************************************************************************//** 419 @Description FPM defines 420*//***************************************************************************/ 421 422/* masks */ 423#define FPM_EV_MASK_DOUBLE_ECC 0x80000000 424#define FPM_EV_MASK_STALL 0x40000000 425#define FPM_EV_MASK_SINGLE_ECC 0x20000000 426#define FPM_EV_MASK_RELEASE_FM 0x00010000 427#define FPM_EV_MASK_DOUBLE_ECC_EN 0x00008000 428#define FPM_EV_MASK_STALL_EN 0x00004000 429#define FPM_EV_MASK_SINGLE_ECC_EN 0x00002000 430#define FPM_EV_MASK_EXTERNAL_HALT 0x00000008 431#define FPM_EV_MASK_ECC_ERR_HALT 0x00000004 432 433#define FPM_RAM_CTL_RAMS_ECC_EN 0x80000000 434#define FPM_RAM_CTL_IRAM_ECC_EN 0x40000000 435#define FPM_RAM_CTL_MURAM_ECC 0x00008000 436#define FPM_RAM_CTL_IRAM_ECC 0x00004000 437#define FPM_RAM_CTL_MURAM_TEST_ECC 0x20000000 438#define FPM_RAM_CTL_IRAM_TEST_ECC 0x10000000 439#define FPM_RAM_CTL_RAMS_ECC_EN_SRC_SEL 0x08000000 440 441#define FPM_IRAM_ECC_ERR_EX_EN 0x00020000 442#define FPM_MURAM_ECC_ERR_EX_EN 0x00040000 443 444#define FPM_REV1_MAJOR_MASK 0x0000FF00 445#define FPM_REV1_MINOR_MASK 0x000000FF 446 447#define FPM_REV2_INTEG_MASK 0x00FF0000 448#define FPM_REV2_ERR_MASK 0x0000FF00 449#define FPM_REV2_CFG_MASK 0x000000FF 450 451#define FPM_TS_FRACTION_MASK 0x0000FFFF 452#define FPM_TS_CTL_EN 0x80000000 453 454#define FPM_PORT_FM_CTL1 0x00000001 455#define FPM_PORT_FM_CTL2 0x00000002 456#define FPM_PRC_REALSE_STALLED 0x00800000 457 458#define FPM_PS_STALLED 0x00800000 459#define FPM_PS_FM_CTL1_SEL 0x80000000 460#define FPM_PS_FM_CTL2_SEL 0x40000000 461#define FPM_PS_FM_CTL_SEL_MASK (FPM_PS_FM_CTL1_SEL | FPM_PS_FM_CTL2_SEL) 462 463#define FPM_RSTC_FM_RESET 0x80000000 464#define FPM_RSTC_10G0_RESET 0x04000000 465#define FPM_RSTC_1G0_RESET 0x40000000 466#define FPM_RSTC_1G1_RESET 0x20000000 467#define FPM_RSTC_1G2_RESET 0x10000000 468#define FPM_RSTC_1G3_RESET 0x08000000 469#define FPM_RSTC_1G4_RESET 0x02000000 470 471 472/* shifts */ 473#define FPM_DISP_LIMIT_SHIFT 24 474 475#define FPM_THR1_PRS_SHIFT 24 476#define FPM_THR1_KG_SHIFT 16 477#define FPM_THR1_PLCR_SHIFT 8 478#define FPM_THR1_BMI_SHIFT 0 479 480#define FPM_THR2_QMI_ENQ_SHIFT 24 481#define FPM_THR2_QMI_DEQ_SHIFT 0 482#define FPM_THR2_FM_CTL1_SHIFT 16 483#define FPM_THR2_FM_CTL2_SHIFT 8 484 485#define FPM_EV_MASK_CAT_ERR_SHIFT 1 486#define FPM_EV_MASK_DMA_ERR_SHIFT 0 487 488#define FPM_REV1_MAJOR_SHIFT 8 489#define FPM_REV1_MINOR_SHIFT 0 490 491#define FPM_REV2_INTEG_SHIFT 16 492#define FPM_REV2_ERR_SHIFT 8 493#define FPM_REV2_CFG_SHIFT 0 494 495#define FPM_TS_INT_SHIFT 16 496 497#define FPM_PORT_FM_CTL_PORTID_SHIFT 24 498 499#define FPM_PS_FM_CTL_SEL_SHIFT 30 500#define FPM_PRC_ORA_FM_CTL_SEL_SHIFT 16 501 502/* Interrupts defines */ 503#define FPM_EVENT_FM_CTL_0 0x00008000 504#define FPM_EVENT_FM_CTL 0x0000FF00 505#define FPM_EVENT_FM_CTL_BRK 0x00000080 506 507/* others */ 508#define FPM_MAX_DISP_LIMIT 31 509 510/**************************************************************************//** 511 @Description BMI defines 512*//***************************************************************************/ 513/* masks */ 514#define BMI_INIT_START 0x80000000 515#define BMI_ERR_INTR_EN_PIPELINE_ECC 0x80000000 516#define BMI_ERR_INTR_EN_LIST_RAM_ECC 0x40000000 517#define BMI_ERR_INTR_EN_STATISTICS_RAM_ECC 0x20000000 518#define BMI_ERR_INTR_EN_DISPATCH_RAM_ECC 0x10000000 519#define BMI_NUM_OF_TASKS_MASK 0x3F000000 520#define BMI_NUM_OF_EXTRA_TASKS_MASK 0x000F0000 521#define BMI_NUM_OF_DMAS_MASK 0x00000F00 522#define BMI_NUM_OF_EXTRA_DMAS_MASK 0x0000000F 523#define BMI_FIFO_SIZE_MASK 0x000003FF 524#define BMI_EXTRA_FIFO_SIZE_MASK 0x03FF0000 525#define BMI_CFG2_DMAS_MASK 0x0000003F 526 527/* shifts */ 528#define BMI_CFG2_TASKS_SHIFT 16 529#define BMI_CFG2_DMAS_SHIFT 0 530#define BMI_CFG1_FIFO_SIZE_SHIFT 16 531#define BMI_FIFO_SIZE_SHIFT 0 532#define BMI_EXTRA_FIFO_SIZE_SHIFT 16 533#define BMI_NUM_OF_TASKS_SHIFT 24 534#define BMI_EXTRA_NUM_OF_TASKS_SHIFT 16 535#define BMI_NUM_OF_DMAS_SHIFT 8 536#define BMI_EXTRA_NUM_OF_DMAS_SHIFT 0 537 538/* others */ 539#define BMI_FIFO_ALIGN 0x100 540 541 542/**************************************************************************//** 543 @Description QMI defines 544*//***************************************************************************/ 545/* masks */ 546#define QMI_CFG_ENQ_EN 0x80000000 547#define QMI_CFG_DEQ_EN 0x40000000 548#define QMI_CFG_EN_COUNTERS 0x10000000 549#define QMI_CFG_SOFT_RESET 0x01000000 550#define QMI_CFG_DEQ_MASK 0x0000003F 551#define QMI_CFG_ENQ_MASK 0x00003F00 552 553#define QMI_ERR_INTR_EN_DOUBLE_ECC 0x80000000 554#define QMI_ERR_INTR_EN_DEQ_FROM_DEF 0x40000000 555#define QMI_INTR_EN_SINGLE_ECC 0x80000000 556 557/* shifts */ 558#define QMI_CFG_ENQ_SHIFT 8 559#define QMI_TAPC_TAP 22 560 561 562/**************************************************************************//** 563 @Description IRAM defines 564*//***************************************************************************/ 565/* masks */ 566#define IRAM_IADD_AIE 0x80000000 567#define IRAM_READY 0x80000000 568 569typedef struct { 570 void (*f_Isr) (t_Handle h_Arg, uint32_t event); 571 t_Handle h_SrcHandle; 572} t_FmanCtrlIntrSrc; 573 574 575typedef struct 576{ 577 /* uint8_t numOfPartitions; */ 578 bool resetOnInit; 579#ifdef FM_PARTITION_ARRAY 580 uint16_t liodnBasePerPort[FM_SIZE_OF_LIODN_TABLE]; 581#endif 582 bool enCounters; 583 t_FmThresholds thresholds; 584 e_FmDmaCacheOverride dmaCacheOverride; 585 e_FmDmaAidMode dmaAidMode; 586 bool dmaAidOverride; 587 uint8_t dmaAxiDbgNumOfBeats; 588 uint8_t dmaCamNumOfEntries; 589 uint32_t dmaWatchdog; 590 t_FmDmaThresholds dmaCommQThresholds; 591 t_FmDmaThresholds dmaWriteBufThresholds; 592 t_FmDmaThresholds dmaReadBufThresholds; 593 uint32_t dmaSosEmergency; 594 e_FmDmaDbgCntMode dmaDbgCntMode; 595 bool dmaStopOnBusError; 596 bool dmaEnEmergency; 597 t_FmDmaEmergency dmaEmergency; 598 bool dmaEnEmergencySmoother; 599 uint32_t dmaEmergencySwitchCounter; 600 bool haltOnExternalActivation; 601 bool haltOnUnrecoverableEccError; 602 e_FmCatastrophicErr catastrophicErr; 603 e_FmDmaErr dmaErr; 604 bool enMuramTestMode; 605 bool enIramTestMode; 606 bool externalEccRamsEnable; 607 uint16_t tnumAgingPeriod; 608 t_FmPcdFirmwareParams firmware; 609 bool fwVerify; 610} t_FmDriverParam; 611 612typedef void (t_FmanCtrlIsr)( t_Handle h_Fm, uint32_t event); 613 614typedef struct 615{ 616/***************************/ 617/* Master/Guest parameters */ 618/***************************/ 619 uint8_t fmId; 620 e_FmPortType portsTypes[FM_MAX_NUM_OF_HW_PORT_IDS]; 621 uint16_t fmClkFreq; 622/**************************/ 623/* Master Only parameters */ 624/**************************/ 625 bool enabledTimeStamp; 626 uint8_t count1MicroBit; 627 uint8_t totalNumOfTasks; 628 uint32_t totalFifoSize; 629 uint8_t maxNumOfOpenDmas; 630 uint8_t accumulatedNumOfTasks; 631 uint32_t accumulatedFifoSize; 632 uint8_t accumulatedNumOfOpenDmas; 633#ifdef FM_QMI_DEQ_OPTIONS_SUPPORT 634 uint8_t accumulatedNumOfDeqTnums; 635#endif /* FM_QMI_DEQ_OPTIONS_SUPPORT */ 636#ifdef FM_LOW_END_RESTRICTION 637 bool lowEndRestriction; 638#endif /* FM_LOW_END_RESTRICTION */ 639 uint32_t exceptions; 640 int irq; 641 int errIrq; 642 bool ramsEccEnable; 643 bool explicitEnable; 644 bool internalCall; 645 uint8_t ramsEccOwners; 646 uint32_t extraFifoPoolSize; 647 uint8_t extraTasksPoolSize; 648 uint8_t extraOpenDmasPoolSize; 649#if defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS) 650 uint16_t macMaxFrameLengths10G[FM_MAX_NUM_OF_10G_MACS]; 651#endif /* defined(FM_MAX_NUM_OF_10G_MACS) && (FM_MAX_NUM_OF_10G_MACS) */ 652 uint16_t macMaxFrameLengths1G[FM_MAX_NUM_OF_1G_MACS]; 653} t_FmStateStruct; 654 655typedef struct 656{ 657/***************************/ 658/* Master/Guest parameters */ 659/***************************/ 660/* locals for recovery */ 661 uintptr_t baseAddr; 662 663/* un-needed for recovery */ 664 t_Handle h_Pcd; 665 char fmModuleName[MODULE_NAME_SIZE]; 666 char fmIpcHandlerModuleName[FM_MAX_NUM_OF_GUESTS][MODULE_NAME_SIZE]; 667 t_Handle h_IpcSessions[FM_MAX_NUM_OF_GUESTS]; 668 t_FmIntrSrc intrMng[e_FM_EV_DUMMY_LAST]; /* FM exceptions user callback */ 669 uint8_t guestId; 670/**************************/ 671/* Master Only parameters */ 672/**************************/ 673/* locals for recovery */ 674 t_FmFpmRegs *p_FmFpmRegs; 675 t_FmBmiRegs *p_FmBmiRegs; 676 t_FmQmiRegs *p_FmQmiRegs; 677 t_FmDmaRegs *p_FmDmaRegs; 678 t_FmExceptionsCallback *f_Exception; 679 t_FmBusErrorCallback *f_BusError; 680 t_Handle h_App; /* Application handle */ 681 t_Handle h_Spinlock; 682 bool recoveryMode; 683 t_FmStateStruct *p_FmStateStruct; 684 685/* un-needed for recovery */ 686 t_FmDriverParam *p_FmDriverParam; 687 t_Handle h_FmMuram; 688 uint64_t fmMuramPhysBaseAddr; 689 bool independentMode; 690 bool hcPortInitialized; 691 uintptr_t camBaseAddr; /* save for freeing */ 692 uintptr_t resAddr; 693 uintptr_t fifoBaseAddr; /* save for freeing */ 694 t_FmanCtrlIntrSrc fmanCtrlIntr[FM_NUM_OF_FMAN_CTRL_EVENT_REGS]; /* FM exceptions user callback */ 695 bool usedEventRegs[FM_NUM_OF_FMAN_CTRL_EVENT_REGS]; 696} t_Fm; 697 698 699#endif /* __FM_H */ 700