dtrace_asm.S revision 242723
1242723Sjhibbits/* 2242723Sjhibbits * CDDL HEADER START 3242723Sjhibbits * 4242723Sjhibbits * The contents of this file are subject to the terms of the 5242723Sjhibbits * Common Development and Distribution License, Version 1.0 only 6242723Sjhibbits * (the "License"). You may not use this file except in compliance 7242723Sjhibbits * with the License. 8242723Sjhibbits * 9242723Sjhibbits * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10242723Sjhibbits * or http://www.opensolaris.org/os/licensing. 11242723Sjhibbits * See the License for the specific language governing permissions 12242723Sjhibbits * and limitations under the License. 13242723Sjhibbits * 14242723Sjhibbits * When distributing Covered Code, include this CDDL HEADER in each 15242723Sjhibbits * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16242723Sjhibbits * If applicable, add the following below this CDDL HEADER, with the 17242723Sjhibbits * fields enclosed by brackets "[]" replaced with your own identifying 18242723Sjhibbits * information: Portions Copyright [yyyy] [name of copyright owner] 19242723Sjhibbits * 20242723Sjhibbits * CDDL HEADER END 21242723Sjhibbits * 22242723Sjhibbits * $FreeBSD: head/sys/cddl/dev/dtrace/powerpc/dtrace_asm.S 242723 2012-11-07 23:45:09Z jhibbits $ 23242723Sjhibbits */ 24242723Sjhibbits/* 25242723Sjhibbits * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 26242723Sjhibbits * Use is subject to license terms. 27242723Sjhibbits */ 28242723Sjhibbits 29242723Sjhibbits#include "assym.s" 30242723Sjhibbits 31242723Sjhibbits#define _ASM 32242723Sjhibbits 33242723Sjhibbits#include <sys/cpuvar_defs.h> 34242723Sjhibbits#include <sys/dtrace.h> 35242723Sjhibbits 36242723Sjhibbits#include <machine/asm.h> 37242723Sjhibbits/* 38242723Sjhibbits#include <machine/cpu.h> 39242723Sjhibbits*/ 40242723Sjhibbits 41242723Sjhibbits/* 42242723Sjhibbits * Primitives 43242723Sjhibbits */ 44242723Sjhibbits 45242723Sjhibbits .text 46242723Sjhibbits 47242723Sjhibbits/* 48242723Sjhibbitsvoid dtrace_membar_producer(void) 49242723Sjhibbits*/ 50242723SjhibbitsASENTRY_NOPROF(dtrace_membar_producer) 51242723Sjhibbits blr 52242723SjhibbitsEND(dtrace_membar_producer) 53242723Sjhibbits 54242723Sjhibbits/* 55242723Sjhibbitsvoid dtrace_membar_consumer(void) 56242723Sjhibbits*/ 57242723SjhibbitsASENTRY_NOPROF(dtrace_membar_consumer) 58242723Sjhibbits blr 59242723SjhibbitsEND(dtrace_membar_consumer) 60242723Sjhibbits 61242723Sjhibbits/* 62242723Sjhibbitsdtrace_icookie_t dtrace_interrupt_disable(void) 63242723Sjhibbits*/ 64242723SjhibbitsASENTRY_NOPROF(dtrace_interrupt_disable) 65242723Sjhibbits mfmsr %r3 66242723Sjhibbits andi. %r0,%r3,~PSL_EE@l 67242723Sjhibbits mtmsr %r0 68242723Sjhibbits blr 69242723SjhibbitsEND(dtrace_interrupt_disable) 70242723Sjhibbits 71242723Sjhibbits/* 72242723Sjhibbitsvoid dtrace_interrupt_enable(dtrace_icookie_t cookie) 73242723Sjhibbits*/ 74242723SjhibbitsASENTRY_NOPROF(dtrace_interrupt_enable) 75242723Sjhibbits mtmsr %r3 76242723Sjhibbits blr 77242723SjhibbitsEND(dtrace_interrupt_enable) 78242723Sjhibbits 79242723Sjhibbits/* 80242723Sjhibbitsuint32_t dtrace_cas32(uint32_t *target, uint32_t cmp, uint32_t new) 81242723Sjhibbits*/ 82242723SjhibbitsASENTRY_NOPROF(dtrace_cas32) 83242723Sjhibbits1: 84242723Sjhibbits lwarx %r0,0,%r3 85242723Sjhibbits cmpw %r4,%r0 86242723Sjhibbits bne 2f 87242723Sjhibbits stwcx. %r5,0,%r3 88242723Sjhibbits bne 1b 89242723Sjhibbits2: mr %r3,%r0 90242723Sjhibbits blr 91242723SjhibbitsEND(dtrace_cas32) 92242723Sjhibbits 93242723Sjhibbits/* 94242723Sjhibbitsvoid * 95242723Sjhibbitsdtrace_casptr(void *target, void *cmp, void *new) 96242723Sjhibbits*/ 97242723SjhibbitsASENTRY_NOPROF(dtrace_casptr) 98242723Sjhibbits1: 99242723Sjhibbits lwarx %r0,0,%r3 100242723Sjhibbits cmpw %r4,%r0 101242723Sjhibbits bne 2f 102242723Sjhibbits stwcx. %r5,0,%r3 103242723Sjhibbits bne 1b 104242723Sjhibbits2: mr %r3,%r0 105242723Sjhibbits blr 106242723SjhibbitsEND(dtrace_casptr) 107242723Sjhibbits 108242723Sjhibbits 109242723Sjhibbits/* 110242723Sjhibbitsuintptr_t 111242723Sjhibbitsdtrace_fulword(void *addr) 112242723Sjhibbits*/ 113242723SjhibbitsASENTRY_NOPROF(dtrace_fulword) 114242723SjhibbitsEND(dtrace_fulword) 115242723Sjhibbits 116242723Sjhibbits/* 117242723Sjhibbitsuint8_t 118242723Sjhibbitsdtrace_fuword8_nocheck(void *addr) 119242723Sjhibbits*/ 120242723SjhibbitsASENTRY_NOPROF(dtrace_fuword8_nocheck) 121242723Sjhibbits lbz %r3,0(%r3) 122242723Sjhibbits blr 123242723SjhibbitsEND(dtrace_fuword8_nocheck) 124242723Sjhibbits 125242723Sjhibbits/* 126242723Sjhibbitsuint16_t 127242723Sjhibbitsdtrace_fuword16_nocheck(void *addr) 128242723Sjhibbits*/ 129242723SjhibbitsASENTRY_NOPROF(dtrace_fuword16_nocheck) 130242723Sjhibbits lhz %r3,0(%r3) 131242723Sjhibbits blr 132242723SjhibbitsEND(dtrace_fuword16_nocheck) 133242723Sjhibbits 134242723Sjhibbits/* 135242723Sjhibbitsuint32_t 136242723Sjhibbitsdtrace_fuword32_nocheck(void *addr) 137242723Sjhibbits*/ 138242723SjhibbitsASENTRY_NOPROF(dtrace_fuword32_nocheck) 139242723Sjhibbits lwz %r3,0(%r3) 140242723Sjhibbits blr 141242723SjhibbitsEND(dtrace_fuword32_nocheck) 142242723Sjhibbits 143242723Sjhibbits/* 144242723Sjhibbitsuint64_t 145242723Sjhibbitsdtrace_fuword64_nocheck(void *addr) 146242723Sjhibbits*/ 147242723SjhibbitsASENTRY_NOPROF(dtrace_fuword64_nocheck) 148242723Sjhibbits#if defined(__powerpc64__) 149242723Sjhibbits ld %r3,0(%r3) 150242723Sjhibbits#else 151242723Sjhibbits lwz %r5,0(%r3) 152242723Sjhibbits lwz %r4,4(%r3) 153242723Sjhibbits mr %r3,%r5 154242723Sjhibbits#endif 155242723Sjhibbits blr 156242723SjhibbitsEND(dtrace_fuword64_nocheck) 157242723Sjhibbits 158242723Sjhibbits/* 159242723SjhibbitsXXX: unoptimized 160242723Sjhibbitsvoid 161242723Sjhibbitsdtrace_copy(uintptr_t src, uintptr_t dest, size_t size) 162242723Sjhibbits*/ 163242723SjhibbitsASENTRY_NOPROF(dtrace_copy) 164242723Sjhibbits addme %r7,%r3 165242723Sjhibbits addme %r8,%r4 166242723Sjhibbits1: 167242723Sjhibbits lbzu %r3,1(%r7) 168242723Sjhibbits stbu %r3,1(%r8) 169242723Sjhibbits addme %r5,%r5 170242723Sjhibbits beq 2f 171242723Sjhibbits2: 172242723Sjhibbits blr 173242723SjhibbitsEND(dtrace_copy) 174242723Sjhibbits 175242723Sjhibbits/* 176242723Sjhibbitsvoid 177242723Sjhibbitsdtrace_copystr(uintptr_t uaddr, uintptr_t kaddr, size_t size, 178242723Sjhibbits volatile uint16_t *flags) 179242723Sjhibbits*/ 180242723SjhibbitsASENTRY_NOPROF(dtrace_copystr) 181242723Sjhibbits addme %r7,%r3 182242723Sjhibbits addme %r8,%r4 183242723Sjhibbits1: 184242723Sjhibbits lbzu %r3,1(%r7) 185242723Sjhibbits stbu %r3,1(%r8) 186242723Sjhibbits addme %r5,%r5 187242723Sjhibbits beq 2f 188242723Sjhibbits or %r3,%r3,%r3 189242723Sjhibbits beq 2f 190242723Sjhibbits andi. %r0,%r5,0x0fff 191242723Sjhibbits beq 2f 192242723Sjhibbits lwz %r0,0(%r6) 193242723Sjhibbits andi. %r0,%r0,CPU_DTRACE_BADADDR 194242723Sjhibbits beq 1b 195242723Sjhibbits2: 196242723Sjhibbits blr 197242723SjhibbitsEND(dtrace_copystr) 198242723Sjhibbits 199242723Sjhibbits/* 200242723Sjhibbitsvoid dtrace_invop_init(void) 201242723Sjhibbits*/ 202242723SjhibbitsASENTRY_NOPROF(dtrace_invop_init) 203242723Sjhibbits /* XXX: impement it properly -- implement dtrace_invop_start */ 204242723Sjhibbits li %r0,0 205242723Sjhibbits li %r3,dtrace_invop_jump_addr@l 206242723Sjhibbits addis %r3,%r3,dtrace_invop_jump_addr@ha 207242723Sjhibbits stw %r0,0(%r3) 208242723Sjhibbits blr 209242723SjhibbitsEND(dtrace_invop_init) 210242723Sjhibbits 211242723Sjhibbits/* 212242723Sjhibbitsvoid dtrace_invop_uninit(void) 213242723Sjhibbits*/ 214242723SjhibbitsASENTRY_NOPROF(dtrace_invop_uninit) 215242723Sjhibbits li %r0,0 216242723Sjhibbits li %r3,dtrace_invop_jump_addr@l 217242723Sjhibbits addis %r3,%r3,dtrace_invop_jump_addr@ha 218242723Sjhibbits stw %r0,0(%r3) 219242723Sjhibbits blr 220242723SjhibbitsEND(dtrace_invop_uninit) 221242723Sjhibbits 222242723Sjhibbits/* 223242723Sjhibbits * The panic() and cmn_err() functions invoke vpanic() as a common entry point 224242723Sjhibbits * into the panic code implemented in panicsys(). vpanic() is responsible 225242723Sjhibbits * for passing through the format string and arguments, and constructing a 226242723Sjhibbits * regs structure on the stack into which it saves the current register 227242723Sjhibbits * values. If we are not dying due to a fatal trap, these registers will 228242723Sjhibbits * then be preserved in panicbuf as the current processor state. Before 229242723Sjhibbits * invoking panicsys(), vpanic() activates the first panic trigger (see 230242723Sjhibbits * common/os/panic.c) and switches to the panic_stack if successful. Note that 231242723Sjhibbits * DTrace takes a slightly different panic path if it must panic from probe 232242723Sjhibbits * context. Instead of calling panic, it calls into dtrace_vpanic(), which 233242723Sjhibbits * sets up the initial stack as vpanic does, calls dtrace_panic_trigger(), and 234242723Sjhibbits * branches back into vpanic(). 235242723Sjhibbits */ 236242723Sjhibbits 237242723Sjhibbits/* 238242723Sjhibbitsvoid 239242723Sjhibbitsvpanic(const char *format, va_list alist) 240242723Sjhibbits*/ 241242723SjhibbitsASENTRY_NOPROF(vpanic) /* Initial stack layout: */ 242242723Sjhibbits 243242723Sjhibbitsvpanic_common: 244242723Sjhibbits blr 245242723SjhibbitsEND(vpanic) 246242723Sjhibbits 247242723Sjhibbits 248242723Sjhibbits 249242723Sjhibbits/* 250242723Sjhibbitsvoid 251242723Sjhibbitsdtrace_vpanic(const char *format, va_list alist) 252242723Sjhibbits*/ 253242723SjhibbitsASENTRY_NOPROF(dtrace_vpanic) /* Initial stack layout: */ 254242723Sjhibbits 255242723Sjhibbits#if 0 256242723Sjhibbits bl dtrace_panic_trigger /* %eax = dtrace_panic_trigger() */ 257242723Sjhibbits#endif 258242723Sjhibbits b vpanic_common 259242723SjhibbitsEND(dtrace_vpanic) 260242723Sjhibbits 261242723Sjhibbits/* 262242723Sjhibbitsuintptr_t 263242723Sjhibbitsdtrace_caller(int aframes) 264242723Sjhibbits*/ 265242723SjhibbitsASENTRY_NOPROF(dtrace_caller) 266242723Sjhibbits li %r3, -1 267242723Sjhibbits blr 268242723SjhibbitsEND(dtrace_caller) 269242723Sjhibbits 270