rocket.dts revision 303975 
1/*-
2 * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $FreeBSD: releng/11.0/sys/boot/fdt/dts/riscv/rocket.dts 298638 2016-04-26 13:22:08Z br $
35 */
36
37/dts-v1/;
38
39/ {
40	model = "UC Berkeley Spike Simulator RV64I";
41	compatible = "riscv,rv64i";
42	#address-cells = <1>;
43	#size-cells = <1>;
44	#interrupt-cells = <1>;
45
46	cpus {
47		#address-cells = <1>;
48		#size-cells = <0>;
49
50		cpu@0 {
51			device_type = "cpu";
52			compatible = "riscv,rv64i";
53			reg = <0x40002000>;
54		};
55	};
56
57	aliases {
58		console0 = &console0;
59	};
60
61	memory {
62		device_type = "memory";
63		reg = <0x0 0x10000000>; /* 256MB at 0x0 */
64	};
65
66	soc {
67		#address-cells = <2>;
68		#size-cells = <2>;
69		#interrupt-cells = <1>;
70
71		compatible = "simple-bus";
72		ranges;
73
74		pic0: pic@0 {
75			compatible = "riscv,pic";
76			interrupt-controller;
77		};
78
79		timer0: timer@0 {
80			compatible = "riscv,timer";
81			interrupts = < 1 >;
82			interrupt-parent = < &pic0 >;
83			clock-frequency = < 1000000 >;
84		};
85
86		htif0: htif@0 {
87			compatible = "riscv,htif";
88			interrupts = < 0 >;
89			interrupt-parent = < &pic0 >;
90
91			console0: console@0 {
92				compatible = "htif,console";
93				status = "okay";
94			};
95		};
96	};
97
98	chosen {
99		bootargs = "-v";
100		stdin = "console0";
101		stdout = "console0";
102	};
103};
104