xref: /freebsd-11.0-release/sys/boot/fdt/dts/riscv/rocket.dts

/*-
 * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
 * All rights reserved.
 *
 * Portions of this software were developed by SRI International and the
 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
 *
 * Portions of this software were developed by the University of Cambridge
 * Computer Laboratory as part of the CTSRD Project, with support from the
 * UK Higher Education Innovation Fund (HEIF).
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * $FreeBSD: releng/11.0/sys/boot/fdt/dts/riscv/rocket.dts 298638 2016-04-26 13:22:08Z br $
 */

/dts-v1/;

/ {
	model = "UC Berkeley Spike Simulator RV64I";
	compatible = "riscv,rv64i";
	#address-cells = <1>;
	#size-cells = <1>;
	#interrupt-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "riscv,rv64i";
			reg = <0x40002000>;
		};
	};

	aliases {
		console0 = &console0;
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x10000000>; /* 256MB at 0x0 */
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		#interrupt-cells = <1>;

		compatible = "simple-bus";
		ranges;

		pic0: pic@0 {
			compatible = "riscv,pic";
			interrupt-controller;
		};

		timer0: timer@0 {
			compatible = "riscv,timer";
			interrupts = < 1 >;
			interrupt-parent = < &pic0 >;
			clock-frequency = < 1000000 >;
		};

		htif0: htif@0 {
			compatible = "riscv,htif";
			interrupts = < 0 >;
			interrupt-parent = < &pic0 >;

			console0: console@0 {
				compatible = "htif,console";
				status = "okay";
			};
		};
	};

	chosen {
		bootargs = "-v";
		stdin = "console0";
		stdout = "console0";
	};
};