db88f6281.dts revision 301222 
1/*
2 * Copyright (c) 2009-2010 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Semihalf under sponsorship from
6 * the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * Marvell DB-88F6281 Device Tree Source.
30 *
31 * $FreeBSD: head/sys/boot/fdt/dts/arm/db88f6281.dts 301222 2016-06-02 18:35:35Z zbb $
32 */
33
34/dts-v1/;
35
36/ {
37	model = "mrvl,DB-88F6281";
38	compatible = "DB-88F6281-BP", "DB-88F6281-BP-A";
39	#address-cells = <1>;
40	#size-cells = <1>;
41
42	aliases {
43		ethernet0 = &enet0;
44		mpp = &MPP;
45		pci0 = &pci0;
46		serial0 = &serial0;
47		serial1 = &serial1;
48		soc = &SOC;
49		sram = &SRAM;
50	};
51
52	cpus {
53		#address-cells = <1>;
54		#size-cells = <0>;
55
56		cpu@0 {
57			device_type = "cpu";
58			compatible = "ARM,88FR131";
59			reg = <0x0>;
60			d-cache-line-size = <32>;	// 32 bytes
61			i-cache-line-size = <32>;	// 32 bytes
62			d-cache-size = <0x4000>;	// L1, 16K
63			i-cache-size = <0x4000>;	// L1, 16K
64			timebase-frequency = <0>;
65			bus-frequency = <0>;
66			clock-frequency = <0>;
67		};
68	};
69
70	memory {
71		device_type = "memory";
72		reg = <0x0 0x20000000>;		// 512M at 0x0
73	};
74
75	localbus@0 {
76		#address-cells = <2>;
77		#size-cells = <1>;
78		compatible = "mrvl,lbc";
79		bank-count = <3>;
80
81		/* This reflects CPU decode windows setup. */
82		ranges = <0x0 0x2f 0xf9300000 0x00100000>;
83
84		nand@0,0 {
85			#address-cells = <1>;
86			#size-cells = <1>;
87			compatible = "mrvl,nfc";
88			reg = <0x0 0x0 0x00100000>;
89			bank-width = <2>;
90			device-width = <1>;
91
92			slice@0 {
93				reg = <0x0 0x200000>;
94				label = "u-boot";
95				read-only;
96			};
97
98			slice@200000 {
99				reg = <0x200000 0x7e00000>;
100				label = "root";
101			};
102		};
103	};
104
105	SOC: soc88f6281@f1000000 {
106		#address-cells = <1>;
107		#size-cells = <1>;
108		compatible = "simple-bus";
109		ranges = <0x0 0xf1000000 0x00100000>;
110		bus-frequency = <0>;
111
112		PIC: pic@20200 {
113			interrupt-controller;
114			#address-cells = <0>;
115			#interrupt-cells = <1>;
116			reg = <0x20200 0x3c>;
117			compatible = "mrvl,pic";
118		};
119
120		timer@20300 {
121			compatible = "mrvl,timer";
122			reg = <0x20300 0x30>;
123			interrupts = <1>;
124			interrupt-parent = <&PIC>;
125			mrvl,has-wdt;
126		};
127
128		MPP: mpp@10000 {
129			#pin-cells = <2>;
130			compatible = "mrvl,mpp";
131			reg = <0x10000 0x34>;
132			pin-count = <50>;
133			pin-map = <
134				0  1		/* MPP[0]:  NF_IO[2] */
135				1  1		/* MPP[1]:  NF_IO[3] */
136				2  1		/* MPP[2]:  NF_IO[4] */
137				3  1		/* MPP[3]:  NF_IO[5] */
138				4  1		/* MPP[4]:  NF_IO[6] */
139				5  1		/* MPP[5]:  NF_IO[7] */
140				6  1		/* MPP[6]:  SYSRST_OUTn */
141				7  2		/* MPP[7]:  SPI_SCn */
142				8  1		/* MPP[8]:  TW_SDA */
143				9  1		/* MPP[9]:  TW_SCK */
144				10 3		/* MPP[10]: UA0_TXD */
145				11 3		/* MPP[11]: UA0_RXD */
146				12 1		/* MPP[12]: SD_CLK */
147				13 1		/* MPP[13]: SD_CMD */
148				14 1		/* MPP[14]: SD_D[0] */
149				15 1		/* MPP[15]: SD_D[1] */
150				16 1		/* MPP[16]: SD_D[2] */
151				17 1		/* MPP[17]: SD_D[3] */
152				18 1		/* MPP[18]: NF_IO[0] */
153				19 1		/* MPP[19]: NF_IO[1] */
154				20 5		/* MPP[20]: SATA1_AC */
155				21 5 >;		/* MPP[21]: SATA0_AC */
156		};
157
158		GPIO: gpio@10100 {
159			#gpio-cells = <3>;
160			compatible = "mrvl,gpio";
161			reg = <0x10100 0x20>;
162			gpio-controller;
163			interrupts = <35 36 37 38 39 40 41>;
164			interrupt-parent = <&PIC>;
165		};
166
167		rtc@10300 {
168			compatible = "mrvl,rtc";
169			reg = <0x10300 0x08>;
170		};
171
172		twsi@11000 {
173			#address-cells = <1>;
174			#size-cells = <0>;
175			compatible = "mrvl,twsi";
176			reg = <0x11000 0x20>;
177			interrupts = <43>;
178			interrupt-parent = <&PIC>;
179		};
180
181		enet0: ethernet@72000 {
182			#address-cells = <1>;
183			#size-cells = <1>;
184			model = "V2";
185			compatible = "mrvl,ge";
186			reg = <0x72000 0x2000>;
187			ranges = <0x0 0x72000 0x2000>;
188			local-mac-address = [ 00 00 00 00 00 00 ];
189			interrupts = <12 13 14 11 46>;
190			interrupt-parent = <&PIC>;
191			phy-handle = <&phy0>;
192
193			mdio@0 {
194				#address-cells = <1>;
195				#size-cells = <0>;
196				compatible = "mrvl,mdio";
197
198				phy0: ethernet-phy@0 {
199					reg = <0x8>;
200				};
201			};
202		};
203
204		serial0: serial@12000 {
205			compatible = "ns16550";
206			reg = <0x12000 0x20>;
207			reg-shift = <2>;
208			clock-frequency = <0>;
209			interrupts = <33>;
210			interrupt-parent = <&PIC>;
211		};
212
213		serial1: serial@12100 {
214			compatible = "ns16550";
215			reg = <0x12100 0x20>;
216			reg-shift = <2>;
217			clock-frequency = <0>;
218			interrupts = <34>;
219			interrupt-parent = <&PIC>;
220		};
221
222		crypto@30000 {
223			compatible = "mrvl,cesa";
224			reg = <0x30000 0x1000	/* tdma base reg chan 0 */
225			       0x3D000 0x1000>;	/* cesa base reg chan 0 */
226			interrupts = <22>;
227			interrupt-parent = <&PIC>;
228
229			sram-handle = <&SRAM>;
230		};
231
232		usb@50000 {
233			compatible = "mrvl,usb-ehci", "usb-ehci";
234			reg = <0x50000 0x1000>;
235			interrupts = <48 19>;
236			interrupt-parent = <&PIC>;
237		};
238
239		xor@60000 {
240			compatible = "mrvl,xor";
241			reg = <0x60000 0x1000>;
242			interrupts = <5 6 7 8>;
243			interrupt-parent = <&PIC>;
244		};
245
246		sata@80000 {
247			compatible = "mrvl,sata";
248			reg = <0x80000 0x6000>;
249			interrupts = <21>;
250			interrupt-parent = <&PIC>;
251		};
252	};
253
254	SRAM: sram@fd000000 {
255		compatible = "mrvl,cesa-sram";
256		reg = <0xfd000000 0x00100000>;
257	};
258
259	pci0: pcie@f1040000 {
260		compatible = "mrvl,pcie";
261		device_type = "pci";
262		#interrupt-cells = <1>;
263		#size-cells = <2>;
264		#address-cells = <3>;
265		reg = <0xf1040000 0x2000>;
266		bus-range = <0 255>;
267		ranges = <0x02000000 0x0 0xf1300000 0xf1300000 0x0 0x04000000
268			  0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
269		clock-frequency = <33333333>;
270		interrupt-parent = <&PIC>;
271		interrupts = <44>;
272		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
273		interrupt-map = <
274			/* IDSEL 0x1 */
275			0x0800 0x0 0x0 0x1 &PIC 0x9
276			0x0800 0x0 0x0 0x2 &PIC 0x9
277			0x0800 0x0 0x0 0x3 &PIC 0x9
278			0x0800 0x0 0x0 0x4 &PIC 0x9
279			>;
280		pcie@0 {
281			reg = <0x0 0x0 0x0 0x0 0x0>;
282			#size-cells = <2>;
283			#address-cells = <3>;
284			device_type = "pci";
285			ranges = <0x02000000 0x0 0xf1300000
286				  0x02000000 0x0 0xf1300000
287				  0x0 0x04000000
288
289				  0x01000000 0x0 0x0
290				  0x01000000 0x0 0x0
291				  0x0 0x00100000>;
292		};
293	};
294
295      	chosen {
296		stdin = "serial0";
297		stdout = "serial0";
298	};
299};
300