db78100.dts revision 262614 
1/*
2 * Copyright (c) 2010 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Semihalf under sponsorship from
6 * the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * Marvell DB-78100 Device Tree Source.
30 *
31 * $FreeBSD: head/sys/boot/fdt/dts/arm/db78100.dts 262614 2014-02-28 18:29:09Z imp $
32 */
33
34/dts-v1/;
35
36/ {
37	model = "mrvl,DB-78100";
38	compatible = "DB-78100-BP", "DB-78100-BP-A";
39	#address-cells = <1>;
40	#size-cells = <1>;
41
42	aliases {
43		ethernet0 = &enet0;
44		serial0 = &serial0;
45		serial1 = &serial1;
46		mpp = &MPP;
47	};
48
49	cpus {
50		#address-cells = <1>;
51		#size-cells = <0>;
52
53		cpu@0 {
54			device_type = "cpu";
55			compatible = "ARM,88FR571";
56			reg = <0x0>;
57			d-cache-line-size = <32>;	// 32 bytes
58			i-cache-line-size = <32>;	// 32 bytes
59			d-cache-size = <0x4000>;	// L1, 16K
60			i-cache-size = <0x4000>;	// L1, 16K
61			timebase-frequency = <0>;
62			bus-frequency = <0>;
63			clock-frequency = <0>;
64		};
65	};
66
67	memory {
68		device_type = "memory";
69		reg = <0x0 0x20000000>;		// 512M at 0x0
70	};
71
72	localbus@0 {
73		#address-cells = <2>;
74		#size-cells = <1>;
75		compatible = "mrvl,lbc";
76		bank-count = <5>;
77
78		/* This reflects CPU decode windows setup. */
79		ranges = <0x0 0x2f 0xf9300000 0x00100000
80			  0x1 0x3e 0xf9400000 0x00100000
81			  0x2 0x3d 0xf9500000 0x02000000
82			  0x3 0x3b 0xfb500000 0x00100000>;
83
84		nor@0,0 {
85			#address-cells = <1>;
86			#size-cells = <1>;
87			compatible = "cfi-flash";
88			reg = <0x0 0x0 0x00100000>;
89		};
90
91		led@1,0 {
92			#address-cells = <1>;
93			#size-cells = <1>;
94			compatible = "led";
95			reg = <0x1 0x0 0x00100000>;
96		};
97
98		nor@2,0 {
99			#address-cells = <1>;
100			#size-cells = <1>;
101			compatible = "cfi-flash";
102			reg = <0x2 0x0 0x02000000>;
103		};
104
105		nand@3,0 {
106			#address-cells = <1>;
107			#size-cells = <1>;
108			compatible = "mrvl,nfc";
109			reg = <0x3 0x0 0x00100000>;
110		};
111	};
112
113	soc78100@f1000000 {
114		#address-cells = <1>;
115		#size-cells = <1>;
116		compatible = "simple-bus";
117		ranges = <0x0 0xf1000000 0x00100000>;
118		bus-frequency = <0>;
119
120		PIC: pic@20200 {
121			interrupt-controller;
122			#address-cells = <0>;
123			#interrupt-cells = <1>;
124			reg = <0x20200 0x3c>;
125			compatible = "mrvl,pic";
126		};
127
128		timer@20300 {
129			compatible = "mrvl,timer";
130			reg = <0x20300 0x30>;
131			interrupts = <8>;
132			interrupt-parent = <&PIC>;
133			mrvl,has-wdt;
134		};
135
136		MPP: mpp@10000 {
137			#pin-cells = <2>;
138			compatible = "mrvl,mpp";
139			reg = <0x10000 0x34>;
140			pin-count = <50>;
141			pin-map = <
142				0  2		/* MPP[0]:  GE1_TXCLK */
143				1  2		/* MPP[1]:  GE1_TXCTL */
144				2  2		/* MPP[2]:  GE1_RXCTL */
145				3  2		/* MPP[3]:  GE1_RXCLK */
146				4  2		/* MPP[4]:  GE1_TXD[0] */
147				5  2		/* MPP[5]:  GE1_TXD[1] */
148				6  2		/* MPP[6]:  GE1_TXD[2] */
149				7  2		/* MPP[7]:  GE1_TXD[3] */
150				8  2		/* MPP[8]:  GE1_RXD[0] */
151				9  2		/* MPP[9]:  GE1_RXD[1] */
152				10 2		/* MPP[10]: GE1_RXD[2] */
153				11 2		/* MPP[11]: GE1_RXD[3] */
154				13 3		/* MPP[13]: SYSRST_OUTn */
155				14 3		/* MPP[14]: SATA1_ACTn */
156				15 3		/* MPP[15]: SATA0_ACTn */
157				16 4		/* MPP[16]: UA2_TXD */
158				17 4		/* MPP[17]: UA2_RXD */
159				18 3		/* MPP[18]: <UNKNOWN> */
160				19 3		/* MPP[19]: <UNKNOWN> */
161				20 3		/* MPP[20]: <UNKNOWN> */
162				21 3		/* MPP[21]: <UNKNOWN> */
163				22 4		/* MPP[22]: UA3_TXD */
164				23 4 >;		/* MPP[21]: UA3_RXD */
165		};
166
167		GPIO: gpio@10100 {
168			#gpio-cells = <3>;
169			compatible = "mrvl,gpio";
170			reg = <0x10100 0x20>;
171			gpio-controller;
172			interrupts = <56 57 58 59>;
173			interrupt-parent = <&PIC>;
174		};
175
176		rtc@10300 {
177			compatible = "mrvl,rtc";
178			reg = <0x10300 0x08>;
179		};
180
181		twsi@11000 {
182			#address-cells = <1>;
183			#size-cells = <0>;
184			compatible = "mrvl,twsi";
185			reg = <0x11000 0x20>;
186			interrupts = <2>;
187			interrupt-parent = <&PIC>;
188		};
189
190		twsi@11100 {
191			#address-cells = <1>;
192			#size-cells = <0>;
193			compatible = "mrvl,twsi";
194			reg = <0x11100 0x20>;
195			interrupts = <3>;
196			interrupt-parent = <&PIC>;
197		};
198
199		enet0: ethernet@72000 {
200			#address-cells = <1>;
201			#size-cells = <1>;
202			model = "V2";
203			compatible = "mrvl,ge";
204			reg = <0x72000 0x2000>;
205			ranges = <0x0 0x72000 0x2000>;
206			local-mac-address = [ 00 00 00 00 00 00 ];
207			interrupts = <41 42 43 40 70>;
208			interrupt-parent = <&PIC>;
209			phy-handle = <&phy0>;
210
211			mdio@0 {
212				#address-cells = <1>;
213				#size-cells = <0>;
214				compatible = "mrvl,mdio";
215
216				phy0: ethernet-phy@0 {
217					reg = <0x8>;
218				};
219				phy1: ethernet-phy@1 {
220					reg = <0x9>;
221				};
222			};
223		};
224
225		enet1: ethernet@76000 {
226			#address-cells = <1>;
227			#size-cells = <1>;
228			model = "V2";
229			compatible = "mrvl,ge";
230			reg = <0x76000 0x2000>;
231			ranges = <0x0 0x76000 0x2000>;
232			local-mac-address = [ 00 00 00 00 00 00 ];
233			interrupts = <45 46 47 44 70>;
234			interrupt-parent = <&PIC>;
235			phy-handle = <&phy1>;
236		};
237
238		serial0: serial@12000 {
239			compatible = "ns16550";
240			reg = <0x12000 0x20>;
241			reg-shift = <2>;
242			clock-frequency = <0>;
243			interrupts = <12>;
244			interrupt-parent = <&PIC>;
245		};
246
247		serial1: serial@12100 {
248			compatible = "ns16550";
249			reg = <0x12100 0x20>;
250			reg-shift = <2>;
251			clock-frequency = <0>;
252			interrupts = <13>;
253			interrupt-parent = <&PIC>;
254		};
255
256		usb@50000 {
257			compatible = "mrvl,usb-ehci", "usb-ehci";
258			reg = <0x50000 0x1000>;
259			interrupts = <72 16>;
260			interrupt-parent = <&PIC>;
261		};
262
263		usb@51000 {
264			compatible = "mrvl,usb-ehci", "usb-ehci";
265			reg = <0x51000 0x1000>;
266			interrupts = <72 17>;
267			interrupt-parent = <&PIC>;
268		};
269
270		usb@52000 {
271			compatible = "mrvl,usb-ehci", "usb-ehci";
272			reg = <0x52000 0x1000>;
273			interrupts = <72 18>;
274			interrupt-parent = <&PIC>;
275		};
276
277		xor@60000 {
278			compatible = "mrvl,xor";
279			reg = <0x60000 0x1000>;
280			interrupts = <22 23>;
281			interrupt-parent = <&PIC>;
282		};
283
284		crypto@90000 {
285			compatible = "mrvl,cesa";
286			reg = <0x90000 0x10000>;
287			interrupts = <19>;
288			interrupt-parent = <&PIC>;
289		};
290
291		sata@a0000 {
292			compatible = "mrvl,sata";
293			reg = <0xa0000 0x6000>;
294			interrupts = <26>;
295			interrupt-parent = <&PIC>;
296		};
297	};
298
299	pci0: pcie@f1040000 {
300		compatible = "mrvl,pcie";
301		device_type = "pci";
302		#interrupt-cells = <1>;
303		#size-cells = <2>;
304		#address-cells = <3>;
305		reg = <0xf1040000 0x2000>;
306		bus-range = <0 255>;
307		ranges = <0x02000000 0x0 0xf2000000 0xf2000000 0x0 0x04000000
308			  0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
309		clock-frequency = <33333333>;
310		interrupt-parent = <&PIC>;
311		interrupts = <68>;
312		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
313		interrupt-map = <
314			/* IDSEL 0x1 */
315			0x0800 0x0 0x0 0x1 &PIC 0x20
316			0x0800 0x0 0x0 0x2 &PIC 0x21
317			0x0800 0x0 0x0 0x3 &PIC 0x22
318			0x0800 0x0 0x0 0x4 &PIC 0x23
319			>;
320	};
321
322	sram@fd000000 {
323		compatible = "mrvl,cesa-sram";
324		reg = <0xfd000000 0x00100000>;
325	};
326
327	chosen {
328		stdin = "serial0";
329		stdout = "serial0";
330	};
331};
332