1294416Szbb/* 2294416Szbb * Device Tree Include file for Marvell Armada 380 SoC. 3294416Szbb * 4294416Szbb * Copyright (C) 2014 Marvell 5294416Szbb * 6294416Szbb * Lior Amsalem <alior@marvell.com> 7294416Szbb * Gregory CLEMENT <gregory.clement@free-electrons.com> 8294416Szbb * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9294416Szbb * 10294416Szbb * This file is dual-licensed: you can use it either under the terms 11294416Szbb * of the GPL or the X11 license, at your option. Note that this dual 12294416Szbb * licensing only applies to this file, and not this project as a 13294416Szbb * whole. 14294416Szbb * 15294416Szbb * a) This file is free software; you can redistribute it and/or 16294416Szbb * modify it under the terms of the GNU General Public License as 17294416Szbb * published by the Free Software Foundation; either version 2 of the 18294416Szbb * License, or (at your option) any later version. 19294416Szbb * 20294416Szbb * This file is distributed in the hope that it will be useful 21294416Szbb * but WITHOUT ANY WARRANTY; without even the implied warranty of 22294416Szbb * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23294416Szbb * GNU General Public License for more details. 24294416Szbb * 25294416Szbb * Or, alternatively 26294416Szbb * 27294416Szbb * b) Permission is hereby granted, free of charge, to any person 28294416Szbb * obtaining a copy of this software and associated documentation 29294416Szbb * files (the "Software"), to deal in the Software without 30294416Szbb * restriction, including without limitation the rights to use 31294416Szbb * copy, modify, merge, publish, distribute, sublicense, and/or 32294416Szbb * sell copies of the Software, and to permit persons to whom the 33294416Szbb * Software is furnished to do so, subject to the following 34294416Szbb * conditions: 35294416Szbb * 36294416Szbb * The above copyright notice and this permission notice shall be 37294416Szbb * included in all copies or substantial portions of the Software. 38294416Szbb * 39294416Szbb * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 40294416Szbb * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41294416Szbb * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42294416Szbb * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43294416Szbb * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44294416Szbb * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45294416Szbb * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46294416Szbb * OTHER DEALINGS IN THE SOFTWARE. 47294416Szbb * 48294416Szbb * $FreeBSD: releng/11.0/sys/boot/fdt/dts/arm/armada-380.dtsi 294416 2016-01-20 13:14:36Z zbb $ 49294416Szbb */ 50294416Szbb 51294416Szbb#include "armada-38x.dtsi" 52294416Szbb 53294416Szbb/ { 54294416Szbb model = "Marvell Armada 380 family SoC"; 55294416Szbb compatible = "marvell,armada380"; 56294416Szbb 57294416Szbb cpus { 58294416Szbb #address-cells = <1>; 59294416Szbb #size-cells = <0>; 60294416Szbb enable-method = "marvell,armada-380-smp"; 61294416Szbb 62294416Szbb cpu@0 { 63294416Szbb device_type = "cpu"; 64294416Szbb compatible = "arm,cortex-a9"; 65294416Szbb reg = <0>; 66294416Szbb }; 67294416Szbb }; 68294416Szbb 69294416Szbb soc { 70294416Szbb internal-regs { 71294416Szbb pinctrl@18000 { 72294416Szbb compatible = "marvell,mv88f6810-pinctrl"; 73294416Szbb }; 74294416Szbb }; 75294416Szbb 76294416Szbb pcie-controller { 77294416Szbb compatible = "marvell,armada-370-pcie"; 78294416Szbb status = "disabled"; 79294416Szbb device_type = "pci"; 80294416Szbb 81294416Szbb #address-cells = <3>; 82294416Szbb #size-cells = <2>; 83294416Szbb 84294416Szbb msi-parent = <&mpic>; 85294416Szbb bus-range = <0x00 0xff>; 86294416Szbb 87294416Szbb ranges = 88294416Szbb <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 89294416Szbb 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 90294416Szbb 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 91294416Szbb 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 92294416Szbb 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 93294416Szbb 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ 94294416Szbb 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ 95294416Szbb 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ 96294416Szbb 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ 97294416Szbb 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; 98294416Szbb 99294416Szbb /* x1 port */ 100294416Szbb pcie@1,0 { 101294416Szbb device_type = "pci"; 102294416Szbb assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 103294416Szbb reg = <0x0800 0 0 0 0>; 104294416Szbb #address-cells = <3>; 105294416Szbb #size-cells = <2>; 106294416Szbb #interrupt-cells = <1>; 107294416Szbb ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 108294416Szbb 0x81000000 0 0 0x81000000 0x1 0 1 0>; 109294416Szbb interrupt-map-mask = <0 0 0 0>; 110294416Szbb interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 111294416Szbb marvell,pcie-port = <0>; 112294416Szbb marvell,pcie-lane = <0>; 113294416Szbb clocks = <&gateclk 8>; 114294416Szbb status = "disabled"; 115294416Szbb }; 116294416Szbb 117294416Szbb /* x1 port */ 118294416Szbb pcie@2,0 { 119294416Szbb device_type = "pci"; 120294416Szbb assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 121294416Szbb reg = <0x1000 0 0 0 0>; 122294416Szbb #address-cells = <3>; 123294416Szbb #size-cells = <2>; 124294416Szbb #interrupt-cells = <1>; 125294416Szbb ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 126294416Szbb 0x81000000 0 0 0x81000000 0x2 0 1 0>; 127294416Szbb interrupt-map-mask = <0 0 0 0>; 128294416Szbb interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 129294416Szbb marvell,pcie-port = <1>; 130294416Szbb marvell,pcie-lane = <0>; 131294416Szbb clocks = <&gateclk 5>; 132294416Szbb status = "disabled"; 133294416Szbb }; 134294416Szbb 135294416Szbb /* x1 port */ 136294416Szbb pcie@3,0 { 137294416Szbb device_type = "pci"; 138294416Szbb assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 139294416Szbb reg = <0x1800 0 0 0 0>; 140294416Szbb #address-cells = <3>; 141294416Szbb #size-cells = <2>; 142294416Szbb #interrupt-cells = <1>; 143294416Szbb ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 144294416Szbb 0x81000000 0 0 0x81000000 0x3 0 1 0>; 145294416Szbb interrupt-map-mask = <0 0 0 0>; 146294416Szbb interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 147294416Szbb marvell,pcie-port = <2>; 148294416Szbb marvell,pcie-lane = <0>; 149294416Szbb clocks = <&gateclk 6>; 150294416Szbb status = "disabled"; 151294416Szbb }; 152294416Szbb }; 153294416Szbb }; 154294416Szbb}; 155