1282985Szbb/*- 2282985Szbb * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com> 3282985Szbb * Copyright (c) 2015 Semihalf 4282985Szbb * All rights reserved. 5282985Szbb * 6282985Szbb * Redistribution and use in source and binary forms, with or without 7282985Szbb * modification, are permitted provided that the following conditions 8282985Szbb * are met: 9282985Szbb * 1. Redistributions of source code must retain the above copyright 10282985Szbb * notice, this list of conditions and the following disclaimer. 11282985Szbb * 2. Redistributions in binary form must reproduce the above copyright 12282985Szbb * notice, this list of conditions and the following disclaimer in the 13282985Szbb * documentation and/or other materials provided with the distribution. 14282985Szbb * 15282985Szbb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16282985Szbb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17282985Szbb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18282985Szbb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19282985Szbb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20282985Szbb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21282985Szbb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22282985Szbb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23282985Szbb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24282985Szbb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25282985Szbb * SUCH DAMAGE. 26282985Szbb * 27282985Szbb * $FreeBSD: releng/11.0/sys/boot/fdt/dts/arm/annapurna-alpine.dts 282985 2015-05-15 18:25:48Z zbb $ 28282985Szbb */ 29282985Szbb 30282985Szbb/dts-v1/; 31282985Szbb 32282985Szbb/ { 33282985Szbb model = "annapurna,alpine"; 34282985Szbb #address-cells = <1>; 35282985Szbb #size-cells = <1>; 36282985Szbb 37282985Szbb aliases { 38282985Szbb serial0 = &serial0; 39282985Szbb }; 40282985Szbb 41282985Szbb cpus { 42282985Szbb #address-cells = <1>; 43282985Szbb #size-cells = <0>; 44282985Szbb 45282985Szbb cpu@0 { 46282985Szbb device_type = "cpu"; 47282985Szbb compatible = "arm,cortex-a15"; 48282985Szbb reg = <0x0>; 49282985Szbb d-cache-line-size = <64>; // 64 bytes 50282985Szbb i-cache-line-size = <64>; // 64 bytes 51282985Szbb d-cache-size = <0x8000>; // L1, 32K 52282985Szbb i-cache-size = <0x8000>; // L1, 32K 53282985Szbb timebase-frequency = <0>; 54282985Szbb bus-frequency = <375000000>; 55282985Szbb clock-frequency = <0>; 56282985Szbb }; 57282985Szbb 58282985Szbb cpu@1 { 59282985Szbb device_type = "cpu"; 60282985Szbb compatible = "arm,cortex-a15"; 61282985Szbb reg = <0x0>; 62282985Szbb d-cache-line-size = <64>; // 64 bytes 63282985Szbb i-cache-line-size = <64>; // 64 bytes 64282985Szbb d-cache-size = <0x8000>; // L1, 32K 65282985Szbb i-cache-size = <0x8000>; // L1, 32K 66282985Szbb timebase-frequency = <0>; 67282985Szbb bus-frequency = <375000000>; 68282985Szbb clock-frequency = <0>; 69282985Szbb }; 70282985Szbb 71282985Szbb cpu@2 { 72282985Szbb device_type = "cpu"; 73282985Szbb compatible = "arm,cortex-a15"; 74282985Szbb reg = <0x0>; 75282985Szbb d-cache-line-size = <64>; // 64 bytes 76282985Szbb i-cache-line-size = <64>; // 64 bytes 77282985Szbb d-cache-size = <0x8000>; // L1, 32K 78282985Szbb i-cache-size = <0x8000>; // L1, 32K 79282985Szbb timebase-frequency = <0>; 80282985Szbb bus-frequency = <375000000>; 81282985Szbb clock-frequency = <0>; 82282985Szbb }; 83282985Szbb 84282985Szbb cpu@3 { 85282985Szbb device_type = "cpu"; 86282985Szbb compatible = "arm,cortex-a15"; 87282985Szbb reg = <0x0>; 88282985Szbb d-cache-line-size = <64>; // 64 bytes 89282985Szbb i-cache-line-size = <64>; // 64 bytes 90282985Szbb d-cache-size = <0x8000>; // L1, 32K 91282985Szbb i-cache-size = <0x8000>; // L1, 32K 92282985Szbb timebase-frequency = <0>; 93282985Szbb bus-frequency = <375000000>; 94282985Szbb clock-frequency = <0>; 95282985Szbb }; 96282985Szbb }; 97282985Szbb 98282985Szbb memory { 99282985Szbb device_type = "memory"; 100282985Szbb reg = <0x00100000 0x7ff00000>; // 2047MB at 1MB 101282985Szbb }; 102282985Szbb 103282985Szbb soc { 104282985Szbb #address-cells = <1>; 105282985Szbb #size-cells = <1>; 106282985Szbb compatible = "simple-bus"; 107282985Szbb ranges = <0x0 0xfb000000 0x03000000>; 108282985Szbb bus-frequency = <0>; 109282985Szbb 110282985Szbb MPIC: interrupt-controller { 111282985Szbb compatible = "arm,gic"; 112282985Szbb reg = < 0x1000 0x1000 >, /* Distributor Registers */ 113282985Szbb < 0x2000 0x2000 >; /* CPU Interface Registers */ 114282985Szbb interrupt-controller; 115282985Szbb #address-cells = <0>; 116282985Szbb #interrupt-cells = <3>; 117282985Szbb 118282985Szbb // In intr[2], bits[3:0] are trigger type and level flags. 119282985Szbb // 1 = low-to-high edge triggered 120282985Szbb // 2 = high-to-low edge triggered 121282985Szbb // 4 = active high level-sensitive 122282985Szbb // 8 = active low level-sensitive 123282985Szbb // The hardware only supports active-high-level or rising-edge. 124282985Szbb 125282985Szbb }; 126282985Szbb 127282985Szbb generic_timer { 128282985Szbb compatible = "arm,sp804"; 129282985Szbb reg = <0x02890000 0x1000>; 130282985Szbb interrupts = <0 9 4>; 131282985Szbb interrupt-parent = <&MPIC>; 132282985Szbb clock-frequency = <375000000>; 133282985Szbb }; 134282985Szbb 135282985Szbb cpu_resume { 136282985Szbb compatible = "annapurna-labs,al-cpu-resume"; 137282985Szbb reg = <0x00ff5ec0 0x30>; 138282985Szbb }; 139282985Szbb 140282985Szbb nb_service { 141282985Szbb compatible = "annapurna-labs,al-nb-service"; 142282985Szbb reg = <0x00070000 0x10000>; 143282985Szbb interrupts = <0 32 4>, 144282985Szbb <0 33 4>, 145282985Szbb <0 34 4>, 146282985Szbb <0 35 4>; 147282985Szbb interrupt-parent = <&MPIC>; 148282985Szbb }; 149282985Szbb 150282985Szbb wdt0 { 151282985Szbb compatible = "arm,sp805", "arm,primecell"; 152282985Szbb reg = <0x288c000 0x1000>; 153282985Szbb interrupt-parent = <&MPIC>; 154282985Szbb }; 155282985Szbb 156282985Szbb serial0: serial@2883000 { 157282985Szbb compatible = "ns16550"; 158282985Szbb reg = <0x2883000 0x20>; 159282985Szbb reg-shift = <2>; 160282985Szbb current-speed = <115200>; 161282985Szbb clock-frequency = <375000000>; 162282985Szbb interrupts = <0 17 4>; 163282985Szbb interrupt-parent = <&MPIC>; 164282985Szbb }; 165282985Szbb }; 166282985Szbb 167282985Szbb pcie-internal { 168282985Szbb compatible = "annapurna-labs,al-internal-pcie"; 169282985Szbb device_type = "pci"; 170282985Szbb #size-cells = <2>; 171282985Szbb #address-cells = <3>; 172282985Szbb interrupt-parent = <&MPIC>; 173282985Szbb interrupt-map-mask = <0xf800 0 0 7>; 174282985Szbb interrupt-map = <0x3000 0 0 1 &MPIC 0 32 4>, // USB adapter 175282985Szbb <0x3800 0 0 1 &MPIC 0 36 4>, 176282985Szbb <0x4000 0 0 1 &MPIC 0 43 4>, // SATA 0 (PCIe expander) 177282985Szbb <0x4800 0 0 1 &MPIC 0 44 1>; // SATA 1 (onboard) 178282985Szbb 179282985Szbb // ranges: 180282985Szbb // - ECAM - non prefetchable config space 181282985Szbb // - 32 bit non prefetchable memory space 182282985Szbb ranges = <0x00000000 0x0 0xfbc00000 0xfbc00000 0x0 0x100000 183282985Szbb 0x02000000 0x0 0xfe000000 0xfe000000 0x0 0x1000000>; 184282985Szbb 185282985Szbb bus-range = <0x00 0x00>; 186282985Szbb }; 187282985Szbb 188282985Szbb// WORKAROUND: enabling PCIe controller when no card is plugged in 189282985Szbb// leads to kernel panic because u-boot disables PCIe controller if no link 190282985Szbb// is detected. Just be kind and compatible with Linux 191282985Szbb/* // External PCIe Controller 0 192282985Szbb pcie-external0 { 193282985Szbb compatible = "annapurna-labs,al-external-pcie"; 194282985Szbb reg = <0xfd800000 0x00020000>; 195282985Szbb device_type = "pci"; 196282985Szbb #size-cells = <2>; 197282985Szbb #address-cells = <3>; 198282985Szbb interrupt-parent = <&MPIC>; 199282985Szbb interrupt-map-mask = <0x00 0 0 7>; 200282985Szbb interrupt-map = <0x0000 0 0 1 &MPIC 0 40 4>; 201282985Szbb 202282985Szbb // ranges: 203282985Szbb // Controller 0: 204282985Szbb // - ECAM - non prefetchable config space: 2MB 205282985Szbb // - IO - IO port space 64KB, reserve 64KB from target memory windows 206282985Szbb // real IO address on the pci bus starts at 0x10000 207282985Szbb // - 32 bit non prefetchable memory space: 128MB - 64KB 208282985Szbb 209282985Szbb ranges = <0x00000000 0x0 0xfb600000 0xfb600000 0x0 0x00200000 210282985Szbb 0x01000000 0x0 0x00010000 0xe0000000 0x0 0x00010000 211282985Szbb 0x02000000 0x0 0xe1000000 0xe1000000 0x0 0x06f00000>; 212282985Szbb 213282985Szbb bus-range = <0x00 0xff>; 214282985Szbb }; 215282985Szbb 216282985Szbb // External PCIe Controllers 1 217282985Szbb pcie-external1 { 218282985Szbb compatible = "annapurna-labs,al-external-pcie"; 219282985Szbb reg = <0xfd820000 0x00020000>; 220282985Szbb device_type = "pci"; 221282985Szbb #size-cells = <2>; 222282985Szbb #address-cells = <3>; 223282985Szbb interrupt-parent = <&MPIC>; 224282985Szbb interrupt-map-mask = <0x0 0 0 7>; 225282985Szbb interrupt-map = <0x0000 0 0 1 &MPIC 0 41 4>; 226282985Szbb 227282985Szbb // ranges: 228282985Szbb // - ECAM - non prefetchable config space: 2MB 229282985Szbb // - IO - IO port space 64KB, reserve 64KB from target memory windows 230282985Szbb // real IO address on the pci bus starts at 0x20000 231282985Szbb // - 32 bit non prefetchable memory space: 64MB - 64KB 232282985Szbb ranges = <0x00000000 0x0 0xfb800000 0xfb800000 0x0 0x00200000 233282985Szbb 0x01000000 0x0 0x00020000 0xe8000000 0x0 0x00010000 234282985Szbb 0x02000000 0x0 0xe8100000 0xe8100000 0x0 0x02ff0000>; 235282985Szbb 236282985Szbb bus-range = <0x00 0xff>; 237282985Szbb }; */ 238282985Szbb 239282985Szbb chosen { 240282985Szbb stdin = "serial0"; 241282985Szbb stdout = "serial0"; 242282985Szbb stddbg = "serial0"; 243282985Szbb }; 244282985Szbb}; 245