cpu.h revision 286919
1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2014 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz. 8 * 9 * Portions of this software were developed by Andrew Turner 10 * under sponsorship from the FreeBSD Foundation 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)cpu.h 5.4 (Berkeley) 5/9/91 37 * from: FreeBSD: src/sys/i386/include/cpu.h,v 1.62 2001/06/29 38 * $FreeBSD: head/sys/arm64/include/cpu.h 286919 2015-08-19 10:36:36Z zbb $ 39 */ 40 41#ifndef _MACHINE_CPU_H_ 42#define _MACHINE_CPU_H_ 43 44#include <machine/atomic.h> 45#include <machine/frame.h> 46#include <machine/armreg.h> 47 48#define TRAPF_PC(tfp) ((tfp)->tf_lr) 49#define TRAPF_USERMODE(tfp) (((tfp)->tf_elr & (1ul << 63)) == 0) 50 51#define cpu_getstack(td) ((td)->td_frame->tf_sp) 52#define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp)) 53#define cpu_spinwait() /* nothing */ 54 55/* Extract CPU affinity levels 0-3 */ 56#define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff) 57#define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff) 58#define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff) 59#define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff) 60#define CPU_AFF0_MASK 0xffUL 61#define CPU_AFF1_MASK 0xff00UL 62#define CPU_AFF2_MASK 0xff0000UL 63#define CPU_AFF3_MASK 0xff00000000UL 64#define CPU_AFF_MASK (CPU_AFF0_MASK | CPU_AFF1_MASK | \ 65 CPU_AFF2_MASK| CPU_AFF3_MASK) /* Mask affinity fields in MPIDR_EL1 */ 66 67#ifdef _KERNEL 68 69#define CPU_IMPL_ARM 0x41 70#define CPU_IMPL_BROADCOM 0x42 71#define CPU_IMPL_CAVIUM 0x43 72#define CPU_IMPL_DEC 0x44 73#define CPU_IMPL_INFINEON 0x49 74#define CPU_IMPL_FREESCALE 0x4D 75#define CPU_IMPL_NVIDIA 0x4E 76#define CPU_IMPL_APM 0x50 77#define CPU_IMPL_QUALCOMM 0x51 78#define CPU_IMPL_MARVELL 0x56 79#define CPU_IMPL_INTEL 0x69 80 81#define CPU_PART_THUNDER 0x0A1 82#define CPU_PART_FOUNDATION 0xD00 83#define CPU_PART_CORTEX_A53 0xD03 84#define CPU_PART_CORTEX_A57 0xD07 85 86#define CPU_REV_THUNDER_1_0 0x00 87#define CPU_REV_THUNDER_1_1 0x01 88 89#define CPU_IMPL(midr) (((midr) >> 24) & 0xff) 90#define CPU_PART(midr) (((midr) >> 4) & 0xfff) 91#define CPU_VAR(midr) (((midr) >> 20) & 0xf) 92#define CPU_REV(midr) (((midr) >> 0) & 0xf) 93 94#define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24) 95#define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4) 96#define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20) 97#define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0) 98 99#define CPU_IMPL_MASK (0xff << 24) 100#define CPU_PART_MASK (0xfff << 4) 101#define CPU_VAR_MASK (0xf << 20) 102#define CPU_REV_MASK (0xf << 0) 103 104#define CPU_ID_RAW(impl, part, var, rev) \ 105 (CPU_IMPL_TO_MIDR((impl)) | \ 106 CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \ 107 CPU_REV_TO_MIDR((rev))) 108 109#define CPU_MATCH(mask, impl, part, var, rev) \ 110 (((mask) & PCPU_GET(midr)) == \ 111 ((mask) & CPU_ID_RAW((impl), (part), (var), (rev)))) 112 113#define CPU_MATCH_RAW(mask, devid) \ 114 (((mask) & PCPU_GET(midr)) == ((mask) & (devid))) 115 116/* 117 * Chip-specific errata. This defines are intended to be 118 * booleans used within if statements. When an appropriate 119 * kernel option is disabled, these defines must be defined 120 * as 0 to allow the compiler to remove a dead code thus 121 * produce better optimized kernel image. 122 */ 123/* 124 * Vendor: Cavium 125 * Chip: ThunderX 126 * Revision(s): Pass 1.0, Pass 1.1 127 */ 128#ifdef THUNDERX_PASS_1_1_ERRATA 129#define CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1 \ 130 (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 131 CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, CPU_REV_THUNDER_1_0) || \ 132 CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 133 CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, CPU_REV_THUNDER_1_1)) 134#else 135#define CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1 0 136#endif 137 138 139extern char btext[]; 140extern char etext[]; 141 142extern uint64_t __cpu_affinity[]; 143 144void cpu_halt(void) __dead2; 145void cpu_reset(void) __dead2; 146void fork_trampoline(void); 147void identify_cpu(void); 148void swi_vm(void *v); 149 150#define CPU_AFFINITY(cpu) __cpu_affinity[(cpu)] 151 152static __inline uint64_t 153get_cyclecount(void) 154{ 155 uint64_t ret; 156 157 ret = READ_SPECIALREG(cntvct_el0); 158 159 return (ret); 160} 161 162#define ADDRESS_TRANSLATE_FUNC(stage) \ 163static inline uint64_t \ 164arm64_address_translate_ ##stage (uint64_t addr) \ 165{ \ 166 uint64_t ret; \ 167 \ 168 __asm __volatile( \ 169 "at " __STRING(stage) ", %1 \n" \ 170 "mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \ 171 \ 172 return (ret); \ 173} 174 175ADDRESS_TRANSLATE_FUNC(s1e0r) 176ADDRESS_TRANSLATE_FUNC(s1e0w) 177ADDRESS_TRANSLATE_FUNC(s1e1r) 178ADDRESS_TRANSLATE_FUNC(s1e1w) 179 180#endif 181 182#endif /* !_MACHINE_CPU_H_ */ 183