ixp425reg.h revision 214946
1164426Ssam/* $NetBSD: ixp425reg.h,v 1.19 2005/12/11 12:16:51 christos Exp $ */ 2164426Ssam/* 3164426Ssam * Copyright (c) 2003 4164426Ssam * Ichiro FUKUHARA <ichiro@ichiro.org>. 5164426Ssam * All rights reserved. 6164426Ssam * 7164426Ssam * Redistribution and use in source and binary forms, with or without 8164426Ssam * modification, are permitted provided that the following conditions 9164426Ssam * are met: 10164426Ssam * 1. Redistributions of source code must retain the above copyright 11164426Ssam * notice, this list of conditions and the following disclaimer. 12164426Ssam * 2. Redistributions in binary form must reproduce the above copyright 13164426Ssam * notice, this list of conditions and the following disclaimer in the 14164426Ssam * documentation and/or other materials provided with the distribution. 15164426Ssam * 3. All advertising materials mentioning features or use of this software 16164426Ssam * must display the following acknowledgement: 17164426Ssam * This product includes software developed by Ichiro FUKUHARA. 18164426Ssam * 4. The name of the company nor the name of the author may be used to 19164426Ssam * endorse or promote products derived from this software without specific 20164426Ssam * prior written permission. 21164426Ssam * 22164426Ssam * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 23164426Ssam * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24164426Ssam * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25164426Ssam * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 26164426Ssam * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27164426Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28164426Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29164426Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30164426Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31164426Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32164426Ssam * SUCH DAMAGE. 33164426Ssam * 34164426Ssam * $FreeBSD: head/sys/arm/xscale/ixp425/ixp425reg.h 214946 2010-11-07 20:33:39Z thompsa $ 35164426Ssam * 36164426Ssam */ 37164426Ssam 38164426Ssam#ifndef _IXP425REG_H_ 39164426Ssam#define _IXP425REG_H_ 40164426Ssam 41164426Ssam/* 42164426Ssam * Physical memory map for the Intel IXP425 43164426Ssam */ 44164426Ssam/* 45164426Ssam * CC00 00FF --------------------------- 46164426Ssam * SDRAM Configuration Registers 47164426Ssam * CC00 0000 --------------------------- 48164426Ssam * 49164426Ssam * C800 BFFF --------------------------- 50164426Ssam * System and Peripheral Registers 51164426Ssam * C800 0000 --------------------------- 52164426Ssam * Expansion Bus Configuration Registers 53164426Ssam * C400 0000 --------------------------- 54164426Ssam * PCI Configuration and Status Registers 55164426Ssam * C000 0000 --------------------------- 56164426Ssam * 57164426Ssam * 6400 0000 --------------------------- 58164426Ssam * Queue manager 59164426Ssam * 6000 0000 --------------------------- 60164426Ssam * Expansion Bus Data 61164426Ssam * 5000 0000 --------------------------- 62164426Ssam * PCI Data 63164426Ssam * 4800 0000 --------------------------- 64164426Ssam * 65164426Ssam * 4000 0000 --------------------------- 66164426Ssam * SDRAM 67186352Ssam * 0000 0000 --------------------------- 68164426Ssam */ 69164426Ssam 70164426Ssam/* 71186352Ssam * Virtual memory map for the Intel IXP425/IXP435 integrated devices 72164426Ssam */ 73164426Ssam/* 74164426Ssam * FFFF FFFF --------------------------- 75164426Ssam * 76186352Ssam * Global cache clean area 77186352Ssam * FF00 0000 --------------------------- 78186352Ssam * 79188088Ssam * FE00 0000 --------------------------- 80188088Ssam * 16M CFI Flash (on ext bus) 81188088Ssam * FD00 0000 --------------------------- 82188088Ssam * 83164426Ssam * FC00 0000 --------------------------- 84164426Ssam * PCI Data (memory space) 85186352Ssam * F800 0000 --------------------------- IXP425_PCI_MEM_VBASE 86164426Ssam * 87164426Ssam * F020 1000 --------------------------- 88186352Ssam * SDRAM/DDR Memory Controller 89186352Ssam * F020 0000 --------------------------- IXP425_MCU_VBASE 90164426Ssam * 91194654Ssam * F001 F000 RS485 (Cambria) CAMBRIA_RS485_VBASE 92194654Ssam * F001 E000 GPS (Cambria) CAMBRIA_GPS_VBASE 93194654Ssam * F001 D000 EHCI USB 2 (IXP435) IXP435_USB2_VBASE 94194654Ssam * F001 C000 EHCI USB 1 (IXP435) IXP435_USB1_VBASE 95186352Ssam * Queue manager 96189463Ssam * F001 8000 --------------------------- IXP425_QMGR_VBASE 97186352Ssam * PCI Configuration and Status 98189463Ssam * F001 7000 --------------------------- IXP425_PCI_VBASE 99189463Ssam * 100189463Ssam * (NB: gap for future addition of EXP CS5-7) 101189463Ssam * F001 4000 Expansion Bus Chip Select 4 102189463Ssam * F001 3000 Expansion Bus Chip Select 3 103189463Ssam * F001 2000 Expansion Bus Chip Select 2 104189463Ssam * F001 1000 Expansion Bus Chip Select 1 105186352Ssam * Expansion Bus Configuration 106186352Ssam * F001 0000 --------------------------- IXP425_EXP_VBASE 107189463Ssam * 108189463Ssam * F000 C000 MAC-A (IXP435) 109186352Ssam * F000 B000 USB (option on IXP425) 110186352Ssam * F000 A000 MAC-B (IXP425) | MAC-C (IXP435) 111189463Ssam * F000 9000 MAC-A (IXP425) 112186352Ssam * F000 8000 NPE-C 113186352Ssam * F000 7000 NPE-B (IXP425) 114186352Ssam * F000 6000 NPE-A 115186352Ssam * F000 5000 Timers 116186352Ssam * F000 4000 GPIO Controller 117186352Ssam * F000 3000 Interrupt Controller 118186352Ssam * F000 2000 Performance Monitor Controller (PMC) 119186352Ssam * F000 1000 UART 1 (IXP425) 120186352Ssam * F000 0000 UART 0 121186352Ssam * F000 0000 --------------------------- IXP425_IO_VBASE 122164426Ssam * 123164426Ssam * 0000 0000 --------------------------- 124164426Ssam * 125164426Ssam */ 126164426Ssam 127164426Ssam/* Physical/Virtual address for I/O space */ 128164426Ssam 129164426Ssam#define IXP425_IO_VBASE 0xf0000000UL 130164426Ssam#define IXP425_IO_HWBASE 0xc8000000UL 131164426Ssam#define IXP425_IO_SIZE 0x00010000UL 132164426Ssam 133189463Ssam/* Physical/Virtual addresss offsets */ 134164426Ssam#define IXP425_UART0_OFFSET 0x00000000UL 135164426Ssam#define IXP425_UART1_OFFSET 0x00001000UL 136164426Ssam#define IXP425_PMC_OFFSET 0x00002000UL 137164426Ssam#define IXP425_INTR_OFFSET 0x00003000UL 138164426Ssam#define IXP425_GPIO_OFFSET 0x00004000UL 139164426Ssam#define IXP425_TIMER_OFFSET 0x00005000UL 140164426Ssam#define IXP425_NPE_A_OFFSET 0x00006000UL /* Not User Programmable */ 141164426Ssam#define IXP425_NPE_B_OFFSET 0x00007000UL /* Not User Programmable */ 142164426Ssam#define IXP425_NPE_C_OFFSET 0x00008000UL /* Not User Programmable */ 143186352Ssam#define IXP425_MAC_B_OFFSET 0x00009000UL /* Ethernet MAC on NPE-B */ 144186352Ssam#define IXP425_MAC_C_OFFSET 0x0000a000UL /* Ethernet MAC on NPE-C */ 145164426Ssam#define IXP425_USB_OFFSET 0x0000b000UL 146189463Ssam 147186352Ssam#define IXP435_MAC_A_OFFSET 0x0000c000UL /* Ethernet MAC on NPE-A */ 148164426Ssam 149164426Ssam#define IXP425_REG_SIZE 0x1000 150164426Ssam 151164426Ssam/* 152164426Ssam * UART 153164426Ssam * UART0 0xc8000000 154164426Ssam * UART1 0xc8001000 155164426Ssam * 156164426Ssam */ 157164426Ssam/* I/O space */ 158164426Ssam#define IXP425_UART0_HWBASE (IXP425_IO_HWBASE + IXP425_UART0_OFFSET) 159164426Ssam#define IXP425_UART1_HWBASE (IXP425_IO_HWBASE + IXP425_UART1_OFFSET) 160164426Ssam 161164426Ssam#define IXP425_UART0_VBASE (IXP425_IO_VBASE + IXP425_UART0_OFFSET) 162164426Ssam /* 0xf0000000 */ 163164426Ssam#define IXP425_UART1_VBASE (IXP425_IO_VBASE + IXP425_UART1_OFFSET) 164164426Ssam /* 0xf0001000 */ 165164426Ssam 166164426Ssam#define IXP425_UART_FREQ 14745600 167164426Ssam 168164426Ssam#define IXP425_UART_IER 0x01 /* interrupt enable register */ 169164426Ssam#define IXP425_UART_IER_RTOIE 0x10 /* receiver timeout interrupt enable */ 170164426Ssam#define IXP425_UART_IER_UUE 0x40 /* UART Unit enable */ 171164426Ssam 172164426Ssam/*#define IXP4XX_COM_NPORTS 8*/ 173164426Ssam 174164426Ssam/* 175164426Ssam * Timers 176164426Ssam */ 177164426Ssam#define IXP425_TIMER_HWBASE (IXP425_IO_HWBASE + IXP425_TIMER_OFFSET) 178164426Ssam#define IXP425_TIMER_VBASE (IXP425_IO_VBASE + IXP425_TIMER_OFFSET) 179164426Ssam 180164426Ssam#define IXP425_OST_TS 0x0000 181164426Ssam#define IXP425_OST_TIM0 0x0004 182164426Ssam#define IXP425_OST_TIM1 0x000C 183164426Ssam 184164426Ssam#define IXP425_OST_TIM0_RELOAD 0x0008 185164426Ssam#define IXP425_OST_TIM1_RELOAD 0x0010 186164426Ssam#define TIMERRELOAD_MASK 0xFFFFFFFC 187164426Ssam#define OST_ONESHOT_EN (1U << 1) 188164426Ssam#define OST_TIMER_EN (1U << 0) 189164426Ssam 190164426Ssam#define IXP425_OST_STATUS 0x0020 191164426Ssam#define OST_WARM_RESET (1U << 4) 192164426Ssam#define OST_WDOG_INT (1U << 3) 193164426Ssam#define OST_TS_INT (1U << 2) 194164426Ssam#define OST_TIM1_INT (1U << 1) 195164426Ssam#define OST_TIM0_INT (1U << 0) 196164426Ssam 197164426Ssam#define IXP425_OST_WDOG 0x0014 198164426Ssam#define IXP425_OST_WDOG_ENAB 0x0018 199164426Ssam#define IXP425_OST_WDOG_KEY 0x001c 200164426Ssam#define OST_WDOG_KEY_MAJICK 0x482e 201164426Ssam#define OST_WDOG_ENAB_RST_ENA (1u << 0) 202164426Ssam#define OST_WDOG_ENAB_INT_ENA (1u << 1) 203164426Ssam#define OST_WDOG_ENAB_CNT_ENA (1u << 2) 204164426Ssam 205164426Ssam/* 206164426Ssam * Interrupt Controller Unit. 207164426Ssam * PA 0xc8003000 208164426Ssam */ 209164426Ssam 210164426Ssam#define IXP425_IRQ_HWBASE IXP425_IO_HWBASE + IXP425_INTR_OFFSET 211164426Ssam#define IXP425_IRQ_VBASE IXP425_IO_VBASE + IXP425_INTR_OFFSET 212164426Ssam /* 0xf0003000 */ 213164426Ssam#define IXP425_IRQ_SIZE 0x00000020UL 214164426Ssam 215164426Ssam#define IXP425_INT_STATUS (IXP425_IRQ_VBASE + 0x00) 216164426Ssam#define IXP425_INT_ENABLE (IXP425_IRQ_VBASE + 0x04) 217164426Ssam#define IXP425_INT_SELECT (IXP425_IRQ_VBASE + 0x08) 218164426Ssam#define IXP425_IRQ_STATUS (IXP425_IRQ_VBASE + 0x0C) 219164426Ssam#define IXP425_FIQ_STATUS (IXP425_IRQ_VBASE + 0x10) 220164426Ssam#define IXP425_INT_PRTY (IXP425_IRQ_VBASE + 0x14) 221164426Ssam#define IXP425_IRQ_ENC (IXP425_IRQ_VBASE + 0x18) 222164426Ssam#define IXP425_FIQ_ENC (IXP425_IRQ_VBASE + 0x1C) 223164426Ssam 224164426Ssam#define IXP425_INT_SW1 31 /* SW Interrupt 1 */ 225164426Ssam#define IXP425_INT_SW0 30 /* SW Interrupt 0 */ 226164426Ssam#define IXP425_INT_GPIO_12 29 /* GPIO 12 */ 227164426Ssam#define IXP425_INT_GPIO_11 28 /* GPIO 11 */ 228164426Ssam#define IXP425_INT_GPIO_10 27 /* GPIO 11 */ 229164426Ssam#define IXP425_INT_GPIO_9 26 /* GPIO 9 */ 230164426Ssam#define IXP425_INT_GPIO_8 25 /* GPIO 8 */ 231164426Ssam#define IXP425_INT_GPIO_7 24 /* GPIO 7 */ 232164426Ssam#define IXP425_INT_GPIO_6 23 /* GPIO 6 */ 233164426Ssam#define IXP425_INT_GPIO_5 22 /* GPIO 5 */ 234164426Ssam#define IXP425_INT_GPIO_4 21 /* GPIO 4 */ 235164426Ssam#define IXP425_INT_GPIO_3 20 /* GPIO 3 */ 236164426Ssam#define IXP425_INT_GPIO_2 19 /* GPIO 2 */ 237164426Ssam#define IXP425_INT_XSCALE_PMU 18 /* XScale PMU */ 238164426Ssam#define IXP425_INT_AHB_PMU 17 /* AHB PMU */ 239164426Ssam#define IXP425_INT_WDOG 16 /* Watchdog Timer */ 240164426Ssam#define IXP425_INT_UART0 15 /* HighSpeed UART */ 241164426Ssam#define IXP425_INT_STAMP 14 /* Timestamp Timer */ 242164426Ssam#define IXP425_INT_UART1 13 /* Console UART */ 243164426Ssam#define IXP425_INT_USB 12 /* USB */ 244164426Ssam#define IXP425_INT_TMR1 11 /* General-Purpose Timer1 */ 245164426Ssam#define IXP425_INT_PCIDMA2 10 /* PCI DMA Channel 2 */ 246164426Ssam#define IXP425_INT_PCIDMA1 9 /* PCI DMA Channel 1 */ 247164426Ssam#define IXP425_INT_PCIINT 8 /* PCI Interrupt */ 248164426Ssam#define IXP425_INT_GPIO_1 7 /* GPIO 1 */ 249164426Ssam#define IXP425_INT_GPIO_0 6 /* GPIO 0 */ 250164426Ssam#define IXP425_INT_TMR0 5 /* General-Purpose Timer0 */ 251164426Ssam#define IXP425_INT_QUE33_64 4 /* Queue Manager 33-64 */ 252164426Ssam#define IXP425_INT_QUE1_32 3 /* Queue Manager 1-32 */ 253164426Ssam#define IXP425_INT_NPE_C 2 /* NPE C */ 254164426Ssam#define IXP425_INT_NPE_B 1 /* NPE B */ 255164426Ssam#define IXP425_INT_NPE_A 0 /* NPE A */ 256164426Ssam 257186352Ssam/* NB: IXP435 has an additional 32 IRQ's */ 258186352Ssam#define IXP435_INT_STATUS2 (IXP425_IRQ_VBASE + 0x20) 259186352Ssam#define IXP435_INT_ENABLE2 (IXP425_IRQ_VBASE + 0x24) 260186352Ssam#define IXP435_INT_SELECT2 (IXP425_IRQ_VBASE + 0x28) 261186352Ssam#define IXP435_IRQ_STATUS2 (IXP425_IRQ_VBASE + 0x2C) 262186352Ssam#define IXP435_FIQ_STATUS2 (IXP425_IRQ_VBASE + 0x30) 263186352Ssam 264186352Ssam#define IXP435_INT_USB0 32 /* USB Host 2.0 Host 0 */ 265186352Ssam#define IXP435_INT_USB1 33 /* USB Host 2.0 Host 1 */ 266186352Ssam#define IXP435_INT_QMGR_PER 60 /* Queue manager parity error */ 267186352Ssam#define IXP435_INT_ECC 61 /* Single or multi-bit ECC error */ 268186352Ssam 269164426Ssam/* 270164426Ssam * software interrupt 271164426Ssam */ 272164426Ssam#define IXP425_INT_bit31 31 273164426Ssam#define IXP425_INT_bit30 30 274164426Ssam#define IXP425_INT_bit14 14 275164426Ssam#define IXP425_INT_bit11 11 276164426Ssam 277164426Ssam#define IXP425_INT_HWMASK (0xffffffff & \ 278164426Ssam ~((1 << IXP425_INT_bit31) | \ 279164426Ssam (1 << IXP425_INT_bit30) | \ 280164426Ssam (1 << IXP425_INT_bit14) | \ 281164426Ssam (1 << IXP425_INT_bit11))) 282164426Ssam#define IXP425_INT_GPIOMASK (0x3ff800c0u) 283164426Ssam 284186352Ssam#define IXP435_INT_HWMASK ((1 << (IXP435_INT_USB0 - 32)) | \ 285186352Ssam (1 << (IXP435_INT_USB1 - 32)) | \ 286186352Ssam (1 << (IXP435_INT_QMGR_PER - 32)) | \ 287186352Ssam (1 << (IXP435_INT_ECC - 32))) 288186352Ssam 289164426Ssam/* 290164426Ssam * GPIO 291164426Ssam */ 292164426Ssam#define IXP425_GPIO_HWBASE IXP425_IO_HWBASE + IXP425_GPIO_OFFSET 293164426Ssam#define IXP425_GPIO_VBASE IXP425_IO_VBASE + IXP425_GPIO_OFFSET 294164426Ssam /* 0xf0004000 */ 295164426Ssam#define IXP425_GPIO_SIZE 0x00000020UL 296164426Ssam 297164426Ssam#define IXP425_GPIO_GPOUTR 0x00 298164426Ssam#define IXP425_GPIO_GPOER 0x04 299164426Ssam#define IXP425_GPIO_GPINR 0x08 300164426Ssam#define IXP425_GPIO_GPISR 0x0c 301164426Ssam#define IXP425_GPIO_GPIT1R 0x10 302164426Ssam#define IXP425_GPIO_GPIT2R 0x14 303164426Ssam#define IXP425_GPIO_GPCLKR 0x18 304164426Ssam# define GPCLKR_MUX14 (1U << 8) 305164426Ssam# define GPCLKR_CLK0TC_SHIFT 4 306164426Ssam# define GPCLKR_CLK0DC_SHIFT 0 307164426Ssam 308164426Ssam/* GPIO Output */ 309164426Ssam#define GPOUT_ON 0x1 310164426Ssam#define GPOUT_OFF 0x0 311164426Ssam 312164426Ssam/* GPIO direction */ 313164426Ssam#define GPOER_INPUT 0x1 314164426Ssam#define GPOER_OUTPUT 0x0 315164426Ssam 316164426Ssam/* GPIO Type bits */ 317164426Ssam#define GPIO_TYPE_ACT_HIGH 0x0 318164426Ssam#define GPIO_TYPE_ACT_LOW 0x1 319164426Ssam#define GPIO_TYPE_EDG_RISING 0x2 320164426Ssam#define GPIO_TYPE_EDG_FALLING 0x3 321164426Ssam#define GPIO_TYPE_TRANSITIONAL 0x4 322164426Ssam#define GPIO_TYPE_MASK 0x7 323164426Ssam#define GPIO_TYPE(b,v) ((v) << (((b) & 0x7) * 3)) 324164426Ssam#define GPIO_TYPE_REG(b) (((b)&8)?IXP425_GPIO_GPIT2R:IXP425_GPIO_GPIT1R) 325164426Ssam 326214946Sthompsa#define IXP4XX_GPIO_PINS 16 327214946Sthompsa 328164426Ssam/* 329164426Ssam * Expansion Bus Configuration Space. 330164426Ssam */ 331164426Ssam#define IXP425_EXP_HWBASE 0xc4000000UL 332189463Ssam#define IXP425_EXP_VBASE 0xf0010000UL 333189463Ssam#define IXP425_EXP_SIZE 0x1000 334164426Ssam 335164426Ssam/* offset */ 336164426Ssam#define EXP_TIMING_CS0_OFFSET 0x0000 337164426Ssam#define EXP_TIMING_CS1_OFFSET 0x0004 338164426Ssam#define EXP_TIMING_CS2_OFFSET 0x0008 339164426Ssam#define EXP_TIMING_CS3_OFFSET 0x000c 340164426Ssam#define EXP_TIMING_CS4_OFFSET 0x0010 341164426Ssam#define EXP_TIMING_CS5_OFFSET 0x0014 342164426Ssam#define EXP_TIMING_CS6_OFFSET 0x0018 343164426Ssam#define EXP_TIMING_CS7_OFFSET 0x001c 344164426Ssam#define EXP_CNFG0_OFFSET 0x0020 345164426Ssam#define EXP_CNFG1_OFFSET 0x0024 346164426Ssam#define EXP_FCTRL_OFFSET 0x0028 347164426Ssam 348164426Ssam#define IXP425_EXP_RECOVERY_SHIFT 16 349164426Ssam#define IXP425_EXP_HOLD_SHIFT 20 350164426Ssam#define IXP425_EXP_STROBE_SHIFT 22 351164426Ssam#define IXP425_EXP_SETUP_SHIFT 26 352164426Ssam#define IXP425_EXP_ADDR_SHIFT 28 353164426Ssam#define IXP425_EXP_CS_EN (1U << 31) 354164426Ssam 355164426Ssam#define IXP425_EXP_RECOVERY_T(x) (((x) & 15) << IXP425_EXP_RECOVERY_SHIFT) 356164426Ssam#define IXP425_EXP_HOLD_T(x) (((x) & 3) << IXP425_EXP_HOLD_SHIFT) 357164426Ssam#define IXP425_EXP_STROBE_T(x) (((x) & 15) << IXP425_EXP_STROBE_SHIFT) 358164426Ssam#define IXP425_EXP_SETUP_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT) 359164426Ssam#define IXP425_EXP_ADDR_T(x) (((x) & 3) << IXP425_EXP_ADDR_SHIFT) 360164426Ssam 361164426Ssam/* EXP_CSn bits */ 362164426Ssam#define EXP_BYTE_EN 0x00000001 /* bus uses only 8-bit data */ 363164426Ssam#define EXP_WR_EN 0x00000002 /* ena writes to CS region */ 364164426Ssam/* bit 2 is reserved */ 365164426Ssam#define EXP_SPLT_EN 0x00000008 /* ena AHB split transfers */ 366164426Ssam#define EXP_MUX_EN 0x00000010 /* multiplexed address/data */ 367164426Ssam#define EXP_HRDY_POL 0x00000020 /* HPI|HRDY polarity */ 368164426Ssam#define EXP_BYTE_RD16 0x00000040 /* byte rd access to word dev */ 369164426Ssam#define EXP_CNFG 0x00003c00 /* device config size */ 370164426Ssam#define EXP_SZ_512 (0 << 10) 371164426Ssam#define EXP_SZ_1K (1 << 10) 372164426Ssam#define EXP_SZ_2K (2 << 10) 373164426Ssam#define EXP_SZ_4K (3 << 10) 374164426Ssam#define EXP_SZ_8K (4 << 10) 375164426Ssam#define EXP_SZ_16K (5 << 10) 376164426Ssam#define EXP_SZ_32K (6 << 10) 377164426Ssam#define EXP_SZ_64K (7 << 10) 378164426Ssam#define EXP_SZ_128K (8 << 10) 379164426Ssam#define EXP_SZ_256K (9 << 10) 380164426Ssam#define EXP_SZ_512K (10 << 10) 381164426Ssam#define EXP_SZ_1M (11 << 10) 382164426Ssam#define EXP_SZ_2M (12 << 10) 383164426Ssam#define EXP_SZ_4M (13 << 10) 384164426Ssam#define EXP_SZ_8M (14 << 10) 385164426Ssam#define EXP_SZ_16M (15 << 10) 386164426Ssam#define EXP_CYC_TYPE 0x0000c000 /* bus cycle "type" */ 387164426Ssam#define EXP_CYC_INTEL (0 << 14) 388164426Ssam#define EXP_CYC_MOTO (1 << 14) 389164426Ssam#define EXP_CYC_HPI (2 << 14) 390164426Ssam#define EXP_T5 0x000f0000 /* recovery timing */ 391164426Ssam#define EXP_T4 0x00300000 /* hold timing */ 392164426Ssam#define EXP_T3 0x03c00000 /* strobe timing */ 393164426Ssam#define EXP_T2 0x0c000000 /* setup/chip select timing */ 394164426Ssam#define EXP_T1 0x30000000 /* address timing */ 395164426Ssam/* bit 30 is reserved */ 396164426Ssam#define EXP_CS_EN 0x80000000 /* chip select enabled */ 397164426Ssam 398164426Ssam/* EXP_CNFG0 bits */ 399164426Ssam#define EXP_CNFG0_8BIT (1 << 0) 400164426Ssam#define EXP_CNFG0_PCI_HOST (1 << 1) 401164426Ssam#define EXP_CNFG0_PCI_ARB (1 << 2) 402164426Ssam#define EXP_CNFG0_PCI_66MHZ (1 << 4) 403164426Ssam#define EXP_CNFG0_MEM_MAP (1 << 31) 404164426Ssam 405164426Ssam/* EXP_CNFG1 bits */ 406164426Ssam#define EXP_CNFG1_SW_INT0 (1 << 0) 407164426Ssam#define EXP_CNFG1_SW_INT1 (1 << 1) 408164426Ssam 409164426Ssam#define EXP_FCTRL_RCOMP (1<<0) 410186418Ssam#define EXP_FCTRL_USB_DEVICE (1<<1) 411164426Ssam#define EXP_FCTRL_HASH (1<<2) 412164426Ssam#define EXP_FCTRL_AES (1<<3) 413164426Ssam#define EXP_FCTRL_DES (1<<4) 414164426Ssam#define EXP_FCTRL_HDLC (1<<5) 415164426Ssam#define EXP_FCTRL_AAL (1<<6) 416164426Ssam#define EXP_FCTRL_HSS (1<<7) 417164426Ssam#define EXP_FCTRL_UTOPIA (1<<8) 418164426Ssam#define EXP_FCTRL_ETH0 (1<<9) 419164426Ssam#define EXP_FCTRL_ETH1 (1<<10) 420186418Ssam#define EXP_FCTRL_NPEA (1<<11) /* reset */ 421186418Ssam#define EXP_FCTRL_NPEB (1<<12) /* reset */ 422186418Ssam#define EXP_FCTRL_NPEC (1<<13) /* reset */ 423164426Ssam#define EXP_FCTRL_PCI (1<<14) 424186418Ssam#define EXP_FCTRL_ECC_TIMESYNC (1<<15) 425186418Ssam#define EXP_FCTRL_UTOPIA_PHY (3<<16) /* PHY limit */ 426186418Ssam#define EXP_FCTRL_USB_HOST (1<<18) 427186418Ssam#define EXP_FCTRL_NPEA_ETH (1<<19) 428186418Ssam#define EXP_FCTRL_NPEB_ETH (1<<20) 429186418Ssam#define EXP_FCTRL_RSA (1<<21) 430186418Ssam#define EXP_FCTRL_MAXFREQ (3<<22) /* XScale frequency */ 431186418Ssam#define EXP_FCTRL_RESVD (0xff<<24) 432164426Ssam 433186418Ssam#define EXP_FCTRL_IXP46X_ONLY \ 434186418Ssam (EXP_FCTRL_ECC_TIMESYNC | EXP_FCTRL_USB_HOST | EXP_FCTRL_NPEA_ETH | \ 435186418Ssam EXP_FCTRL_NPEB_ETH | EXP_FCTRL_RSA | EXP_FCTRL_MAXFREQ) 436186418Ssam 437186418Ssam#define EXP_FCTRL_BITS \ 438186418Ssam "\20\1RCOMP\2USB\3HASH\4AES\5DES\6HDLC\7AAL\10HSS\11UTOPIA\12ETH0" \ 439186418Ssam "\13ETH1\17PCI\20ECC\23USB_HOST\24NPEA_ETH\25NPEB_ETH\26RSA" 440186418Ssam 441164426Ssam/* 442164426Ssam * PCI 443164426Ssam */ 444164426Ssam#define IXP425_PCI_HWBASE 0xc0000000 445189463Ssam#define IXP425_PCI_VBASE 0xf0017000UL 446189463Ssam#define IXP425_PCI_SIZE 0x1000 447164426Ssam 448186352Ssam#define IXP425_AHB_OFFSET 0x00000000UL /* AHB bus */ 449186352Ssam 450164426Ssam/* 451164426Ssam * Mapping registers of IXP425 PCI Configuration 452164426Ssam */ 453164426Ssam/* PCI_ID_REG 0x00 */ 454164426Ssam/* PCI_COMMAND_STATUS_REG 0x04 */ 455164426Ssam/* PCI_CLASS_REG 0x08 */ 456164426Ssam/* PCI_BHLC_REG 0x0c */ 457164426Ssam#define PCI_MAPREG_BAR0 0x10 /* Base Address 0 */ 458164426Ssam#define PCI_MAPREG_BAR1 0x14 /* Base Address 1 */ 459164426Ssam#define PCI_MAPREG_BAR2 0x18 /* Base Address 2 */ 460164426Ssam#define PCI_MAPREG_BAR3 0x1c /* Base Address 3 */ 461164426Ssam#define PCI_MAPREG_BAR4 0x20 /* Base Address 4 */ 462164426Ssam#define PCI_MAPREG_BAR5 0x24 /* Base Address 5 */ 463164426Ssam/* PCI_SUBSYS_ID_REG 0x2c */ 464164426Ssam/* PCI_INTERRUPT_REG 0x3c */ 465164426Ssam#define PCI_RTOTTO 0x40 466164426Ssam 467164426Ssam/* PCI Controller CSR Base Address */ 468164426Ssam#define IXP425_PCI_CSR_BASE IXP425_PCI_VBASE 469164426Ssam 470164426Ssam/* PCI Memory Space */ 471164426Ssam#define IXP425_PCI_MEM_HWBASE 0x48000000UL 472164426Ssam#define IXP425_PCI_MEM_VBASE 0xf8000000UL 473164426Ssam#define IXP425_PCI_MEM_SIZE 0x04000000UL /* 64MB */ 474164426Ssam 475164426Ssam/* PCI I/O Space */ 476164426Ssam#define IXP425_PCI_IO_HWBASE 0x00000000UL 477164426Ssam#define IXP425_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */ 478164426Ssam 479164426Ssam/* PCI Controller Configuration Offset */ 480164426Ssam#define PCI_NP_AD 0x00 481164426Ssam#define PCI_NP_CBE 0x04 482164426Ssam# define NP_CBE_SHIFT 4 483164426Ssam#define PCI_NP_WDATA 0x08 484164426Ssam#define PCI_NP_RDATA 0x0c 485164426Ssam#define PCI_CRP_AD_CBE 0x10 486164426Ssam#define PCI_CRP_AD_WDATA 0x14 487164426Ssam#define PCI_CRP_AD_RDATA 0x18 488164426Ssam#define PCI_CSR 0x1c 489164426Ssam# define CSR_PRST (1U << 16) 490164426Ssam# define CSR_IC (1U << 15) 491164426Ssam# define CSR_ABE (1U << 4) 492164426Ssam# define CSR_PDS (1U << 3) 493164426Ssam# define CSR_ADS (1U << 2) 494164426Ssam# define CSR_HOST (1U << 0) 495164426Ssam#define PCI_ISR 0x20 496164426Ssam# define ISR_AHBE (1U << 3) 497164426Ssam# define ISR_PPE (1U << 2) 498164426Ssam# define ISR_PFE (1U << 1) 499164426Ssam# define ISR_PSE (1U << 0) 500164426Ssam#define PCI_INTEN 0x24 501164426Ssam#define PCI_DMACTRL 0x28 502164426Ssam#define PCI_AHBMEMBASE 0x2c 503164426Ssam#define PCI_AHBIOBASE 0x30 504164426Ssam#define PCI_PCIMEMBASE 0x34 505164426Ssam#define PCI_AHBDOORBELL 0x38 506164426Ssam#define PCI_PCIDOORBELL 0x3c 507164426Ssam#define PCI_ATPDMA0_AHBADDR 0x40 508164426Ssam#define PCI_ATPDMA0_PCIADDR 0x44 509164426Ssam#define PCI_ATPDMA0_LENGTH 0x48 510164426Ssam#define PCI_ATPDMA1_AHBADDR 0x4c 511164426Ssam#define PCI_ATPDMA1_PCIADDR 0x50 512164426Ssam#define PCI_ATPDMA1_LENGTH 0x54 513164426Ssam#define PCI_PTADMA0_AHBADDR 0x58 514164426Ssam#define PCI_PTADMA0_PCIADDR 0x5c 515164426Ssam#define PCI_PTADMA0_LENGTH 0x60 516164426Ssam#define PCI_PTADMA1_AHBADDR 0x64 517164426Ssam#define PCI_PTADMA1_PCIADDR 0x68 518164426Ssam#define PCI_PTADMA1_LENGTH 0x6c 519164426Ssam 520164426Ssam/* PCI target(T)/initiator(I) Interface Commands for PCI_NP_CBE register */ 521164426Ssam#define COMMAND_NP_IA 0x0 /* Interrupt Acknowledge (I)*/ 522164426Ssam#define COMMAND_NP_SC 0x1 /* Special Cycle (I)*/ 523164426Ssam#define COMMAND_NP_IO_READ 0x2 /* I/O Read (T)(I) */ 524164426Ssam#define COMMAND_NP_IO_WRITE 0x3 /* I/O Write (T)(I) */ 525164426Ssam#define COMMAND_NP_MEM_READ 0x6 /* Memory Read (T)(I) */ 526164426Ssam#define COMMAND_NP_MEM_WRITE 0x7 /* Memory Write (T)(I) */ 527164426Ssam#define COMMAND_NP_CONF_READ 0xa /* Configuration Read (T)(I) */ 528164426Ssam#define COMMAND_NP_CONF_WRITE 0xb /* Configuration Write (T)(I) */ 529164426Ssam 530164426Ssam/* PCI byte enables */ 531164426Ssam#define BE_8BIT(a) ((0x10u << ((a) & 0x03)) ^ 0xf0) 532164426Ssam#define BE_16BIT(a) ((0x30u << ((a) & 0x02)) ^ 0xf0) 533164426Ssam#define BE_32BIT(a) 0x00 534164426Ssam 535164426Ssam/* PCI byte selects */ 536164426Ssam#define READ_8BIT(v,a) ((u_int8_t)((v) >> (((a) & 3) * 8))) 537164426Ssam#define READ_16BIT(v,a) ((u_int16_t)((v) >> (((a) & 2) * 8))) 538164426Ssam#define WRITE_8BIT(v,a) (((u_int32_t)(v)) << (((a) & 3) * 8)) 539164426Ssam#define WRITE_16BIT(v,a) (((u_int32_t)(v)) << (((a) & 2) * 8)) 540164426Ssam 541164426Ssam/* PCI Controller Configuration Commands for PCI_CRP_AD_CBE */ 542164426Ssam#define COMMAND_CRP_READ 0x00 543164426Ssam#define COMMAND_CRP_WRITE (1U << 16) 544164426Ssam 545164426Ssam/* 546164426Ssam * SDRAM Configuration Register 547164426Ssam */ 548164426Ssam#define IXP425_MCU_HWBASE 0xcc000000UL 549164426Ssam#define IXP425_MCU_VBASE 0xf0200000UL 550164426Ssam#define IXP425_MCU_SIZE 0x1000 /* Actually only 256 bytes */ 551164426Ssam#define MCU_SDR_CONFIG 0x00 552164426Ssam#define MCU_SDR_CONFIG_MCONF(x) ((x) & 0x7) 553164426Ssam#define MCU_SDR_CONFIG_64MBIT (1u << 5) 554164426Ssam#define MCU_SDR_REFRESH 0x04 555164426Ssam#define MCU_SDR_IR 0x08 556164426Ssam 557164426Ssam/* 558186352Ssam * IXP435 DDR MCU Registers 559186352Ssam */ 560186352Ssam#define IXP435_MCU_HWBASE 0xcc00e500UL 561186352Ssam#define MCU_DDR_SDIR 0x00 /* DDR SDAM Initialization Reg*/ 562186352Ssam#define MCU_DDR_SDCR0 0x04 /* DDR SDRAM Control Reg 0 */ 563186352Ssam#define MCU_DDR_SDCR1 0x08 /* DDR SDRAM Control Reg 1 */ 564186352Ssam#define MCU_DDR_SDBR 0x0c /* SDRAM Base Register */ 565186352Ssam#define MCU_DDR_SBR0 0x10 /* SDRAM Boundary Register 0 */ 566186352Ssam#define MCU_DDR_SBR1 0x14 /* SDRAM Boundary Register 1 */ 567186352Ssam#define MCU_DDR_ECCR 0x1c /* ECC Control Register */ 568186352Ssam#define MCU_DDR_ELOG0 0x20 /* ECC Log Register 0 */ 569186352Ssam#define MCU_DDR_ELOG1 0x24 /* ECC Log Register 1 */ 570186352Ssam#define MCU_DDR_ECAR0 0x28 /* ECC Address Register 0 */ 571186352Ssam#define MCU_DDR_ECAR1 0x2c /* ECC Address Register 1 */ 572186352Ssam#define MCU_DDR_ECTST 0x30 /* ECC Test Register */ 573186352Ssam#define MCU_DDR_MCISR 0x34 /* MC Interrupt Status Reg */ 574186352Ssam#define MCU_DDR_MPTCR 0x3c /* MC Port Transaction Cnt Reg*/ 575186352Ssam#define MCU_DDR_RFR 0x48 /* Refresh Frequency Register */ 576186352Ssam#define MCU_DDR_SDPR(n) (0x50+(n)*4) /* SDRAM Page Register 0-7 */ 577186352Ssam/* NB: RCVDLY at 0x1050 and LEGOVERIDE at 0x1074 */ 578186352Ssam 579186352Ssam/* 580164426Ssam * Performance Monitoring Unit (CP14) 581164426Ssam * 582164426Ssam * CP14.0.1 Performance Monitor Control Register(PMNC) 583164426Ssam * CP14.1.1 Clock Counter(CCNT) 584164426Ssam * CP14.4.1 Interrupt Enable Register(INTEN) 585164426Ssam * CP14.5.1 Overflow Flag Register(FLAG) 586164426Ssam * CP14.8.1 Event Selection Register(EVTSEL) 587164426Ssam * CP14.0.2 Performance Counter Register 0(PMN0) 588164426Ssam * CP14.1.2 Performance Counter Register 0(PMN1) 589164426Ssam * CP14.2.2 Performance Counter Register 0(PMN2) 590164426Ssam * CP14.3.2 Performance Counter Register 0(PMN3) 591164426Ssam */ 592164426Ssam 593164426Ssam#define PMNC_E 0x00000001 /* enable all counters */ 594164426Ssam#define PMNC_P 0x00000002 /* reset all PMNs to 0 */ 595164426Ssam#define PMNC_C 0x00000004 /* clock counter reset */ 596164426Ssam#define PMNC_D 0x00000008 /* clock counter / 64 */ 597164426Ssam 598164426Ssam#define INTEN_CC_IE 0x00000001 /* enable clock counter interrupt */ 599164426Ssam#define INTEN_PMN0_IE 0x00000002 /* enable PMN0 interrupt */ 600164426Ssam#define INTEN_PMN1_IE 0x00000004 /* enable PMN1 interrupt */ 601164426Ssam#define INTEN_PMN2_IE 0x00000008 /* enable PMN2 interrupt */ 602164426Ssam#define INTEN_PMN3_IE 0x00000010 /* enable PMN3 interrupt */ 603164426Ssam 604164426Ssam#define FLAG_CC_IF 0x00000001 /* clock counter overflow */ 605164426Ssam#define FLAG_PMN0_IF 0x00000002 /* PMN0 overflow */ 606164426Ssam#define FLAG_PMN1_IF 0x00000004 /* PMN1 overflow */ 607164426Ssam#define FLAG_PMN2_IF 0x00000008 /* PMN2 overflow */ 608164426Ssam#define FLAG_PMN3_IF 0x00000010 /* PMN3 overflow */ 609164426Ssam 610164426Ssam#define EVTSEL_EVCNT_MASK 0x0000000ff /* event to count for PMNs */ 611164426Ssam#define PMNC_EVCNT0_SHIFT 0 612164426Ssam#define PMNC_EVCNT1_SHIFT 8 613164426Ssam#define PMNC_EVCNT2_SHIFT 16 614164426Ssam#define PMNC_EVCNT3_SHIFT 24 615164426Ssam 616164426Ssam/* 617164426Ssam * Queue Manager 618164426Ssam */ 619164426Ssam#define IXP425_QMGR_HWBASE 0x60000000UL 620189463Ssam#define IXP425_QMGR_VBASE 0xf0018000UL 621164426Ssam#define IXP425_QMGR_SIZE 0x4000 622164426Ssam 623164426Ssam/* 624164426Ssam * Network Processing Engines (NPE's) and associated Ethernet MAC's. 625164426Ssam */ 626164426Ssam#define IXP425_NPE_A_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_A_OFFSET) 627164426Ssam#define IXP425_NPE_A_VBASE (IXP425_IO_VBASE + IXP425_NPE_A_OFFSET) 628164426Ssam#define IXP425_NPE_A_SIZE 0x1000 /* Actually only 256 bytes */ 629164426Ssam 630164426Ssam#define IXP425_NPE_B_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_B_OFFSET) 631164426Ssam#define IXP425_NPE_B_VBASE (IXP425_IO_VBASE + IXP425_NPE_B_OFFSET) 632164426Ssam#define IXP425_NPE_B_SIZE 0x1000 /* Actually only 256 bytes */ 633164426Ssam 634164426Ssam#define IXP425_NPE_C_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_C_OFFSET) 635164426Ssam#define IXP425_NPE_C_VBASE (IXP425_IO_VBASE + IXP425_NPE_C_OFFSET) 636164426Ssam#define IXP425_NPE_C_SIZE 0x1000 /* Actually only 256 bytes */ 637164426Ssam 638164426Ssam#define IXP425_MAC_B_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_B_OFFSET) 639164426Ssam#define IXP425_MAC_B_VBASE (IXP425_IO_VBASE + IXP425_MAC_B_OFFSET) 640164426Ssam#define IXP425_MAC_B_SIZE 0x1000 /* Actually only 256 bytes */ 641164426Ssam 642186352Ssam#define IXP425_MAC_C_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_C_OFFSET) 643186352Ssam#define IXP425_MAC_C_VBASE (IXP425_IO_VBASE + IXP425_MAC_C_OFFSET) 644186352Ssam#define IXP425_MAC_C_SIZE 0x1000 /* Actually only 256 bytes */ 645186352Ssam 646186352Ssam#define IXP435_MAC_A_HWBASE (IXP425_IO_HWBASE + IXP435_MAC_A_OFFSET) 647186352Ssam#define IXP435_MAC_A_VBASE (IXP425_IO_VBASE + IXP435_MAC_A_OFFSET) 648186352Ssam#define IXP435_MAC_A_SIZE 0x1000 /* Actually only 256 bytes */ 649186352Ssam 650164426Ssam/* 651164426Ssam * Expansion Bus Data Space. 652164426Ssam */ 653164426Ssam#define IXP425_EXP_BUS_HWBASE 0x50000000UL 654164426Ssam#define IXP425_EXP_BUS_SIZE 0x01000000 /* max, typically smaller */ 655164426Ssam 656164426Ssam#define IXP425_EXP_BUS_CSx_HWBASE(i) \ 657164426Ssam (IXP425_EXP_BUS_HWBASE + (i)*IXP425_EXP_BUS_SIZE) 658189463Ssam#define IXP425_EXP_BUS_CSx_SIZE 0x1000 659167570Sjhay#define IXP425_EXP_BUS_CSx_VBASE(i) \ 660189463Ssam (0xF0011000UL + (((i)-1)*IXP425_EXP_BUS_CSx_SIZE)) 661167570Sjhay 662189463Ssam/* NB: CS0 is special; it maps flash */ 663188088Ssam#define IXP425_EXP_BUS_CS0_HWBASE IXP425_EXP_BUS_CSx_HWBASE(0) 664188088Ssam#define IXP425_EXP_BUS_CS0_VBASE 0xFD000000UL 665189651Ssam#ifndef IXP4XX_FLASH_SIZE 666188088Ssam#define IXP425_EXP_BUS_CS0_SIZE 0x01000000 /* NB: 16M */ 667189651Ssam#else 668189651Ssam#define IXP425_EXP_BUS_CS0_SIZE IXP4XX_FLASH_SIZE 669189651Ssam#endif 670164426Ssam#define IXP425_EXP_BUS_CS1_HWBASE IXP425_EXP_BUS_CSx_HWBASE(1) 671167570Sjhay#define IXP425_EXP_BUS_CS1_VBASE IXP425_EXP_BUS_CSx_VBASE(1) 672189463Ssam#define IXP425_EXP_BUS_CS1_SIZE IXP425_EXP_BUS_CSx_SIZE 673167570Sjhay#define IXP425_EXP_BUS_CS2_HWBASE IXP425_EXP_BUS_CSx_HWBASE(2) 674167570Sjhay#define IXP425_EXP_BUS_CS2_VBASE IXP425_EXP_BUS_CSx_VBASE(2) 675189463Ssam#define IXP425_EXP_BUS_CS2_SIZE IXP425_EXP_BUS_CSx_SIZE 676167570Sjhay#define IXP425_EXP_BUS_CS3_HWBASE IXP425_EXP_BUS_CSx_HWBASE(3) 677167570Sjhay#define IXP425_EXP_BUS_CS3_VBASE IXP425_EXP_BUS_CSx_VBASE(3) 678189463Ssam#define IXP425_EXP_BUS_CS3_SIZE IXP425_EXP_BUS_CSx_SIZE 679167570Sjhay#define IXP425_EXP_BUS_CS4_HWBASE IXP425_EXP_BUS_CSx_HWBASE(4) 680167570Sjhay#define IXP425_EXP_BUS_CS4_VBASE IXP425_EXP_BUS_CSx_VBASE(4) 681189463Ssam#define IXP425_EXP_BUS_CS4_SIZE IXP425_EXP_BUS_CSx_SIZE 682164426Ssam 683164426Ssam/* NB: not mapped (yet) */ 684164426Ssam#define IXP425_EXP_BUS_CS5_HWBASE IXP425_EXP_BUS_CSx_HWBASE(5) 685164426Ssam#define IXP425_EXP_BUS_CS6_HWBASE IXP425_EXP_BUS_CSx_HWBASE(6) 686164426Ssam#define IXP425_EXP_BUS_CS7_HWBASE IXP425_EXP_BUS_CSx_HWBASE(7) 687164426Ssam 688186352Ssam/* 689186352Ssam * IXP435/Gateworks Cambria 690186352Ssam */ 691194654Ssam#define IXP435_USB1_HWBASE 0xCD000000UL /* USB host controller 1 */ 692194654Ssam#define IXP435_USB1_VBASE 0xF001C000UL 693194654Ssam#define IXP435_USB1_SIZE 0x1000 /* NB: only uses 0x300 */ 694194654Ssam 695194654Ssam#define IXP435_USB2_HWBASE 0xCE000000UL /* USB host controller 2 */ 696194654Ssam#define IXP435_USB2_VBASE 0xF001D000UL 697194654Ssam#define IXP435_USB2_SIZE 0x1000 /* NB: only uses 0x300 */ 698194654Ssam 699186352Ssam#define CAMBRIA_GPS_HWBASE 0x53FC0000UL /* optional GPS Serial Port */ 700194654Ssam#define CAMBRIA_GPS_VBASE 0xF001E000UL 701194654Ssam#define CAMBRIA_GPS_SIZE 0x1000 702186352Ssam#define CAMBRIA_RS485_HWBASE 0x53F80000UL /* optional RS485 Serial Port */ 703194654Ssam#define CAMBRIA_RS485_VBASE 0xF001F000UL 704194654Ssam#define CAMBRIA_RS485_SIZE 0x1000 705194654Ssam 706194654Ssam/* NB: these are mapped on the fly, so no fixed virtual addresses */ 707186352Ssam#define CAMBRIA_OCTAL_LED_HWBASE 0x53F40000UL /* Octal Status LED Latch */ 708186352Ssam#define CAMBRIA_OCTAL_LED_SIZE 0x1000 709186352Ssam#define CAMBRIA_CFSEL1_HWBASE 0x53E40000UL /* Compact Flash Socket Sel 0 */ 710186352Ssam#define CAMBRIA_CFSEL1_SIZE 0x40000 711186352Ssam#define CAMBRIA_CFSEL0_HWBASE 0x53E00000UL /* Compact Flash Socket Sel 1 */ 712186352Ssam#define CAMBRIA_CFSEL0_SIZE 0x40000 713186352Ssam 714164426Ssam#endif /* _IXP425REG_H_ */ 715