1259698Sdim/*- 2259698Sdim * Copyright (c) 2006 Sam Leffler, Errno Consulting 3259698Sdim * All rights reserved. 4259698Sdim * 5259698Sdim * Redistribution and use in source and binary forms, with or without 6259698Sdim * modification, are permitted provided that the following conditions 7259698Sdim * are met: 8259698Sdim * 1. Redistributions of source code must retain the above copyright 9259698Sdim * notice, this list of conditions and the following disclaimer, 10259698Sdim * without modification. 11259698Sdim * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12259698Sdim * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13259698Sdim * redistribution must be conditioned upon including a substantially 14259698Sdim * similar Disclaimer requirement for further binary redistribution. 15259698Sdim * 16259698Sdim * NO WARRANTY 17259698Sdim * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18259698Sdim * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19259698Sdim * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20259698Sdim * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21259698Sdim * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22259698Sdim * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23259698Sdim * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24259698Sdim * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25259698Sdim * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26259698Sdim * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27259698Sdim * THE POSSIBILITY OF SUCH DAMAGES. 28259698Sdim * 29259698Sdim * $FreeBSD: releng/11.0/sys/arm/xscale/ixp425/ixp425_npereg.h 299069 2016-05-04 15:48:59Z pfg $ 30259698Sdim */ 31259698Sdim 32259698Sdim/*- 33259698Sdim * Copyright (c) 2001-2005, Intel Corporation. 34259698Sdim * All rights reserved. 35259698Sdim * 36259698Sdim * Redistribution and use in source and binary forms, with or without 37259698Sdim * modification, are permitted provided that the following conditions 38259698Sdim * are met: 39259698Sdim * 1. Redistributions of source code must retain the above copyright 40259698Sdim * notice, this list of conditions and the following disclaimer. 41259698Sdim * 2. Redistributions in binary form must reproduce the above copyright 42259698Sdim * notice, this list of conditions and the following disclaimer in the 43259698Sdim * documentation and/or other materials provided with the distribution. 44259698Sdim * 3. Neither the name of the Intel Corporation nor the names of its contributors 45259698Sdim * may be used to endorse or promote products derived from this software 46259698Sdim * without specific prior written permission. 47276479Sdim * 48259698Sdim * 49259698Sdim * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 50259698Sdim * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 51259698Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 52259698Sdim * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 53259698Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 54259698Sdim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 55259698Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 56259698Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 57259698Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 58259698Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 59259698Sdim * SUCH DAMAGE. 60259698Sdim*/ 61259698Sdim 62259698Sdim#ifndef _IXP425_NPEREG_H_ 63259698Sdim#define _IXP425_NPEREG_H_ 64259698Sdim 65259698Sdim/* signature found as 1st word in a microcode image library */ 66259698Sdim#define IX_NPEDL_IMAGEMGR_SIGNATURE 0xDEADBEEF 67259698Sdim/* marks end of header in a microcode image library */ 68259698Sdim#define IX_NPEDL_IMAGEMGR_END_OF_HEADER 0xFFFFFFFF 69259698Sdim 70259698Sdim/* 71259698Sdim * Intel (R) IXP400 Software NPE Image ID Definition 72259698Sdim * 73259698Sdim * Definition of NPE Image ID to be passed to ixNpeDlNpeInitAndStart() 74259698Sdim * as input of type uint32_t which has the following fields format: 75259698Sdim * 76259698Sdim * Field [Bit Location] 77259698Sdim * ----------------------------------- 78259698Sdim * Device ID [31 - 28] 79259698Sdim * NPE ID [27 - 24] 80259698Sdim * NPE Functionality ID [23 - 16] 81259698Sdim * Major Release Number [15 - 8] 82259698Sdim * Minor Release Number [7 - 0] 83280031Sdim */ 84259698Sdim#define IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId) \ 85259698Sdim (((imageId) >> 24) & 0xf) 86259698Sdim#define IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId) \ 87259698Sdim (((imageId) >> 28) & 0xf) 88259698Sdim#define IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \ 89259698Sdim (((imageId) >> 16) & 0xff) 90259698Sdim#define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \ 91259698Sdim (((imageId) >> 8) & 0xff) 92259698Sdim#define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \ 93259698Sdim (((imageId) >> 0) & 0xff) 94259698Sdim 95259698Sdim/* 96259698Sdim * Instruction and Data Memory Size (in words) for each NPE 97259698Sdim */ 98259698Sdim#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096 99259698Sdim#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048 100259698Sdim#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048 101259698Sdim 102259698Sdim#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048 103259698Sdim#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048 104259698Sdim#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048 105259698Sdim 106259698Sdim#define IXP46X_NPEDL_INS_MEMSIZE_WORDS 4096 107259698Sdim#define IXP46X_NPEDL_DATA_MEMSIZE_WORDS 4096 108259698Sdim 109259698Sdim/* BAR offsets */ 110259698Sdim#define IX_NPEDL_REG_OFFSET_EXAD 0x00000000 /* Execution Address */ 111259698Sdim#define IX_NPEDL_REG_OFFSET_EXDATA 0x00000004 /* Execution Data */ 112259698Sdim#define IX_NPEDL_REG_OFFSET_EXCTL 0x00000008 /* Execution Control */ 113259698Sdim#define IX_NPEDL_REG_OFFSET_EXCT 0x0000000C /* Execution Count */ 114259698Sdim#define IX_NPEDL_REG_OFFSET_AP0 0x00000010 /* Action Point 0 */ 115259698Sdim#define IX_NPEDL_REG_OFFSET_AP1 0x00000014 /* Action Point 1 */ 116259698Sdim#define IX_NPEDL_REG_OFFSET_AP2 0x00000018 /* Action Point 2 */ 117259698Sdim#define IX_NPEDL_REG_OFFSET_AP3 0x0000001C /* Action Point 3 */ 118259698Sdim#define IX_NPEDL_REG_OFFSET_WFIFO 0x00000020 /* Watchpoint FIFO */ 119259698Sdim#define IX_NPEDL_REG_OFFSET_WC 0x00000024 /* Watch Count */ 120259698Sdim#define IX_NPEDL_REG_OFFSET_PROFCT 0x00000028 /* Profile Count */ 121259698Sdim#define IX_NPEDL_REG_OFFSET_STAT 0x0000002C /* Messaging Status */ 122259698Sdim#define IX_NPEDL_REG_OFFSET_CTL 0x00000030 /* Messaging Control */ 123259698Sdim#define IX_NPEDL_REG_OFFSET_MBST 0x00000034 /* Mailbox Status */ 124259698Sdim#define IX_NPEDL_REG_OFFSET_FIFO 0x00000038 /* Message FIFO */ 125259698Sdim 126259698Sdim/* 127259698Sdim * Reset value for Mailbox (MBST) register 128259698Sdim * NOTE that if used, it should be complemented with an NPE instruction 129259698Sdim * to clear the Mailbox at the NPE side as well 130259698Sdim */ 131259698Sdim#define IX_NPEDL_REG_RESET_MBST 0x0000F0F0 132259698Sdim 133259698Sdim#define IX_NPEDL_MASK_WFIFO_VALID 0x80000000 /* VALID bit */ 134259698Sdim#define IX_NPEDL_MASK_STAT_OFNE 0x00010000 /* OFNE bit */ 135259698Sdim#define IX_NPEDL_MASK_STAT_IFNE 0x00080000 /* IFNE bit */ 136259698Sdim 137259698Sdim/* 138259698Sdim * EXCTL (Execution Control) Register commands 139259698Sdim*/ 140259698Sdim#define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01 /* Step 1 instruction */ 141259698Sdim#define IX_NPEDL_EXCTL_CMD_NPE_START 0x02 /* Start execution */ 142259698Sdim#define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03 /* Stop execution */ 143259698Sdim#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04 /* Clear ins pipeline */ 144259698Sdim 145259698Sdim/* 146259698Sdim * Read/write operations use address in EXAD and data in EXDATA. 147259698Sdim */ 148259698Sdim#define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10 /* Read ins memory */ 149259698Sdim#define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11 /* Write ins memory */ 150259698Sdim#define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12 /* Read data memory */ 151259698Sdim#define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13 /* Write data memory */ 152259698Sdim#define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14 /* Read ECS register */ 153259698Sdim#define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15 /* Write ECS register */ 154259698Sdim 155259698Sdim#define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C /* Clear Profile Count register */ 156259698Sdim 157259698Sdim 158259698Sdim/* 159259698Sdim * EXCTL (Execution Control) Register status bit masks 160259698Sdim */ 161259698Sdim#define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000 162259698Sdim#define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000 163259698Sdim#define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000 164259698Sdim#define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000 /* pipeline Klean */ 165259698Sdim 166259698Sdim/* 167259698Sdim * Executing Context Stack (ECS) level registers 168259698Sdim */ 169259698Sdim#define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00 /* reg 0 @ bg ctx */ 170259698Sdim#define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01 /* reg 1 @ bg ctx */ 171259698Sdim#define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02 /* reg 2 @ bg ctx */ 172259698Sdim 173259698Sdim#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04 /* reg 0 @ pri 1 ctx */ 174259698Sdim#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05 /* reg 1 @ pri 1 ctx */ 175259698Sdim#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06 /* reg 2 @ pri 1 ctx */ 176259698Sdim 177259698Sdim#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08 /* reg 0 @ pri 2 ctx */ 178259698Sdim#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1 0x09 /* reg 1 @ pri 2 ctx */ 179259698Sdim#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2 0x0A /* reg 2 @ pri 2 ctx */ 180259698Sdim 181259698Sdim#define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C /* reg 0 @ debug ctx */ 182259698Sdim#define IX_NPEDL_ECS_DBG_CTXT_REG_1 0x0D /* reg 1 @ debug ctx */ 183259698Sdim#define IX_NPEDL_ECS_DBG_CTXT_REG_2 0x0E /* reg 2 @ debug ctx */ 184259698Sdim 185259698Sdim#define IX_NPEDL_ECS_INSTRUCT_REG 0x11 /* Instruction reg */ 186259698Sdim 187259698Sdim/* 188259698Sdim * Execution Access register reset values 189259698Sdim */ 190259698Sdim#define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 0xA0000000 191259698Sdim#define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 0x01000000 192259698Sdim#define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 0x00008000 193259698Sdim#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 0x20000080 194259698Sdim#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 0x01000000 195259698Sdim#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 0x00008000 196259698Sdim#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 0x20000080 197259698Sdim#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 0x01000000 198259698Sdim#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 0x00008000 199259698Sdim#define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 0x20000000 200259698Sdim#define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 0x00000000 201259698Sdim#define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 0x001E0000 202259698Sdim#define IX_NPEDL_ECS_INSTRUCT_REG_RESET 0x1003C00F 203259698Sdim 204259698Sdim/* 205259698Sdim * Masks used to read/write particular bits in Execution Access registers 206259698Sdim */ 207259698Sdim 208259698Sdim#define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000 /* Active bit */ 209276479Sdim#define IX_NPEDL_MASK_ECS_REG_0_NEXTPC 0x1FFF0000 /* NextPC bits */ 210259698Sdim#define IX_NPEDL_MASK_ECS_REG_0_LDUR 0x00000700 /* LDUR bits */ 211259698Sdim 212259698Sdim#define IX_NPEDL_MASK_ECS_REG_1_CCTXT 0x000F0000 /* NextPC bits */ 213259698Sdim#define IX_NPEDL_MASK_ECS_REG_1_SELCTXT 0x0000000F 214259698Sdim 215259698Sdim#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000 /* IF bit */ 216259698Sdim#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000 /* IE bit */ 217259698Sdim 218259698Sdim 219259698Sdim/* 220259698Sdim * Bit-Offsets from LSB of particular bit-fields in Execution Access registers. 221259698Sdim */ 222276479Sdim 223259698Sdim#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16 224259698Sdim#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8 225259698Sdim 226259698Sdim#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16 227259698Sdim#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0 228259698Sdim 229259698Sdim/* 230259698Sdim * NPE core & co-processor instruction templates to load into NPE Instruction 231259698Sdim * Register, for read/write of NPE register file registers. 232259698Sdim */ 233259698Sdim 234259698Sdim/* 235259698Sdim * Read an 8-bit NPE internal logical register 236259698Sdim * and return the value in the EXDATA register (aligned to MSB). 237259698Sdim * NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec" 238259698Sdim */ 239259698Sdim#define IX_NPEDL_INSTR_RD_REG_BYTE 0x0FC00000 240259698Sdim 241259698Sdim/* 242259698Sdim * Read a 16-bit NPE internal logical register 243259698Sdim * and return the value in the EXDATA register (aligned to MSB). 244259698Sdim * NPE Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec" 245259698Sdim */ 246259698Sdim#define IX_NPEDL_INSTR_RD_REG_SHORT 0x0FC08010 247259698Sdim 248259698Sdim/* 249259698Sdim * Read a 16-bit NPE internal logical register 250259698Sdim * and return the value in the EXDATA register. 251259698Sdim * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec" 252259698Sdim */ 253259698Sdim#define IX_NPEDL_INSTR_RD_REG_WORD 0x0FC08210 254259698Sdim 255259698Sdim/* 256259698Sdim * Write an 8-bit NPE internal logical register. 257259698Sdim * NPE Assembler instruction: "mov8 d0, #0" 258259698Sdim */ 259259698Sdim#define IX_NPEDL_INSTR_WR_REG_BYTE 0x00004000 260259698Sdim 261259698Sdim/* 262259698Sdim * Write a 16-bit NPE internal logical register. 263259698Sdim * NPE Assembler instruction: "mov16 d0, #0" 264259698Sdim */ 265259698Sdim#define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000 266259698Sdim 267259698Sdim/* 268259698Sdim * Write a 16-bit NPE internal logical register. 269259698Sdim * NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO" 270259698Sdim */ 271259698Sdim#define IX_NPEDL_INSTR_RD_FIFO 0x0F888220 272259698Sdim 273259698Sdim/* 274259698Sdim * Reset Mailbox (MBST) register 275259698Sdim * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM" 276259698Sdim */ 277259698Sdim#define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210 278259698Sdim 279259698Sdim 280259698Sdim/* 281259698Sdim * Bit-offsets from LSB, of particular bit-fields in an NPE instruction 282259698Sdim */ 283259698Sdim#define IX_NPEDL_OFFSET_INSTR_SRC 4 /* src operand */ 284259698Sdim#define IX_NPEDL_OFFSET_INSTR_DEST 9 /* dest operand */ 285259698Sdim#define IX_NPEDL_OFFSET_INSTR_COPROC 18 /* coprocessor ins */ 286259698Sdim 287259698Sdim/* 288259698Sdim * Masks used to read/write particular bits of an NPE Instruction 289259698Sdim */ 290259698Sdim 291259698Sdim/** 292259698Sdim * Mask the bits of 16-bit data value (least-sig 5 bits) to be used in 293259698Sdim * SRC field of immediate-mode NPE instruction 294259698Sdim */ 295259698Sdim#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F 296259698Sdim 297259698Sdim/** 298259698Sdim * Mask the bits of 16-bit data value (most-sig 11 bits) to be used in 299259698Sdim * COPROC field of immediate-mode NPE instruction 300259698Sdim */ 301259698Sdim#define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0 302259698Sdim 303259698Sdim/** 304259698Sdim * LSB offset of the bit-field of 16-bit data value (most-sig 11 bits) 305259698Sdim * to be used in COPROC field of immediate-mode NPE instruction 306259698Sdim */ 307259698Sdim#define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 5 308259698Sdim 309259698Sdim/** 310259698Sdim * Number of left-shifts required to align most-sig 11 bits of 16-bit 311259698Sdim * data value into COPROC field of immediate-mode NPE instruction 312259698Sdim */ 313259698Sdim#define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \ 314259698Sdim (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA) 315259698Sdim 316259698Sdim/** 317259698Sdim * LDUR value used with immediate-mode NPE Instructions by the NpeDl 318259698Sdim * for writing to NPE internal logical registers 319259698Sdim */ 320259698Sdim#define IX_NPEDL_WR_INSTR_LDUR 1 321259698Sdim 322259698Sdim/** 323259698Sdim * LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl 324259698Sdim * for reading from NPE internal logical registers 325259698Sdim */ 326259698Sdim#define IX_NPEDL_RD_INSTR_LDUR 0 327276479Sdim 328259698Sdim 329259698Sdim/** 330259698Sdim * NPE internal Context Store registers. 331259698Sdim */ 332259698Sdimtypedef enum 333259698Sdim{ 334259698Sdim IX_NPEDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */ 335259698Sdim IX_NPEDL_CTXT_REG_STARTPC, /**< identifies STARTPC */ 336259698Sdim IX_NPEDL_CTXT_REG_REGMAP, /**< identifies REGMAP */ 337259698Sdim IX_NPEDL_CTXT_REG_CINDEX, /**< identifies CINDEX */ 338259698Sdim IX_NPEDL_CTXT_REG_MAX /**< Total number of Context Store registers */ 339259698Sdim} IxNpeDlCtxtRegNum; 340259698Sdim 341259698Sdim 342259698Sdim/* 343259698Sdim * NPE Context Store register logical addresses 344259698Sdim */ 345259698Sdim#define IX_NPEDL_CTXT_REG_ADDR_STEVT 0x0000001B 346259698Sdim#define IX_NPEDL_CTXT_REG_ADDR_STARTPC 0x0000001C 347259698Sdim#define IX_NPEDL_CTXT_REG_ADDR_REGMAP 0x0000001E 348259698Sdim#define IX_NPEDL_CTXT_REG_ADDR_CINDEX 0x0000001F 349259698Sdim 350259698Sdim/* 351259698Sdim * NPE Context Store register reset values 352259698Sdim */ 353259698Sdim 354259698Sdim/** 355259698Sdim * Reset value of STEVT NPE internal Context Store register 356259698Sdim * (STEVT = off, 0x80) 357259698Sdim */ 358259698Sdim#define IX_NPEDL_CTXT_REG_RESET_STEVT 0x80 359259698Sdim 360259698Sdim/** 361259698Sdim * Reset value of STARTPC NPE internal Context Store register 362259698Sdim * (STARTPC = 0x0000) 363280031Sdim */ 364259698Sdim#define IX_NPEDL_CTXT_REG_RESET_STARTPC 0x0000 365259698Sdim 366259698Sdim/** 367259698Sdim * Reset value of REGMAP NPE internal Context Store register 368259698Sdim * (REGMAP = d0->p0, d8->p2, d16->p4) 369259698Sdim */ 370259698Sdim#define IX_NPEDL_CTXT_REG_RESET_REGMAP 0x0820 371259698Sdim 372259698Sdim/** 373259698Sdim * Reset value of CINDEX NPE internal Context Store register 374259698Sdim * (CINDEX = 0) 375259698Sdim */ 376259698Sdim#define IX_NPEDL_CTXT_REG_RESET_CINDEX 0x00 377259698Sdim 378259698Sdim 379259698Sdim/* 380259698Sdim * Numeric range of context levels available on an NPE 381259698Sdim */ 382259698Sdim#define IX_NPEDL_CTXT_NUM_MIN 0 383259698Sdim#define IX_NPEDL_CTXT_NUM_MAX 15 384259698Sdim 385259698Sdim 386259698Sdim/** 387259698Sdim * Number of Physical registers currently supported 388259698Sdim * Initial NPE implementations will have a 32-word register file. 389259698Sdim * Later implementations may have a 64-word register file. 390 */ 391#define IX_NPEDL_TOTAL_NUM_PHYS_REG 32 392 393/** 394 * LSB-offset of Regmap number in Physical NPE register address, used 395 * for Physical To Logical register address mapping in the NPE 396 */ 397#define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 1 398 399/** 400 * Mask to extract a logical NPE register address from a physical 401 * register address, used for Physical To Logical address mapping 402 */ 403#define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 0x1 404 405/* 406 * NPE Message/Mailbox interface. 407 */ 408#define IX_NPESTAT IX_NPEDL_REG_OFFSET_STAT /* status register */ 409#define IX_NPECTL IX_NPEDL_REG_OFFSET_CTL /* control register */ 410#define IX_NPEFIFO IX_NPEDL_REG_OFFSET_FIFO /* FIFO register */ 411 412/* control register */ 413#define IX_NPECTL_OFE 0x00010000 /* output fifo enable */ 414#define IX_NPECTL_IFE 0x00020000 /* input fifo enable */ 415#define IX_NPECTL_OFWE 0x01000000 /* output fifo write enable */ 416#define IX_NPECTL_IFWE 0x02000000 /* input fifo write enable */ 417 418/* status register */ 419#define IX_NPESTAT_OFNE 0x00010000 /* output fifo not empty */ 420#define IX_NPESTAT_IFNF 0x00020000 /* input fifo not full */ 421#define IX_NPESTAT_OFNF 0x00040000 /* output fifo not full */ 422#define IX_NPESTAT_IFNE 0x00080000 /* input fifo not empty */ 423#define IX_NPESTAT_MBINT 0x00100000 /* Mailbox interrupt */ 424#define IX_NPESTAT_IFINT 0x00200000 /* input fifo interrupt */ 425#define IX_NPESTAT_OFINT 0x00400000 /* output fifo interrupt */ 426#define IX_NPESTAT_WFINT 0x00800000 /* watch fifo interrupt */ 427#endif /* _IXP425_NPEREG_H_ */ 428