if_npe.c revision 269645
1/*- 2 * Copyright (c) 2006-2008 Sam Leffler. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25#include <sys/cdefs.h> 26__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/if_npe.c 269645 2014-08-06 21:16:15Z jmg $"); 27 28/* 29 * Intel XScale NPE Ethernet driver. 30 * 31 * This driver handles the two ports present on the IXP425. 32 * Packet processing is done by the Network Processing Engines 33 * (NPE's) that work together with a MAC and PHY. The MAC 34 * is also mapped to the XScale cpu; the PHY is accessed via 35 * the MAC. NPE-XScale communication happens through h/w 36 * queues managed by the Q Manager block. 37 * 38 * The code here replaces the ethAcc, ethMii, and ethDB classes 39 * in the Intel Access Library (IAL) and the OS-specific driver. 40 * 41 * XXX add vlan support 42 */ 43#ifdef HAVE_KERNEL_OPTION_HEADERS 44#include "opt_device_polling.h" 45#endif 46 47#include <sys/param.h> 48#include <sys/systm.h> 49#include <sys/bus.h> 50#include <sys/kernel.h> 51#include <sys/mbuf.h> 52#include <sys/malloc.h> 53#include <sys/module.h> 54#include <sys/rman.h> 55#include <sys/socket.h> 56#include <sys/sockio.h> 57#include <sys/sysctl.h> 58#include <sys/endian.h> 59#include <machine/bus.h> 60 61#include <net/ethernet.h> 62#include <net/if.h> 63#include <net/if_arp.h> 64#include <net/if_dl.h> 65#include <net/if_media.h> 66#include <net/if_mib.h> 67#include <net/if_types.h> 68#include <net/if_var.h> 69 70#ifdef INET 71#include <netinet/in.h> 72#include <netinet/in_systm.h> 73#include <netinet/in_var.h> 74#include <netinet/ip.h> 75#endif 76 77#include <net/bpf.h> 78#include <net/bpfdesc.h> 79 80#include <arm/xscale/ixp425/ixp425reg.h> 81#include <arm/xscale/ixp425/ixp425var.h> 82#include <arm/xscale/ixp425/ixp425_qmgr.h> 83#include <arm/xscale/ixp425/ixp425_npevar.h> 84 85#include <dev/mii/mii.h> 86#include <dev/mii/miivar.h> 87#include <arm/xscale/ixp425/if_npereg.h> 88 89#include <machine/armreg.h> 90 91#include "miibus_if.h" 92 93/* 94 * XXX: For the main bus dma tag. Can go away if the new method to get the 95 * dma tag from the parent got MFC'd into RELENG_6. 96 */ 97extern struct ixp425_softc *ixp425_softc; 98 99struct npebuf { 100 struct npebuf *ix_next; /* chain to next buffer */ 101 void *ix_m; /* backpointer to mbuf */ 102 bus_dmamap_t ix_map; /* bus dma map for associated data */ 103 struct npehwbuf *ix_hw; /* associated h/w block */ 104 uint32_t ix_neaddr; /* phys address of ix_hw */ 105}; 106 107struct npedma { 108 const char* name; 109 int nbuf; /* # npebuf's allocated */ 110 bus_dma_tag_t mtag; /* bus dma tag for mbuf data */ 111 struct npehwbuf *hwbuf; /* NPE h/w buffers */ 112 bus_dma_tag_t buf_tag; /* tag+map for NPE buffers */ 113 bus_dmamap_t buf_map; 114 bus_addr_t buf_phys; /* phys addr of buffers */ 115 struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ 116}; 117 118struct npe_softc { 119 /* XXX mii requires this be first; do not move! */ 120 struct ifnet *sc_ifp; /* ifnet pointer */ 121 struct mtx sc_mtx; /* basically a perimeter lock */ 122 device_t sc_dev; 123 bus_space_tag_t sc_iot; 124 bus_space_handle_t sc_ioh; /* MAC register window */ 125 device_t sc_mii; /* child miibus */ 126 bus_space_handle_t sc_miih; /* MII register window */ 127 int sc_npeid; 128 struct ixpnpe_softc *sc_npe; /* NPE support */ 129 int sc_debug; /* DPRINTF* control */ 130 int sc_tickinterval; 131 struct callout tick_ch; /* Tick callout */ 132 int npe_watchdog_timer; 133 struct npedma txdma; 134 struct npebuf *tx_free; /* list of free tx buffers */ 135 struct npedma rxdma; 136 bus_addr_t buf_phys; /* XXX for returning a value */ 137 int rx_qid; /* rx qid */ 138 int rx_freeqid; /* rx free buffers qid */ 139 int tx_qid; /* tx qid */ 140 int tx_doneqid; /* tx completed qid */ 141 struct ifmib_iso_8802_3 mibdata; 142 bus_dma_tag_t sc_stats_tag; /* bus dma tag for stats block */ 143 struct npestats *sc_stats; 144 bus_dmamap_t sc_stats_map; 145 bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ 146 struct npestats sc_totals; /* accumulated sc_stats */ 147}; 148 149/* 150 * Static configuration for IXP425. The tx and 151 * rx free Q id's are fixed by the NPE microcode. The 152 * rx Q id's are programmed to be separate to simplify 153 * multi-port processing. It may be better to handle 154 * all traffic through one Q (as done by the Intel drivers). 155 * 156 * Note that the PHY's are accessible only from MAC B on the 157 * IXP425 and from MAC C on other devices. This and other 158 * platform-specific assumptions are handled with hints. 159 */ 160static const struct { 161 uint32_t macbase; 162 uint32_t miibase; 163 int phy; /* phy id */ 164 uint8_t rx_qid; 165 uint8_t rx_freeqid; 166 uint8_t tx_qid; 167 uint8_t tx_doneqid; 168} npeconfig[NPE_MAX] = { 169 [NPE_A] = { 170 .macbase = IXP435_MAC_A_HWBASE, 171 .miibase = IXP425_MAC_C_HWBASE, 172 .phy = 2, 173 .rx_qid = 4, 174 .rx_freeqid = 26, 175 .tx_qid = 23, 176 .tx_doneqid = 31 177 }, 178 [NPE_B] = { 179 .macbase = IXP425_MAC_B_HWBASE, 180 .miibase = IXP425_MAC_B_HWBASE, 181 .phy = 0, 182 .rx_qid = 4, 183 .rx_freeqid = 27, 184 .tx_qid = 24, 185 .tx_doneqid = 31 186 }, 187 [NPE_C] = { 188 .macbase = IXP425_MAC_C_HWBASE, 189 .miibase = IXP425_MAC_B_HWBASE, 190 .phy = 1, 191 .rx_qid = 12, 192 .rx_freeqid = 28, 193 .tx_qid = 25, 194 .tx_doneqid = 31 195 }, 196}; 197static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ 198 199static __inline uint32_t 200RD4(struct npe_softc *sc, bus_size_t off) 201{ 202 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); 203} 204 205static __inline void 206WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) 207{ 208 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); 209} 210 211#define NPE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 212#define NPE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 213#define NPE_LOCK_INIT(_sc) \ 214 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 215 MTX_NETWORK_LOCK, MTX_DEF) 216#define NPE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 217#define NPE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 218#define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 219 220static devclass_t npe_devclass; 221 222static int override_npeid(device_t, const char *resname, int *val); 223static int npe_activate(device_t dev); 224static void npe_deactivate(device_t dev); 225static int npe_ifmedia_update(struct ifnet *ifp); 226static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); 227static void npe_setmac(struct npe_softc *sc, u_char *eaddr); 228static void npe_getmac(struct npe_softc *sc, u_char *eaddr); 229static void npe_txdone(int qid, void *arg); 230static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, 231 struct mbuf *); 232static int npe_rxdone(int qid, void *arg); 233static void npeinit(void *); 234static void npestart_locked(struct ifnet *); 235static void npestart(struct ifnet *); 236static void npestop(struct npe_softc *); 237static void npewatchdog(struct npe_softc *); 238static int npeioctl(struct ifnet * ifp, u_long, caddr_t); 239 240static int npe_setrxqosentry(struct npe_softc *, int classix, 241 int trafclass, int qid); 242static int npe_setportaddress(struct npe_softc *, const uint8_t mac[]); 243static int npe_setfirewallmode(struct npe_softc *, int onoff); 244static int npe_updatestats(struct npe_softc *); 245#if 0 246static int npe_getstats(struct npe_softc *); 247static uint32_t npe_getimageid(struct npe_softc *); 248static int npe_setloopback(struct npe_softc *, int ena); 249#endif 250 251/* NB: all tx done processing goes through one queue */ 252static int tx_doneqid = -1; 253 254static SYSCTL_NODE(_hw, OID_AUTO, npe, CTLFLAG_RD, 0, 255 "IXP4XX NPE driver parameters"); 256 257static int npe_debug = 0; 258SYSCTL_INT(_hw_npe, OID_AUTO, debug, CTLFLAG_RWTUN, &npe_debug, 259 0, "IXP4XX NPE network interface debug msgs"); 260#define DPRINTF(sc, fmt, ...) do { \ 261 if (sc->sc_debug) device_printf(sc->sc_dev, fmt, __VA_ARGS__); \ 262} while (0) 263#define DPRINTFn(n, sc, fmt, ...) do { \ 264 if (sc->sc_debug >= n) device_printf(sc->sc_dev, fmt, __VA_ARGS__);\ 265} while (0) 266static int npe_tickinterval = 3; /* npe_tick frequency (secs) */ 267SYSCTL_INT(_hw_npe, OID_AUTO, tickinterval, CTLFLAG_RDTUN, &npe_tickinterval, 268 0, "periodic work interval (secs)"); 269 270static int npe_rxbuf = 64; /* # rx buffers to allocate */ 271SYSCTL_INT(_hw_npe, OID_AUTO, rxbuf, CTLFLAG_RDTUN, &npe_rxbuf, 272 0, "rx buffers allocated"); 273static int npe_txbuf = 128; /* # tx buffers to allocate */ 274SYSCTL_INT(_hw_npe, OID_AUTO, txbuf, CTLFLAG_RDTUN, &npe_txbuf, 275 0, "tx buffers allocated"); 276 277static int 278unit2npeid(int unit) 279{ 280 static const int npeidmap[2][3] = { 281 /* on 425 A is for HSS, B & C are for Ethernet */ 282 { NPE_B, NPE_C, -1 }, /* IXP425 */ 283 /* 435 only has A & C, order C then A */ 284 { NPE_C, NPE_A, -1 }, /* IXP435 */ 285 }; 286 /* XXX check feature register instead */ 287 return (unit < 3 ? npeidmap[ 288 (cpu_id() & CPU_ID_CPU_MASK) == CPU_ID_IXP435][unit] : -1); 289} 290 291static int 292npe_probe(device_t dev) 293{ 294 static const char *desc[NPE_MAX] = { 295 [NPE_A] = "IXP NPE-A", 296 [NPE_B] = "IXP NPE-B", 297 [NPE_C] = "IXP NPE-C" 298 }; 299 int unit = device_get_unit(dev); 300 int npeid; 301 302 if (unit > 2 || 303 (ixp4xx_read_feature_bits() & 304 (unit == 0 ? EXP_FCTRL_ETH0 : EXP_FCTRL_ETH1)) == 0) 305 return EINVAL; 306 307 npeid = -1; 308 if (!override_npeid(dev, "npeid", &npeid)) 309 npeid = unit2npeid(unit); 310 if (npeid == -1) { 311 device_printf(dev, "unit %d not supported\n", unit); 312 return EINVAL; 313 } 314 device_set_desc(dev, desc[npeid]); 315 return 0; 316} 317 318static int 319npe_attach(device_t dev) 320{ 321 struct npe_softc *sc = device_get_softc(dev); 322 struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); 323 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 324 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 325 struct ifnet *ifp; 326 int error; 327 u_char eaddr[6]; 328 329 sc->sc_dev = dev; 330 sc->sc_iot = sa->sc_iot; 331 NPE_LOCK_INIT(sc); 332 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 333 sc->sc_debug = npe_debug; 334 sc->sc_tickinterval = npe_tickinterval; 335 336 ifp = if_alloc(IFT_ETHER); 337 if (ifp == NULL) { 338 device_printf(dev, "cannot allocate ifnet\n"); 339 error = EIO; /* XXX */ 340 goto out; 341 } 342 /* NB: must be setup prior to invoking mii code */ 343 sc->sc_ifp = ifp; 344 345 error = npe_activate(dev); 346 if (error) { 347 device_printf(dev, "cannot activate npe\n"); 348 goto out; 349 } 350 351 npe_getmac(sc, eaddr); 352 353 ifp->if_softc = sc; 354 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 355 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 356 ifp->if_start = npestart; 357 ifp->if_ioctl = npeioctl; 358 ifp->if_init = npeinit; 359 IFQ_SET_MAXLEN(&ifp->if_snd, sc->txdma.nbuf - 1); 360 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 361 IFQ_SET_READY(&ifp->if_snd); 362 ifp->if_linkmib = &sc->mibdata; 363 ifp->if_linkmiblen = sizeof(sc->mibdata); 364 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_STATS; 365 /* device supports oversided vlan frames */ 366 ifp->if_capabilities |= IFCAP_VLAN_MTU; 367 ifp->if_capenable = ifp->if_capabilities; 368#ifdef DEVICE_POLLING 369 ifp->if_capabilities |= IFCAP_POLLING; 370#endif 371 372 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug", 373 CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); 374 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tickinterval", 375 CTLFLAG_RW, &sc->sc_tickinterval, 0, "periodic work frequency"); 376 SYSCTL_ADD_STRUCT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "stats", 377 CTLFLAG_RD, &sc->sc_totals, npestats, "onboard stats"); 378 379 ether_ifattach(ifp, eaddr); 380 return 0; 381out: 382 if (ifp != NULL) 383 if_free(ifp); 384 NPE_LOCK_DESTROY(sc); 385 npe_deactivate(dev); 386 return error; 387} 388 389static int 390npe_detach(device_t dev) 391{ 392 struct npe_softc *sc = device_get_softc(dev); 393 struct ifnet *ifp = sc->sc_ifp; 394 395#ifdef DEVICE_POLLING 396 if (ifp->if_capenable & IFCAP_POLLING) 397 ether_poll_deregister(ifp); 398#endif 399 npestop(sc); 400 if (ifp != NULL) { 401 ether_ifdetach(ifp); 402 if_free(ifp); 403 } 404 NPE_LOCK_DESTROY(sc); 405 npe_deactivate(dev); 406 return 0; 407} 408 409/* 410 * Compute and install the multicast filter. 411 */ 412static void 413npe_setmcast(struct npe_softc *sc) 414{ 415 struct ifnet *ifp = sc->sc_ifp; 416 uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; 417 int i; 418 419 if (ifp->if_flags & IFF_PROMISC) { 420 memset(mask, 0, ETHER_ADDR_LEN); 421 memset(addr, 0, ETHER_ADDR_LEN); 422 } else if (ifp->if_flags & IFF_ALLMULTI) { 423 static const uint8_t allmulti[ETHER_ADDR_LEN] = 424 { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; 425 memcpy(mask, allmulti, ETHER_ADDR_LEN); 426 memcpy(addr, allmulti, ETHER_ADDR_LEN); 427 } else { 428 uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; 429 struct ifmultiaddr *ifma; 430 const uint8_t *mac; 431 432 memset(clr, 0, ETHER_ADDR_LEN); 433 memset(set, 0xff, ETHER_ADDR_LEN); 434 435 if_maddr_rlock(ifp); 436 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 437 if (ifma->ifma_addr->sa_family != AF_LINK) 438 continue; 439 mac = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 440 for (i = 0; i < ETHER_ADDR_LEN; i++) { 441 clr[i] |= mac[i]; 442 set[i] &= mac[i]; 443 } 444 } 445 if_maddr_runlock(ifp); 446 447 for (i = 0; i < ETHER_ADDR_LEN; i++) { 448 mask[i] = set[i] | ~clr[i]; 449 addr[i] = set[i]; 450 } 451 } 452 453 /* 454 * Write the mask and address registers. 455 */ 456 for (i = 0; i < ETHER_ADDR_LEN; i++) { 457 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); 458 WR4(sc, NPE_MAC_ADDR(i), addr[i]); 459 } 460} 461 462static void 463npe_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 464{ 465 struct npe_softc *sc; 466 467 if (error != 0) 468 return; 469 sc = (struct npe_softc *)arg; 470 sc->buf_phys = segs[0].ds_addr; 471} 472 473static int 474npe_dma_setup(struct npe_softc *sc, struct npedma *dma, 475 const char *name, int nbuf, int maxseg) 476{ 477 int error, i; 478 479 memset(dma, 0, sizeof(*dma)); 480 481 dma->name = name; 482 dma->nbuf = nbuf; 483 484 /* DMA tag for mapped mbufs */ 485 error = bus_dma_tag_create(ixp425_softc->sc_dmat, 1, 0, 486 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 487 MCLBYTES, maxseg, MCLBYTES, 0, 488 busdma_lock_mutex, &sc->sc_mtx, &dma->mtag); 489 if (error != 0) { 490 device_printf(sc->sc_dev, "unable to create %s mbuf dma tag, " 491 "error %u\n", dma->name, error); 492 return error; 493 } 494 495 /* DMA tag and map for the NPE buffers */ 496 error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 497 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 498 nbuf * sizeof(struct npehwbuf), 1, 499 nbuf * sizeof(struct npehwbuf), 0, 500 busdma_lock_mutex, &sc->sc_mtx, &dma->buf_tag); 501 if (error != 0) { 502 device_printf(sc->sc_dev, 503 "unable to create %s npebuf dma tag, error %u\n", 504 dma->name, error); 505 return error; 506 } 507 if (bus_dmamem_alloc(dma->buf_tag, (void **)&dma->hwbuf, 508 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 509 &dma->buf_map) != 0) { 510 device_printf(sc->sc_dev, 511 "unable to allocate memory for %s h/w buffers, error %u\n", 512 dma->name, error); 513 return error; 514 } 515 /* XXX M_TEMP */ 516 dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); 517 if (dma->buf == NULL) { 518 device_printf(sc->sc_dev, 519 "unable to allocate memory for %s s/w buffers\n", 520 dma->name); 521 return error; 522 } 523 if (bus_dmamap_load(dma->buf_tag, dma->buf_map, 524 dma->hwbuf, nbuf*sizeof(struct npehwbuf), npe_getaddr, sc, 0) != 0) { 525 device_printf(sc->sc_dev, 526 "unable to map memory for %s h/w buffers, error %u\n", 527 dma->name, error); 528 return error; 529 } 530 dma->buf_phys = sc->buf_phys; 531 for (i = 0; i < dma->nbuf; i++) { 532 struct npebuf *npe = &dma->buf[i]; 533 struct npehwbuf *hw = &dma->hwbuf[i]; 534 535 /* calculate offset to shared area */ 536 npe->ix_neaddr = dma->buf_phys + 537 ((uintptr_t)hw - (uintptr_t)dma->hwbuf); 538 KASSERT((npe->ix_neaddr & 0x1f) == 0, 539 ("ixpbuf misaligned, PA 0x%x", npe->ix_neaddr)); 540 error = bus_dmamap_create(dma->mtag, BUS_DMA_NOWAIT, 541 &npe->ix_map); 542 if (error != 0) { 543 device_printf(sc->sc_dev, 544 "unable to create dmamap for %s buffer %u, " 545 "error %u\n", dma->name, i, error); 546 return error; 547 } 548 npe->ix_hw = hw; 549 } 550 bus_dmamap_sync(dma->buf_tag, dma->buf_map, BUS_DMASYNC_PREWRITE); 551 return 0; 552} 553 554static void 555npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) 556{ 557 int i; 558 559 if (dma->hwbuf != NULL) { 560 for (i = 0; i < dma->nbuf; i++) { 561 struct npebuf *npe = &dma->buf[i]; 562 bus_dmamap_destroy(dma->mtag, npe->ix_map); 563 } 564 bus_dmamap_unload(dma->buf_tag, dma->buf_map); 565 bus_dmamem_free(dma->buf_tag, dma->hwbuf, dma->buf_map); 566 } 567 if (dma->buf != NULL) 568 free(dma->buf, M_TEMP); 569 if (dma->buf_tag) 570 bus_dma_tag_destroy(dma->buf_tag); 571 if (dma->mtag) 572 bus_dma_tag_destroy(dma->mtag); 573 memset(dma, 0, sizeof(*dma)); 574} 575 576static int 577override_addr(device_t dev, const char *resname, int *base) 578{ 579 int unit = device_get_unit(dev); 580 const char *resval; 581 582 /* XXX warn for wrong hint type */ 583 if (resource_string_value("npe", unit, resname, &resval) != 0) 584 return 0; 585 switch (resval[0]) { 586 case 'A': 587 *base = IXP435_MAC_A_HWBASE; 588 break; 589 case 'B': 590 *base = IXP425_MAC_B_HWBASE; 591 break; 592 case 'C': 593 *base = IXP425_MAC_C_HWBASE; 594 break; 595 default: 596 device_printf(dev, "Warning, bad value %s for " 597 "npe.%d.%s ignored\n", resval, unit, resname); 598 return 0; 599 } 600 if (bootverbose) 601 device_printf(dev, "using npe.%d.%s=%s override\n", 602 unit, resname, resval); 603 return 1; 604} 605 606static int 607override_npeid(device_t dev, const char *resname, int *npeid) 608{ 609 int unit = device_get_unit(dev); 610 const char *resval; 611 612 /* XXX warn for wrong hint type */ 613 if (resource_string_value("npe", unit, resname, &resval) != 0) 614 return 0; 615 switch (resval[0]) { 616 case 'A': *npeid = NPE_A; break; 617 case 'B': *npeid = NPE_B; break; 618 case 'C': *npeid = NPE_C; break; 619 default: 620 device_printf(dev, "Warning, bad value %s for " 621 "npe.%d.%s ignored\n", resval, unit, resname); 622 return 0; 623 } 624 if (bootverbose) 625 device_printf(dev, "using npe.%d.%s=%s override\n", 626 unit, resname, resval); 627 return 1; 628} 629 630static int 631override_unit(device_t dev, const char *resname, int *val, int min, int max) 632{ 633 int unit = device_get_unit(dev); 634 int resval; 635 636 if (resource_int_value("npe", unit, resname, &resval) != 0) 637 return 0; 638 if (!(min <= resval && resval <= max)) { 639 device_printf(dev, "Warning, bad value %d for npe.%d.%s " 640 "ignored (value must be [%d-%d])\n", resval, unit, 641 resname, min, max); 642 return 0; 643 } 644 if (bootverbose) 645 device_printf(dev, "using npe.%d.%s=%d override\n", 646 unit, resname, resval); 647 *val = resval; 648 return 1; 649} 650 651static void 652npe_mac_reset(struct npe_softc *sc) 653{ 654 /* 655 * Reset MAC core. 656 */ 657 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 658 DELAY(NPE_MAC_RESET_DELAY); 659 /* configure MAC to generate MDC clock */ 660 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 661} 662 663static int 664npe_activate(device_t dev) 665{ 666 struct npe_softc *sc = device_get_softc(dev); 667 int error, i, macbase, miibase, phy; 668 669 /* 670 * Setup NEP ID, MAC, and MII bindings. We allow override 671 * via hints to handle unexpected board configs. 672 */ 673 if (!override_npeid(dev, "npeid", &sc->sc_npeid)) 674 sc->sc_npeid = unit2npeid(device_get_unit(dev)); 675 sc->sc_npe = ixpnpe_attach(dev, sc->sc_npeid); 676 if (sc->sc_npe == NULL) { 677 device_printf(dev, "cannot attach ixpnpe\n"); 678 return EIO; /* XXX */ 679 } 680 681 /* MAC */ 682 if (!override_addr(dev, "mac", &macbase)) 683 macbase = npeconfig[sc->sc_npeid].macbase; 684 if (bootverbose) 685 device_printf(sc->sc_dev, "MAC at 0x%x\n", macbase); 686 if (bus_space_map(sc->sc_iot, macbase, IXP425_REG_SIZE, 0, &sc->sc_ioh)) { 687 device_printf(dev, "cannot map mac registers 0x%x:0x%x\n", 688 macbase, IXP425_REG_SIZE); 689 return ENOMEM; 690 } 691 692 /* PHY */ 693 if (!override_unit(dev, "phy", &phy, 0, MII_NPHY - 1)) 694 phy = npeconfig[sc->sc_npeid].phy; 695 if (!override_addr(dev, "mii", &miibase)) 696 miibase = npeconfig[sc->sc_npeid].miibase; 697 if (bootverbose) 698 device_printf(sc->sc_dev, "MII at 0x%x\n", miibase); 699 if (miibase != macbase) { 700 /* 701 * PHY is mapped through a different MAC, setup an 702 * additional mapping for frobbing the PHY registers. 703 */ 704 if (bus_space_map(sc->sc_iot, miibase, IXP425_REG_SIZE, 0, &sc->sc_miih)) { 705 device_printf(dev, 706 "cannot map MII registers 0x%x:0x%x\n", 707 miibase, IXP425_REG_SIZE); 708 return ENOMEM; 709 } 710 } else 711 sc->sc_miih = sc->sc_ioh; 712 713 /* 714 * Load NPE firmware and start it running. 715 */ 716 error = ixpnpe_init(sc->sc_npe); 717 if (error != 0) { 718 device_printf(dev, "cannot init NPE (error %d)\n", error); 719 return error; 720 } 721 722 /* attach PHY */ 723 error = mii_attach(dev, &sc->sc_mii, sc->sc_ifp, npe_ifmedia_update, 724 npe_ifmedia_status, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 725 if (error != 0) { 726 device_printf(dev, "attaching PHYs failed\n"); 727 return error; 728 } 729 730 error = npe_dma_setup(sc, &sc->txdma, "tx", npe_txbuf, NPE_MAXSEG); 731 if (error != 0) 732 return error; 733 error = npe_dma_setup(sc, &sc->rxdma, "rx", npe_rxbuf, 1); 734 if (error != 0) 735 return error; 736 737 /* setup statistics block */ 738 error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, 739 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 740 sizeof(struct npestats), 1, sizeof(struct npestats), 0, 741 busdma_lock_mutex, &sc->sc_mtx, &sc->sc_stats_tag); 742 if (error != 0) { 743 device_printf(sc->sc_dev, "unable to create stats tag, " 744 "error %u\n", error); 745 return error; 746 } 747 if (bus_dmamem_alloc(sc->sc_stats_tag, (void **)&sc->sc_stats, 748 BUS_DMA_NOWAIT, &sc->sc_stats_map) != 0) { 749 device_printf(sc->sc_dev, 750 "unable to allocate memory for stats block, error %u\n", 751 error); 752 return error; 753 } 754 if (bus_dmamap_load(sc->sc_stats_tag, sc->sc_stats_map, 755 sc->sc_stats, sizeof(struct npestats), npe_getaddr, sc, 0) != 0) { 756 device_printf(sc->sc_dev, 757 "unable to load memory for stats block, error %u\n", 758 error); 759 return error; 760 } 761 sc->sc_stats_phys = sc->buf_phys; 762 763 /* 764 * Setup h/w rx/tx queues. There are four q's: 765 * rx inbound q of rx'd frames 766 * rx_free pool of ixpbuf's for receiving frames 767 * tx outbound q of frames to send 768 * tx_done q of tx frames that have been processed 769 * 770 * The NPE handles the actual tx/rx process and the q manager 771 * handles the queues. The driver just writes entries to the 772 * q manager mailbox's and gets callbacks when there are rx'd 773 * frames to process or tx'd frames to reap. These callbacks 774 * are controlled by the q configurations; e.g. we get a 775 * callback when tx_done has 2 or more frames to process and 776 * when the rx q has at least one frame. These setings can 777 * changed at the time the q is configured. 778 */ 779 sc->rx_qid = npeconfig[sc->sc_npeid].rx_qid; 780 ixpqmgr_qconfig(sc->rx_qid, npe_rxbuf, 0, 1, 781 IX_QMGR_Q_SOURCE_ID_NOT_E, (qconfig_hand_t *)npe_rxdone, sc); 782 sc->rx_freeqid = npeconfig[sc->sc_npeid].rx_freeqid; 783 ixpqmgr_qconfig(sc->rx_freeqid, npe_rxbuf, 0, npe_rxbuf/2, 0, NULL, sc); 784 /* 785 * Setup the NPE to direct all traffic to rx_qid. 786 * When QoS is enabled in the firmware there are 787 * 8 traffic classes; otherwise just 4. 788 */ 789 for (i = 0; i < 8; i++) 790 npe_setrxqosentry(sc, i, 0, sc->rx_qid); 791 792 /* disable firewall mode just in case (should be off) */ 793 npe_setfirewallmode(sc, 0); 794 795 sc->tx_qid = npeconfig[sc->sc_npeid].tx_qid; 796 sc->tx_doneqid = npeconfig[sc->sc_npeid].tx_doneqid; 797 ixpqmgr_qconfig(sc->tx_qid, npe_txbuf, 0, npe_txbuf, 0, NULL, sc); 798 if (tx_doneqid == -1) { 799 ixpqmgr_qconfig(sc->tx_doneqid, npe_txbuf, 0, 2, 800 IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); 801 tx_doneqid = sc->tx_doneqid; 802 } 803 804 KASSERT(npes[sc->sc_npeid] == NULL, 805 ("npe %u already setup", sc->sc_npeid)); 806 npes[sc->sc_npeid] = sc; 807 808 return 0; 809} 810 811static void 812npe_deactivate(device_t dev) 813{ 814 struct npe_softc *sc = device_get_softc(dev); 815 816 npes[sc->sc_npeid] = NULL; 817 818 /* XXX disable q's */ 819 if (sc->sc_npe != NULL) { 820 ixpnpe_stop(sc->sc_npe); 821 ixpnpe_detach(sc->sc_npe); 822 } 823 if (sc->sc_stats != NULL) { 824 bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); 825 bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, 826 sc->sc_stats_map); 827 } 828 if (sc->sc_stats_tag != NULL) 829 bus_dma_tag_destroy(sc->sc_stats_tag); 830 npe_dma_destroy(sc, &sc->txdma); 831 npe_dma_destroy(sc, &sc->rxdma); 832 bus_generic_detach(sc->sc_dev); 833 if (sc->sc_mii != NULL) 834 device_delete_child(sc->sc_dev, sc->sc_mii); 835} 836 837/* 838 * Change media according to request. 839 */ 840static int 841npe_ifmedia_update(struct ifnet *ifp) 842{ 843 struct npe_softc *sc = ifp->if_softc; 844 struct mii_data *mii; 845 846 mii = device_get_softc(sc->sc_mii); 847 NPE_LOCK(sc); 848 mii_mediachg(mii); 849 /* XXX push state ourself? */ 850 NPE_UNLOCK(sc); 851 return (0); 852} 853 854/* 855 * Notify the world which media we're using. 856 */ 857static void 858npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 859{ 860 struct npe_softc *sc = ifp->if_softc; 861 struct mii_data *mii; 862 863 mii = device_get_softc(sc->sc_mii); 864 NPE_LOCK(sc); 865 mii_pollstat(mii); 866 ifmr->ifm_active = mii->mii_media_active; 867 ifmr->ifm_status = mii->mii_media_status; 868 NPE_UNLOCK(sc); 869} 870 871static void 872npe_addstats(struct npe_softc *sc) 873{ 874#define NPEADD(x) sc->sc_totals.x += be32toh(ns->x) 875#define MIBADD(x) do { sc->mibdata.x += be32toh(ns->x); NPEADD(x); } while (0) 876 struct ifnet *ifp = sc->sc_ifp; 877 struct npestats *ns = sc->sc_stats; 878 879 MIBADD(dot3StatsAlignmentErrors); 880 MIBADD(dot3StatsFCSErrors); 881 MIBADD(dot3StatsInternalMacReceiveErrors); 882 NPEADD(RxOverrunDiscards); 883 NPEADD(RxLearnedEntryDiscards); 884 NPEADD(RxLargeFramesDiscards); 885 NPEADD(RxSTPBlockedDiscards); 886 NPEADD(RxVLANTypeFilterDiscards); 887 NPEADD(RxVLANIdFilterDiscards); 888 NPEADD(RxInvalidSourceDiscards); 889 NPEADD(RxBlackListDiscards); 890 NPEADD(RxWhiteListDiscards); 891 NPEADD(RxUnderflowEntryDiscards); 892 MIBADD(dot3StatsSingleCollisionFrames); 893 MIBADD(dot3StatsMultipleCollisionFrames); 894 MIBADD(dot3StatsDeferredTransmissions); 895 MIBADD(dot3StatsLateCollisions); 896 MIBADD(dot3StatsExcessiveCollisions); 897 MIBADD(dot3StatsInternalMacTransmitErrors); 898 MIBADD(dot3StatsCarrierSenseErrors); 899 NPEADD(TxLargeFrameDiscards); 900 NPEADD(TxVLANIdFilterDiscards); 901 902 sc->mibdata.dot3StatsFrameTooLongs += 903 be32toh(ns->RxLargeFramesDiscards) 904 + be32toh(ns->TxLargeFrameDiscards); 905 sc->mibdata.dot3StatsMissedFrames += 906 be32toh(ns->RxOverrunDiscards) 907 + be32toh(ns->RxUnderflowEntryDiscards); 908 909 ifp->if_oerrors += 910 be32toh(ns->dot3StatsInternalMacTransmitErrors) 911 + be32toh(ns->dot3StatsCarrierSenseErrors) 912 + be32toh(ns->TxVLANIdFilterDiscards) 913 ; 914 ifp->if_ierrors += be32toh(ns->dot3StatsFCSErrors) 915 + be32toh(ns->dot3StatsInternalMacReceiveErrors) 916 + be32toh(ns->RxOverrunDiscards) 917 + be32toh(ns->RxUnderflowEntryDiscards) 918 ; 919 ifp->if_collisions += 920 be32toh(ns->dot3StatsSingleCollisionFrames) 921 + be32toh(ns->dot3StatsMultipleCollisionFrames) 922 ; 923#undef NPEADD 924#undef MIBADD 925} 926 927static void 928npe_tick(void *xsc) 929{ 930#define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) 931 struct npe_softc *sc = xsc; 932 struct mii_data *mii = device_get_softc(sc->sc_mii); 933 uint32_t msg[2]; 934 935 NPE_ASSERT_LOCKED(sc); 936 937 /* 938 * NB: to avoid sleeping with the softc lock held we 939 * split the NPE msg processing into two parts. The 940 * request for statistics is sent w/o waiting for a 941 * reply and then on the next tick we retrieve the 942 * results. This works because npe_tick is the only 943 * code that talks via the mailbox's (except at setup). 944 * This likely can be handled better. 945 */ 946 if (ixpnpe_recvmsg_async(sc->sc_npe, msg) == 0 && msg[0] == ACK) { 947 bus_dmamap_sync(sc->sc_stats_tag, sc->sc_stats_map, 948 BUS_DMASYNC_POSTREAD); 949 npe_addstats(sc); 950 } 951 npe_updatestats(sc); 952 mii_tick(mii); 953 954 npewatchdog(sc); 955 956 /* schedule next poll */ 957 callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 958#undef ACK 959} 960 961static void 962npe_setmac(struct npe_softc *sc, u_char *eaddr) 963{ 964 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); 965 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); 966 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); 967 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); 968 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); 969 WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); 970} 971 972static void 973npe_getmac(struct npe_softc *sc, u_char *eaddr) 974{ 975 /* NB: the unicast address appears to be loaded from EEPROM on reset */ 976 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 977 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 978 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 979 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 980 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 981 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 982} 983 984struct txdone { 985 struct npebuf *head; 986 struct npebuf **tail; 987 int count; 988}; 989 990static __inline void 991npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) 992{ 993 struct ifnet *ifp = sc->sc_ifp; 994 995 NPE_LOCK(sc); 996 *td->tail = sc->tx_free; 997 sc->tx_free = td->head; 998 /* 999 * We're no longer busy, so clear the busy flag and call the 1000 * start routine to xmit more packets. 1001 */ 1002 ifp->if_opackets += td->count; 1003 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1004 sc->npe_watchdog_timer = 0; 1005 npestart_locked(ifp); 1006 NPE_UNLOCK(sc); 1007} 1008 1009/* 1010 * Q manager callback on tx done queue. Reap mbufs 1011 * and return tx buffers to the free list. Finally 1012 * restart output. Note the microcode has only one 1013 * txdone q wired into it so we must use the NPE ID 1014 * returned with each npehwbuf to decide where to 1015 * send buffers. 1016 */ 1017static void 1018npe_txdone(int qid, void *arg) 1019{ 1020#define P2V(a, dma) \ 1021 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1022 struct npe_softc *sc0 = arg; 1023 struct npe_softc *sc; 1024 struct npebuf *npe; 1025 struct txdone *td, q[NPE_MAX]; 1026 uint32_t entry; 1027 1028 q[NPE_A].tail = &q[NPE_A].head; q[NPE_A].count = 0; 1029 q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; 1030 q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; 1031 /* XXX max # at a time? */ 1032 while (ixpqmgr_qread(qid, &entry) == 0) { 1033 DPRINTF(sc0, "%s: entry 0x%x NPE %u port %u\n", 1034 __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); 1035 1036 sc = npes[NPE_QM_Q_NPE(entry)]; 1037 npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); 1038 m_freem(npe->ix_m); 1039 npe->ix_m = NULL; 1040 1041 td = &q[NPE_QM_Q_NPE(entry)]; 1042 *td->tail = npe; 1043 td->tail = &npe->ix_next; 1044 td->count++; 1045 } 1046 1047 if (q[NPE_A].count) 1048 npe_txdone_finish(npes[NPE_A], &q[NPE_A]); 1049 if (q[NPE_B].count) 1050 npe_txdone_finish(npes[NPE_B], &q[NPE_B]); 1051 if (q[NPE_C].count) 1052 npe_txdone_finish(npes[NPE_C], &q[NPE_C]); 1053#undef P2V 1054} 1055 1056static int 1057npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) 1058{ 1059 bus_dma_segment_t segs[1]; 1060 struct npedma *dma = &sc->rxdma; 1061 struct npehwbuf *hw; 1062 int error, nseg; 1063 1064 if (m == NULL) { 1065 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1066 if (m == NULL) 1067 return ENOBUFS; 1068 } 1069 KASSERT(m->m_ext.ext_size >= 1536 + ETHER_ALIGN, 1070 ("ext_size %d", m->m_ext.ext_size)); 1071 m->m_pkthdr.len = m->m_len = 1536; 1072 /* backload payload and align ip hdr */ 1073 m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN)); 1074 bus_dmamap_unload(dma->mtag, npe->ix_map); 1075 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, m, 1076 segs, &nseg, 0); 1077 if (error != 0) { 1078 m_freem(m); 1079 return error; 1080 } 1081 hw = npe->ix_hw; 1082 hw->ix_ne[0].data = htobe32(segs[0].ds_addr); 1083 /* NB: NPE requires length be a multiple of 64 */ 1084 /* NB: buffer length is shifted in word */ 1085 hw->ix_ne[0].len = htobe32(segs[0].ds_len << 16); 1086 hw->ix_ne[0].next = 0; 1087 bus_dmamap_sync(dma->buf_tag, dma->buf_map, 1088 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1089 npe->ix_m = m; 1090 /* Flush the memory in the mbuf */ 1091 bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREREAD); 1092 return 0; 1093} 1094 1095/* 1096 * RX q processing for a specific NPE. Claim entries 1097 * from the hardware queue and pass the frames up the 1098 * stack. Pass the rx buffers to the free list. 1099 */ 1100static int 1101npe_rxdone(int qid, void *arg) 1102{ 1103#define P2V(a, dma) \ 1104 &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] 1105 struct npe_softc *sc = arg; 1106 struct npedma *dma = &sc->rxdma; 1107 uint32_t entry; 1108 int rx_npkts = 0; 1109 1110 while (ixpqmgr_qread(qid, &entry) == 0) { 1111 struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); 1112 struct mbuf *m; 1113 1114 bus_dmamap_sync(dma->buf_tag, dma->buf_map, 1115 BUS_DMASYNC_POSTREAD); 1116 DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", 1117 __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); 1118 /* 1119 * Allocate a new mbuf to replenish the rx buffer. 1120 * If doing so fails we drop the rx'd frame so we 1121 * can reuse the previous mbuf. When we're able to 1122 * allocate a new mbuf dispatch the mbuf w/ rx'd 1123 * data up the stack and replace it with the newly 1124 * allocated one. 1125 */ 1126 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1127 if (m != NULL) { 1128 struct mbuf *mrx = npe->ix_m; 1129 struct npehwbuf *hw = npe->ix_hw; 1130 struct ifnet *ifp = sc->sc_ifp; 1131 1132 /* Flush mbuf memory for rx'd data */ 1133 bus_dmamap_sync(dma->mtag, npe->ix_map, 1134 BUS_DMASYNC_POSTREAD); 1135 1136 /* set m_len etc. per rx frame size */ 1137 mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; 1138 mrx->m_pkthdr.len = mrx->m_len; 1139 mrx->m_pkthdr.rcvif = ifp; 1140 1141 ifp->if_ipackets++; 1142 ifp->if_input(ifp, mrx); 1143 rx_npkts++; 1144 } else { 1145 /* discard frame and re-use mbuf */ 1146 m = npe->ix_m; 1147 } 1148 if (npe_rxbuf_init(sc, npe, m) == 0) { 1149 /* return npe buf to rx free list */ 1150 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1151 } else { 1152 /* XXX should not happen */ 1153 } 1154 } 1155 return rx_npkts; 1156#undef P2V 1157} 1158 1159#ifdef DEVICE_POLLING 1160static int 1161npe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1162{ 1163 struct npe_softc *sc = ifp->if_softc; 1164 int rx_npkts = 0; 1165 1166 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1167 rx_npkts = npe_rxdone(sc->rx_qid, sc); 1168 npe_txdone(sc->tx_doneqid, sc); /* XXX polls both NPE's */ 1169 } 1170 return rx_npkts; 1171} 1172#endif /* DEVICE_POLLING */ 1173 1174static void 1175npe_startxmit(struct npe_softc *sc) 1176{ 1177 struct npedma *dma = &sc->txdma; 1178 int i; 1179 1180 NPE_ASSERT_LOCKED(sc); 1181 sc->tx_free = NULL; 1182 for (i = 0; i < dma->nbuf; i++) { 1183 struct npebuf *npe = &dma->buf[i]; 1184 if (npe->ix_m != NULL) { 1185 /* NB: should not happen */ 1186 device_printf(sc->sc_dev, 1187 "%s: free mbuf at entry %u\n", __func__, i); 1188 m_freem(npe->ix_m); 1189 } 1190 npe->ix_m = NULL; 1191 npe->ix_next = sc->tx_free; 1192 sc->tx_free = npe; 1193 } 1194} 1195 1196static void 1197npe_startrecv(struct npe_softc *sc) 1198{ 1199 struct npedma *dma = &sc->rxdma; 1200 struct npebuf *npe; 1201 int i; 1202 1203 NPE_ASSERT_LOCKED(sc); 1204 for (i = 0; i < dma->nbuf; i++) { 1205 npe = &dma->buf[i]; 1206 npe_rxbuf_init(sc, npe, npe->ix_m); 1207 /* set npe buf on rx free list */ 1208 ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); 1209 } 1210} 1211 1212/* 1213 * Reset and initialize the chip 1214 */ 1215static void 1216npeinit_locked(void *xsc) 1217{ 1218 struct npe_softc *sc = xsc; 1219 struct ifnet *ifp = sc->sc_ifp; 1220 1221 NPE_ASSERT_LOCKED(sc); 1222if (ifp->if_drv_flags & IFF_DRV_RUNNING) return;/*XXX*/ 1223 1224 /* 1225 * Reset MAC core. 1226 */ 1227 npe_mac_reset(sc); 1228 1229 /* disable transmitter and reciver in the MAC */ 1230 WR4(sc, NPE_MAC_RX_CNTRL1, 1231 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1232 WR4(sc, NPE_MAC_TX_CNTRL1, 1233 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1234 1235 /* 1236 * Set the MAC core registers. 1237 */ 1238 WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ 1239 WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ 1240 WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ 1241 /* thresholds determined by NPE firmware FS */ 1242 WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); 1243 WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); 1244 WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */ 1245 WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ 1246 WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ 1247 WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ 1248 WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ 1249 WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */ 1250 1251 WR4(sc, NPE_MAC_TX_CNTRL1, 1252 NPE_TX_CNTRL1_RETRY /* retry failed xmits */ 1253 | NPE_TX_CNTRL1_FCS_EN /* append FCS */ 1254 | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ 1255 | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ 1256 /* XXX pad strip? */ 1257 /* ena pause frame handling */ 1258 WR4(sc, NPE_MAC_RX_CNTRL1, NPE_RX_CNTRL1_PAUSE_EN); 1259 WR4(sc, NPE_MAC_RX_CNTRL2, 0); 1260 1261 npe_setmac(sc, IF_LLADDR(ifp)); 1262 npe_setportaddress(sc, IF_LLADDR(ifp)); 1263 npe_setmcast(sc); 1264 1265 npe_startxmit(sc); 1266 npe_startrecv(sc); 1267 1268 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1269 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1270 sc->npe_watchdog_timer = 0; /* just in case */ 1271 1272 /* enable transmitter and reciver in the MAC */ 1273 WR4(sc, NPE_MAC_RX_CNTRL1, 1274 RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); 1275 WR4(sc, NPE_MAC_TX_CNTRL1, 1276 RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); 1277 1278 callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); 1279} 1280 1281static void 1282npeinit(void *xsc) 1283{ 1284 struct npe_softc *sc = xsc; 1285 NPE_LOCK(sc); 1286 npeinit_locked(sc); 1287 NPE_UNLOCK(sc); 1288} 1289 1290/* 1291 * Dequeue packets and place on the h/w transmit queue. 1292 */ 1293static void 1294npestart_locked(struct ifnet *ifp) 1295{ 1296 struct npe_softc *sc = ifp->if_softc; 1297 struct npebuf *npe; 1298 struct npehwbuf *hw; 1299 struct mbuf *m, *n; 1300 struct npedma *dma = &sc->txdma; 1301 bus_dma_segment_t segs[NPE_MAXSEG]; 1302 int nseg, len, error, i; 1303 uint32_t next; 1304 1305 NPE_ASSERT_LOCKED(sc); 1306 /* XXX can this happen? */ 1307 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1308 return; 1309 1310 while (sc->tx_free != NULL) { 1311 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1312 if (m == NULL) { 1313 /* XXX? */ 1314 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1315 return; 1316 } 1317 npe = sc->tx_free; 1318 bus_dmamap_unload(dma->mtag, npe->ix_map); 1319 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1320 m, segs, &nseg, 0); 1321 if (error == EFBIG) { 1322 n = m_collapse(m, M_NOWAIT, NPE_MAXSEG); 1323 if (n == NULL) { 1324 if_printf(ifp, "%s: too many fragments %u\n", 1325 __func__, nseg); 1326 m_freem(m); 1327 return; /* XXX? */ 1328 } 1329 m = n; 1330 error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, 1331 m, segs, &nseg, 0); 1332 } 1333 if (error != 0 || nseg == 0) { 1334 if_printf(ifp, "%s: error %u nseg %u\n", 1335 __func__, error, nseg); 1336 m_freem(m); 1337 return; /* XXX? */ 1338 } 1339 sc->tx_free = npe->ix_next; 1340 1341 bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREWRITE); 1342 1343 /* 1344 * Tap off here if there is a bpf listener. 1345 */ 1346 BPF_MTAP(ifp, m); 1347 1348 npe->ix_m = m; 1349 hw = npe->ix_hw; 1350 len = m->m_pkthdr.len; 1351 next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); 1352 for (i = 0; i < nseg; i++) { 1353 hw->ix_ne[i].data = htobe32(segs[i].ds_addr); 1354 hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); 1355 hw->ix_ne[i].next = htobe32(next); 1356 1357 len = 0; /* zero for segments > 1 */ 1358 next += sizeof(hw->ix_ne[0]); 1359 } 1360 hw->ix_ne[i-1].next = 0; /* zero last in chain */ 1361 bus_dmamap_sync(dma->buf_tag, dma->buf_map, 1362 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1363 1364 DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", 1365 __func__, sc->tx_qid, npe->ix_neaddr, 1366 hw->ix_ne[0].data, hw->ix_ne[0].len); 1367 /* stick it on the tx q */ 1368 /* XXX add vlan priority */ 1369 ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); 1370 1371 sc->npe_watchdog_timer = 5; 1372 } 1373 if (sc->tx_free == NULL) 1374 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1375} 1376 1377void 1378npestart(struct ifnet *ifp) 1379{ 1380 struct npe_softc *sc = ifp->if_softc; 1381 NPE_LOCK(sc); 1382 npestart_locked(ifp); 1383 NPE_UNLOCK(sc); 1384} 1385 1386static void 1387npe_stopxmit(struct npe_softc *sc) 1388{ 1389 struct npedma *dma = &sc->txdma; 1390 int i; 1391 1392 NPE_ASSERT_LOCKED(sc); 1393 1394 /* XXX qmgr */ 1395 for (i = 0; i < dma->nbuf; i++) { 1396 struct npebuf *npe = &dma->buf[i]; 1397 1398 if (npe->ix_m != NULL) { 1399 bus_dmamap_unload(dma->mtag, npe->ix_map); 1400 m_freem(npe->ix_m); 1401 npe->ix_m = NULL; 1402 } 1403 } 1404} 1405 1406static void 1407npe_stoprecv(struct npe_softc *sc) 1408{ 1409 struct npedma *dma = &sc->rxdma; 1410 int i; 1411 1412 NPE_ASSERT_LOCKED(sc); 1413 1414 /* XXX qmgr */ 1415 for (i = 0; i < dma->nbuf; i++) { 1416 struct npebuf *npe = &dma->buf[i]; 1417 1418 if (npe->ix_m != NULL) { 1419 bus_dmamap_unload(dma->mtag, npe->ix_map); 1420 m_freem(npe->ix_m); 1421 npe->ix_m = NULL; 1422 } 1423 } 1424} 1425 1426/* 1427 * Turn off interrupts, and stop the nic. 1428 */ 1429void 1430npestop(struct npe_softc *sc) 1431{ 1432 struct ifnet *ifp = sc->sc_ifp; 1433 1434 /* disable transmitter and reciver in the MAC */ 1435 WR4(sc, NPE_MAC_RX_CNTRL1, 1436 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1437 WR4(sc, NPE_MAC_TX_CNTRL1, 1438 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1439 1440 sc->npe_watchdog_timer = 0; 1441 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1442 1443 callout_stop(&sc->tick_ch); 1444 1445 npe_stopxmit(sc); 1446 npe_stoprecv(sc); 1447 /* XXX go into loopback & drain q's? */ 1448 /* XXX but beware of disabling tx above */ 1449 1450 /* 1451 * The MAC core rx/tx disable may leave the MAC hardware in an 1452 * unpredictable state. A hw reset is executed before resetting 1453 * all the MAC parameters to a known value. 1454 */ 1455 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); 1456 DELAY(NPE_MAC_RESET_DELAY); 1457 WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); 1458 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); 1459} 1460 1461void 1462npewatchdog(struct npe_softc *sc) 1463{ 1464 NPE_ASSERT_LOCKED(sc); 1465 1466 if (sc->npe_watchdog_timer == 0 || --sc->npe_watchdog_timer != 0) 1467 return; 1468 1469 device_printf(sc->sc_dev, "watchdog timeout\n"); 1470 sc->sc_ifp->if_oerrors++; 1471 1472 npeinit_locked(sc); 1473} 1474 1475static int 1476npeioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1477{ 1478 struct npe_softc *sc = ifp->if_softc; 1479 struct mii_data *mii; 1480 struct ifreq *ifr = (struct ifreq *)data; 1481 int error = 0; 1482#ifdef DEVICE_POLLING 1483 int mask; 1484#endif 1485 1486 switch (cmd) { 1487 case SIOCSIFFLAGS: 1488 NPE_LOCK(sc); 1489 if ((ifp->if_flags & IFF_UP) == 0 && 1490 ifp->if_drv_flags & IFF_DRV_RUNNING) { 1491 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1492 npestop(sc); 1493 } else { 1494 /* reinitialize card on any parameter change */ 1495 npeinit_locked(sc); 1496 } 1497 NPE_UNLOCK(sc); 1498 break; 1499 1500 case SIOCADDMULTI: 1501 case SIOCDELMULTI: 1502 /* update multicast filter list. */ 1503 NPE_LOCK(sc); 1504 npe_setmcast(sc); 1505 NPE_UNLOCK(sc); 1506 error = 0; 1507 break; 1508 1509 case SIOCSIFMEDIA: 1510 case SIOCGIFMEDIA: 1511 mii = device_get_softc(sc->sc_mii); 1512 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1513 break; 1514 1515#ifdef DEVICE_POLLING 1516 case SIOCSIFCAP: 1517 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1518 if (mask & IFCAP_POLLING) { 1519 if (ifr->ifr_reqcap & IFCAP_POLLING) { 1520 error = ether_poll_register(npe_poll, ifp); 1521 if (error) 1522 return error; 1523 NPE_LOCK(sc); 1524 /* disable callbacks XXX txdone is shared */ 1525 ixpqmgr_notify_disable(sc->rx_qid); 1526 ixpqmgr_notify_disable(sc->tx_doneqid); 1527 ifp->if_capenable |= IFCAP_POLLING; 1528 NPE_UNLOCK(sc); 1529 } else { 1530 error = ether_poll_deregister(ifp); 1531 /* NB: always enable qmgr callbacks */ 1532 NPE_LOCK(sc); 1533 /* enable qmgr callbacks */ 1534 ixpqmgr_notify_enable(sc->rx_qid, 1535 IX_QMGR_Q_SOURCE_ID_NOT_E); 1536 ixpqmgr_notify_enable(sc->tx_doneqid, 1537 IX_QMGR_Q_SOURCE_ID_NOT_E); 1538 ifp->if_capenable &= ~IFCAP_POLLING; 1539 NPE_UNLOCK(sc); 1540 } 1541 } 1542 break; 1543#endif 1544 default: 1545 error = ether_ioctl(ifp, cmd, data); 1546 break; 1547 } 1548 return error; 1549} 1550 1551/* 1552 * Setup a traffic class -> rx queue mapping. 1553 */ 1554static int 1555npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) 1556{ 1557 uint32_t msg[2]; 1558 1559 msg[0] = (NPE_SETRXQOSENTRY << 24) | (sc->sc_npeid << 20) | classix; 1560 msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); 1561 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1562} 1563 1564static int 1565npe_setportaddress(struct npe_softc *sc, const uint8_t mac[ETHER_ADDR_LEN]) 1566{ 1567 uint32_t msg[2]; 1568 1569 msg[0] = (NPE_SETPORTADDRESS << 24) 1570 | (sc->sc_npeid << 20) 1571 | (mac[0] << 8) 1572 | (mac[1] << 0); 1573 msg[1] = (mac[2] << 24) 1574 | (mac[3] << 16) 1575 | (mac[4] << 8) 1576 | (mac[5] << 0); 1577 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1578} 1579 1580static int 1581npe_setfirewallmode(struct npe_softc *sc, int onoff) 1582{ 1583 uint32_t msg[2]; 1584 1585 /* XXX honor onoff */ 1586 msg[0] = (NPE_SETFIREWALLMODE << 24) | (sc->sc_npeid << 20); 1587 msg[1] = 0; 1588 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1589} 1590 1591/* 1592 * Update and reset the statistics in the NPE. 1593 */ 1594static int 1595npe_updatestats(struct npe_softc *sc) 1596{ 1597 uint32_t msg[2]; 1598 1599 msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; 1600 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1601 return ixpnpe_sendmsg_async(sc->sc_npe, msg); 1602} 1603 1604#if 0 1605/* 1606 * Get the current statistics block. 1607 */ 1608static int 1609npe_getstats(struct npe_softc *sc) 1610{ 1611 uint32_t msg[2]; 1612 1613 msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; 1614 msg[1] = sc->sc_stats_phys; /* physical address of stat block */ 1615 return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); 1616} 1617 1618/* 1619 * Query the image id of the loaded firmware. 1620 */ 1621static uint32_t 1622npe_getimageid(struct npe_softc *sc) 1623{ 1624 uint32_t msg[2]; 1625 1626 msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; 1627 msg[1] = 0; 1628 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; 1629} 1630 1631/* 1632 * Enable/disable loopback. 1633 */ 1634static int 1635npe_setloopback(struct npe_softc *sc, int ena) 1636{ 1637 uint32_t msg[2]; 1638 1639 msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); 1640 msg[1] = 0; 1641 return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); 1642} 1643#endif 1644 1645static void 1646npe_child_detached(device_t dev, device_t child) 1647{ 1648 struct npe_softc *sc; 1649 1650 sc = device_get_softc(dev); 1651 if (child == sc->sc_mii) 1652 sc->sc_mii = NULL; 1653} 1654 1655/* 1656 * MII bus support routines. 1657 */ 1658#define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) 1659#define MII_WR4(sc, reg, v) \ 1660 bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) 1661 1662static uint32_t 1663npe_mii_mdio_read(struct npe_softc *sc, int reg) 1664{ 1665 uint32_t v; 1666 1667 /* NB: registers are known to be sequential */ 1668 v = (MII_RD4(sc, reg+0) & 0xff) << 0; 1669 v |= (MII_RD4(sc, reg+4) & 0xff) << 8; 1670 v |= (MII_RD4(sc, reg+8) & 0xff) << 16; 1671 v |= (MII_RD4(sc, reg+12) & 0xff) << 24; 1672 return v; 1673} 1674 1675static void 1676npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) 1677{ 1678 /* NB: registers are known to be sequential */ 1679 MII_WR4(sc, reg+0, cmd & 0xff); 1680 MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); 1681 MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); 1682 MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); 1683} 1684 1685static int 1686npe_mii_mdio_wait(struct npe_softc *sc) 1687{ 1688 uint32_t v; 1689 int i; 1690 1691 /* NB: typically this takes 25-30 trips */ 1692 for (i = 0; i < 1000; i++) { 1693 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); 1694 if ((v & NPE_MII_GO) == 0) 1695 return 1; 1696 DELAY(1); 1697 } 1698 device_printf(sc->sc_dev, "%s: timeout after ~1ms, cmd 0x%x\n", 1699 __func__, v); 1700 return 0; /* NB: timeout */ 1701} 1702 1703static int 1704npe_miibus_readreg(device_t dev, int phy, int reg) 1705{ 1706 struct npe_softc *sc = device_get_softc(dev); 1707 uint32_t v; 1708 1709 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) | NPE_MII_GO; 1710 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1711 if (npe_mii_mdio_wait(sc)) 1712 v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); 1713 else 1714 v = 0xffff | NPE_MII_READ_FAIL; 1715 return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); 1716} 1717 1718static int 1719npe_miibus_writereg(device_t dev, int phy, int reg, int data) 1720{ 1721 struct npe_softc *sc = device_get_softc(dev); 1722 uint32_t v; 1723 1724 v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) 1725 | data | NPE_MII_WRITE 1726 | NPE_MII_GO; 1727 npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); 1728 /* XXX complain about timeout */ 1729 (void) npe_mii_mdio_wait(sc); 1730 return (0); 1731} 1732 1733static void 1734npe_miibus_statchg(device_t dev) 1735{ 1736 struct npe_softc *sc = device_get_softc(dev); 1737 struct mii_data *mii = device_get_softc(sc->sc_mii); 1738 uint32_t tx1, rx1; 1739 1740 /* sync MAC duplex state */ 1741 tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); 1742 rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); 1743 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1744 tx1 &= ~NPE_TX_CNTRL1_DUPLEX; 1745 rx1 |= NPE_RX_CNTRL1_PAUSE_EN; 1746 } else { 1747 tx1 |= NPE_TX_CNTRL1_DUPLEX; 1748 rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; 1749 } 1750 WR4(sc, NPE_MAC_RX_CNTRL1, rx1); 1751 WR4(sc, NPE_MAC_TX_CNTRL1, tx1); 1752} 1753 1754static device_method_t npe_methods[] = { 1755 /* Device interface */ 1756 DEVMETHOD(device_probe, npe_probe), 1757 DEVMETHOD(device_attach, npe_attach), 1758 DEVMETHOD(device_detach, npe_detach), 1759 1760 /* Bus interface */ 1761 DEVMETHOD(bus_child_detached, npe_child_detached), 1762 1763 /* MII interface */ 1764 DEVMETHOD(miibus_readreg, npe_miibus_readreg), 1765 DEVMETHOD(miibus_writereg, npe_miibus_writereg), 1766 DEVMETHOD(miibus_statchg, npe_miibus_statchg), 1767 1768 { 0, 0 } 1769}; 1770 1771static driver_t npe_driver = { 1772 "npe", 1773 npe_methods, 1774 sizeof(struct npe_softc), 1775}; 1776 1777DRIVER_MODULE(npe, ixp, npe_driver, npe_devclass, 0, 0); 1778DRIVER_MODULE(miibus, npe, miibus_driver, miibus_devclass, 0, 0); 1779MODULE_DEPEND(npe, ixpqmgr, 1, 1, 1); 1780MODULE_DEPEND(npe, miibus, 1, 1, 1); 1781MODULE_DEPEND(npe, ether, 1, 1, 1); 1782