1249997Swkoszek/*-
2250015Swkoszek * Copyright (c) 2012-2013 Thomas Skibo
3249997Swkoszek * All rights reserved.
4250015Swkoszek *
5249997Swkoszek * Redistribution and use in source and binary forms, with or without
6250015Swkoszek * modification, are permitted provided that the following conditions
7250015Swkoszek * are met:
8250015Swkoszek * 1. Redistributions of source code must retain the above copyright
9250015Swkoszek *    notice, this list of conditions and the following disclaimer.
10250015Swkoszek * 2. Redistributions in binary form must reproduce the above copyright
11250015Swkoszek *    notice, this list of conditions and the following disclaimer in the
12250015Swkoszek *    documentation and/or other materials provided with the distribution.
13250015Swkoszek *
14250015Swkoszek * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15250015Swkoszek * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16249997Swkoszek * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17250015Swkoszek * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18250015Swkoszek * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19250015Swkoszek * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20250015Swkoszek * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21250015Swkoszek * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22250015Swkoszek * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23250015Swkoszek * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24250015Swkoszek * SUCH DAMAGE.
25249997Swkoszek *
26250015Swkoszek * $FreeBSD: releng/11.0/sys/arm/xilinx/zy7_reg.h 265148 2014-04-30 14:38:13Z ian $
27249997Swkoszek */
28249997Swkoszek
29250015Swkoszek/*
30250015Swkoszek * Address regions of Zynq-7000.
31249997Swkoszek * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
32249997Swkoszek * (v1.4) November 16, 2012.  Xilinx doc UG585.
33249997Swkoszek */
34249997Swkoszek
35249997Swkoszek#ifndef _ZY7_REG_H_
36249997Swkoszek#define _ZY7_REG_H_
37249997Swkoszek
38249997Swkoszek/* PL AXI buses:  General Purpose Port #0, M_AXI_GP0. */
39249997Swkoszek#define ZYNQ7_PLGP0_HWBASE	0x40000000
40249997Swkoszek#define ZYNQ7_PLGP0_SIZE	0x40000000
41249997Swkoszek
42249997Swkoszek/* PL AXI buses:  General Purpose Port #1, M_AXI_GP1. */
43249997Swkoszek#define ZYNQ7_PLGP1_HWBASE	0x80000000
44249997Swkoszek#define ZYNQ7_PLGP1_SIZE	0x40000000
45249997Swkoszek
46249997Swkoszek/* I/O Peripheral registers. */
47249997Swkoszek#define ZYNQ7_PSIO_HWBASE	0xE0000000
48249997Swkoszek#define ZYNQ7_PSIO_SIZE		0x00300000
49249997Swkoszek
50249997Swkoszek/* UART0 and UART1 */
51249997Swkoszek#define ZYNQ7_UART0_HWBASE	(ZYNQ7_PSIO_HWBASE)
52249997Swkoszek#define ZYNQ7_UART0_SIZE	0x1000
53249997Swkoszek
54249997Swkoszek#define ZYNQ7_UART1_HWBASE	(ZYNQ7_PSIO_HWBASE+0x1000)
55249997Swkoszek#define ZYNQ7_UART1_SIZE	0x1000
56249997Swkoszek
57249997Swkoszek
58249997Swkoszek/* SMC Memories not mapped for now. */
59249997Swkoszek#define ZYNQ7_SMC_HWBASE	0xE1000000
60249997Swkoszek#define ZYNQ7_SMC_SIZE		0x05000000
61249997Swkoszek
62249997Swkoszek/* SLCR, PS system, and CPU private registers combined in this region. */
63249997Swkoszek#define ZYNQ7_PSCTL_HWBASE	0xF8000000
64249997Swkoszek#define ZYNQ7_PSCTL_SIZE	0x01000000
65249997Swkoszek
66249997Swkoszek#define ZYNQ7_SLCR_HWBASE	(ZYNQ7_PSCTL_HWBASE)
67249997Swkoszek#define ZYNQ7_SLCR_SIZE		0x1000
68249997Swkoszek
69249997Swkoszek#define ZYNQ7_DEVCFG_HWBASE	(ZYNQ7_PSCTL_HWBASE+0x7000)
70249997Swkoszek#define ZYNQ7_DEVCFG_SIZE	0x1000
71249997Swkoszek
72249997Swkoszek#endif /* _ZY7_REG_H_ */
73