1/*- 2 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: releng/11.0/sys/arm/ti/ti_spi.c 297419 2016-03-30 16:26:00Z loos $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33 34#include <sys/kernel.h> 35#include <sys/module.h> 36#include <sys/rman.h> 37#include <sys/lock.h> 38#include <sys/mutex.h> 39#include <sys/sysctl.h> 40 41#include <machine/bus.h> 42#include <machine/resource.h> 43#include <machine/intr.h> 44 45#include <dev/fdt/fdt_common.h> 46#include <dev/ofw/ofw_bus.h> 47#include <dev/ofw/ofw_bus_subr.h> 48 49#include <dev/spibus/spi.h> 50#include <dev/spibus/spibusvar.h> 51 52#include <arm/ti/ti_prcm.h> 53#include <arm/ti/ti_hwmods.h> 54#include <arm/ti/ti_spireg.h> 55#include <arm/ti/ti_spivar.h> 56 57#include "spibus_if.h" 58 59static void ti_spi_intr(void *); 60static int ti_spi_detach(device_t); 61 62#undef TI_SPI_DEBUG 63#ifdef TI_SPI_DEBUG 64#define IRQSTATUSBITS \ 65 "\020\1TX0_EMPTY\2TX0_UNDERFLOW\3RX0_FULL\4RX0_OVERFLOW" \ 66 "\5TX1_EMPTY\6TX1_UNDERFLOW\7RX1_FULL\11TX2_EMPTY" \ 67 "\12TX1_UNDERFLOW\13RX2_FULL\15TX3_EMPTY\16TX3_UNDERFLOW" \ 68 "\17RX3_FULL\22EOW" 69#define CONFBITS \ 70 "\020\1PHA\2POL\7EPOL\17DMAW\20DMAR\21DPE0\22DPE1\23IS" \ 71 "\24TURBO\25FORCE\30SBE\31SBPOL\34FFEW\35FFER\36CLKG" 72#define STATBITS \ 73 "\020\1RXS\2TXS\3EOT\4TXFFE\5TXFFF\6RXFFE\7RXFFFF" 74#define MODULCTRLBITS \ 75 "\020\1SINGLE\2NOSPIEN\3SLAVE\4SYST\10MOA\11FDAA" 76#define CTRLBITS \ 77 "\020\1ENABLED" 78 79static void 80ti_spi_printr(device_t dev) 81{ 82 int clk, conf, ctrl, div, i, j, wl; 83 struct ti_spi_softc *sc; 84 uint32_t reg; 85 86 sc = device_get_softc(dev); 87 reg = TI_SPI_READ(sc, MCSPI_SYSCONFIG); 88 device_printf(dev, "SYSCONFIG: %#x\n", reg); 89 reg = TI_SPI_READ(sc, MCSPI_SYSSTATUS); 90 device_printf(dev, "SYSSTATUS: %#x\n", reg); 91 reg = TI_SPI_READ(sc, MCSPI_IRQSTATUS); 92 device_printf(dev, "IRQSTATUS: 0x%b\n", reg, IRQSTATUSBITS); 93 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); 94 device_printf(dev, "IRQENABLE: 0x%b\n", reg, IRQSTATUSBITS); 95 reg = TI_SPI_READ(sc, MCSPI_MODULCTRL); 96 device_printf(dev, "MODULCTRL: 0x%b\n", reg, MODULCTRLBITS); 97 for (i = 0; i < sc->sc_numcs; i++) { 98 ctrl = TI_SPI_READ(sc, MCSPI_CTRL_CH(i)); 99 conf = TI_SPI_READ(sc, MCSPI_CONF_CH(i)); 100 device_printf(dev, "CH%dCONF: 0x%b\n", i, conf, CONFBITS); 101 if (conf & MCSPI_CONF_CLKG) { 102 div = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; 103 div |= ((ctrl >> MCSPI_CTRL_EXTCLK_SHIFT) & MCSPI_CTRL_EXTCLK_MSK) << 4; 104 } else { 105 div = 1; 106 j = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; 107 while (j-- > 0) 108 div <<= 1; 109 } 110 clk = TI_SPI_GCLK / div; 111 wl = ((conf >> MCSPI_CONF_WL_SHIFT) & MCSPI_CONF_WL_MSK) + 1; 112 device_printf(dev, "wordlen: %-2d clock: %d\n", wl, clk); 113 reg = TI_SPI_READ(sc, MCSPI_STAT_CH(i)); 114 device_printf(dev, "CH%dSTAT: 0x%b\n", i, reg, STATBITS); 115 device_printf(dev, "CH%dCTRL: 0x%b\n", i, ctrl, CTRLBITS); 116 } 117 reg = TI_SPI_READ(sc, MCSPI_XFERLEVEL); 118 device_printf(dev, "XFERLEVEL: %#x\n", reg); 119} 120#endif 121 122static void 123ti_spi_set_clock(struct ti_spi_softc *sc, int ch, int freq) 124{ 125 uint32_t clkdiv, conf, div, extclk, reg; 126 127 clkdiv = TI_SPI_GCLK / freq; 128 if (clkdiv > MCSPI_EXTCLK_MSK) { 129 extclk = 0; 130 clkdiv = 0; 131 div = 1; 132 while (TI_SPI_GCLK / div > freq && clkdiv <= 0xf) { 133 clkdiv++; 134 div <<= 1; 135 } 136 conf = clkdiv << MCSPI_CONF_CLK_SHIFT; 137 } else { 138 extclk = clkdiv >> 4; 139 clkdiv &= MCSPI_CONF_CLK_MSK; 140 conf = MCSPI_CONF_CLKG | clkdiv << MCSPI_CONF_CLK_SHIFT; 141 } 142 143 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(ch)); 144 reg &= ~(MCSPI_CTRL_EXTCLK_MSK << MCSPI_CTRL_EXTCLK_SHIFT); 145 reg |= extclk << MCSPI_CTRL_EXTCLK_SHIFT; 146 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(ch), reg); 147 148 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(ch)); 149 reg &= ~(MCSPI_CONF_CLKG | MCSPI_CONF_CLK_MSK << MCSPI_CONF_CLK_SHIFT); 150 TI_SPI_WRITE(sc, MCSPI_CONF_CH(ch), reg | conf); 151} 152 153static int 154ti_spi_probe(device_t dev) 155{ 156 157 if (!ofw_bus_status_okay(dev)) 158 return (ENXIO); 159 if (!ofw_bus_is_compatible(dev, "ti,omap4-mcspi")) 160 return (ENXIO); 161 162 device_set_desc(dev, "TI McSPI controller"); 163 164 return (BUS_PROBE_DEFAULT); 165} 166 167static int 168ti_spi_attach(device_t dev) 169{ 170 int clk_id, err, i, rid, timeout; 171 struct ti_spi_softc *sc; 172 uint32_t rev; 173 174 sc = device_get_softc(dev); 175 sc->sc_dev = dev; 176 177 /* 178 * Get the MMCHS device id from FDT. If it's not there use the newbus 179 * unit number (which will work as long as the devices are in order and 180 * none are skipped in the fdt). Note that this is a property we made 181 * up and added in freebsd, it doesn't exist in the published bindings. 182 */ 183 clk_id = ti_hwmods_get_clock(dev); 184 if (clk_id == INVALID_CLK_IDENT) { 185 device_printf(dev, 186 "failed to get clock based on hwmods property\n"); 187 return (EINVAL); 188 } 189 190 /* Activate the McSPI module. */ 191 err = ti_prcm_clk_enable(clk_id); 192 if (err) { 193 device_printf(dev, "Error: failed to activate source clock\n"); 194 return (err); 195 } 196 197 /* Get the number of available channels. */ 198 if ((OF_getencprop(ofw_bus_get_node(dev), "ti,spi-num-cs", 199 &sc->sc_numcs, sizeof(sc->sc_numcs))) <= 0) { 200 sc->sc_numcs = 2; 201 } 202 203 rid = 0; 204 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 205 RF_ACTIVE); 206 if (!sc->sc_mem_res) { 207 device_printf(dev, "cannot allocate memory window\n"); 208 return (ENXIO); 209 } 210 211 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 212 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 213 214 rid = 0; 215 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 216 RF_ACTIVE); 217 if (!sc->sc_irq_res) { 218 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 219 device_printf(dev, "cannot allocate interrupt\n"); 220 return (ENXIO); 221 } 222 223 /* Hook up our interrupt handler. */ 224 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 225 NULL, ti_spi_intr, sc, &sc->sc_intrhand)) { 226 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 227 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 228 device_printf(dev, "cannot setup the interrupt handler\n"); 229 return (ENXIO); 230 } 231 232 mtx_init(&sc->sc_mtx, "ti_spi", NULL, MTX_DEF); 233 234 /* Issue a softreset to the controller */ 235 TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET); 236 timeout = 1000; 237 while (!(TI_SPI_READ(sc, MCSPI_SYSSTATUS) & 238 MCSPI_SYSSTATUS_RESETDONE)) { 239 if (--timeout == 0) { 240 device_printf(dev, 241 "Error: Controller reset operation timed out\n"); 242 ti_spi_detach(dev); 243 return (ENXIO); 244 } 245 DELAY(100); 246 } 247 248 /* Print the McSPI module revision. */ 249 rev = TI_SPI_READ(sc, MCSPI_REVISION); 250 device_printf(dev, 251 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n", 252 (rev >> MCSPI_REVISION_SCHEME_SHIFT) & MCSPI_REVISION_SCHEME_MSK, 253 (rev >> MCSPI_REVISION_FUNC_SHIFT) & MCSPI_REVISION_FUNC_MSK, 254 (rev >> MCSPI_REVISION_RTL_SHIFT) & MCSPI_REVISION_RTL_MSK, 255 (rev >> MCSPI_REVISION_MAJOR_SHIFT) & MCSPI_REVISION_MAJOR_MSK, 256 (rev >> MCSPI_REVISION_MINOR_SHIFT) & MCSPI_REVISION_MINOR_MSK, 257 (rev >> MCSPI_REVISION_CUSTOM_SHIFT) & MCSPI_REVISION_CUSTOM_MSK); 258 259 /* Set Master mode, single channel. */ 260 TI_SPI_WRITE(sc, MCSPI_MODULCTRL, MCSPI_MODULCTRL_SINGLE); 261 262 /* Clear pending interrupts and disable interrupts. */ 263 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0x0); 264 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff); 265 266 for (i = 0; i < sc->sc_numcs; i++) { 267 /* 268 * Default to SPI mode 0, CS active low, 8 bits word length and 269 * 500kHz clock. 270 */ 271 TI_SPI_WRITE(sc, MCSPI_CONF_CH(i), 272 MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | 273 (8 - 1) << MCSPI_CONF_WL_SHIFT); 274 /* Set initial clock - 500kHz. */ 275 ti_spi_set_clock(sc, i, 500000); 276 } 277 278#ifdef TI_SPI_DEBUG 279 ti_spi_printr(dev); 280#endif 281 282 device_add_child(dev, "spibus", -1); 283 284 return (bus_generic_attach(dev)); 285} 286 287static int 288ti_spi_detach(device_t dev) 289{ 290 struct ti_spi_softc *sc; 291 292 sc = device_get_softc(dev); 293 294 /* Clear pending interrupts and disable interrupts. */ 295 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0); 296 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff); 297 298 /* Reset controller. */ 299 TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET); 300 301 bus_generic_detach(dev); 302 303 mtx_destroy(&sc->sc_mtx); 304 if (sc->sc_intrhand) 305 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 306 if (sc->sc_irq_res) 307 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 308 if (sc->sc_mem_res) 309 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 310 311 return (0); 312} 313 314static int 315ti_spi_fill_fifo(struct ti_spi_softc *sc) 316{ 317 int bytes, timeout; 318 struct spi_command *cmd; 319 uint32_t written; 320 uint8_t *data; 321 322 cmd = sc->sc_cmd; 323 bytes = min(sc->sc_len - sc->sc_written, sc->sc_fifolvl); 324 while (bytes-- > 0) { 325 data = (uint8_t *)cmd->tx_cmd; 326 written = sc->sc_written++; 327 if (written >= cmd->tx_cmd_sz) { 328 data = (uint8_t *)cmd->tx_data; 329 written -= cmd->tx_cmd_sz; 330 } 331 if (sc->sc_fifolvl == 1) { 332 /* FIFO disabled. */ 333 timeout = 1000; 334 while (--timeout > 0 && (TI_SPI_READ(sc, 335 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_TXS) == 0) { 336 DELAY(100); 337 } 338 if (timeout == 0) 339 return (-1); 340 } 341 TI_SPI_WRITE(sc, MCSPI_TX_CH(sc->sc_cs), data[written]); 342 } 343 344 return (0); 345} 346 347static int 348ti_spi_drain_fifo(struct ti_spi_softc *sc) 349{ 350 int bytes, timeout; 351 struct spi_command *cmd; 352 uint32_t read; 353 uint8_t *data; 354 355 cmd = sc->sc_cmd; 356 bytes = min(sc->sc_len - sc->sc_read, sc->sc_fifolvl); 357 while (bytes-- > 0) { 358 data = (uint8_t *)cmd->rx_cmd; 359 read = sc->sc_read++; 360 if (read >= cmd->rx_cmd_sz) { 361 data = (uint8_t *)cmd->rx_data; 362 read -= cmd->rx_cmd_sz; 363 } 364 if (sc->sc_fifolvl == 1) { 365 /* FIFO disabled. */ 366 timeout = 1000; 367 while (--timeout > 0 && (TI_SPI_READ(sc, 368 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_RXS) == 0) { 369 DELAY(100); 370 } 371 if (timeout == 0) 372 return (-1); 373 } 374 data[read] = TI_SPI_READ(sc, MCSPI_RX_CH(sc->sc_cs)); 375 } 376 377 return (0); 378} 379 380static void 381ti_spi_intr(void *arg) 382{ 383 int eow; 384 struct ti_spi_softc *sc; 385 uint32_t status; 386 387 eow = 0; 388 sc = (struct ti_spi_softc *)arg; 389 TI_SPI_LOCK(sc); 390 status = TI_SPI_READ(sc, MCSPI_IRQSTATUS); 391 392 /* 393 * No new TX_empty or RX_full event will be asserted while the CPU has 394 * not performed the number of writes or reads defined by 395 * MCSPI_XFERLEVEL[AEL] and MCSPI_XFERLEVEL[AFL]. It is responsibility 396 * of CPU perform the right number of writes and reads. 397 */ 398 if (status & MCSPI_IRQ_TX0_EMPTY) 399 ti_spi_fill_fifo(sc); 400 if (status & MCSPI_IRQ_RX0_FULL) 401 ti_spi_drain_fifo(sc); 402 403 if (status & MCSPI_IRQ_EOW) 404 eow = 1; 405 406 /* Clear interrupt status. */ 407 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, status); 408 409 /* Check for end of transfer. */ 410 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { 411 sc->sc_flags |= TI_SPI_DONE; 412 wakeup(sc->sc_dev); 413 } 414 415 TI_SPI_UNLOCK(sc); 416} 417 418static int 419ti_spi_pio_transfer(struct ti_spi_softc *sc) 420{ 421 422 while (sc->sc_len - sc->sc_written > 0) { 423 if (ti_spi_fill_fifo(sc) == -1) 424 return (EIO); 425 if (ti_spi_drain_fifo(sc) == -1) 426 return (EIO); 427 } 428 429 return (0); 430} 431 432static int 433ti_spi_gcd(int a, int b) 434{ 435 int m; 436 437 while ((m = a % b) != 0) { 438 a = b; 439 b = m; 440 } 441 442 return (b); 443} 444 445static int 446ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 447{ 448 int cs, err; 449 struct ti_spi_softc *sc; 450 uint32_t reg; 451 452 sc = device_get_softc(dev); 453 454 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, 455 ("TX/RX command sizes should be equal")); 456 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, 457 ("TX/RX data sizes should be equal")); 458 459 /* Get the proper chip select for this child. */ 460 spibus_get_cs(child, &cs); 461 if (cs < 0 || cs > sc->sc_numcs) { 462 device_printf(dev, "Invalid chip select %d requested by %s\n", 463 cs, device_get_nameunit(child)); 464 return (EINVAL); 465 } 466 467 TI_SPI_LOCK(sc); 468 469 /* If the controller is in use wait until it is available. */ 470 while (sc->sc_flags & TI_SPI_BUSY) 471 mtx_sleep(dev, &sc->sc_mtx, 0, "ti_spi", 0); 472 473 /* Now we have control over SPI controller. */ 474 sc->sc_flags = TI_SPI_BUSY; 475 476 /* Save the SPI command data. */ 477 sc->sc_cs = cs; 478 sc->sc_cmd = cmd; 479 sc->sc_read = 0; 480 sc->sc_written = 0; 481 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; 482 sc->sc_fifolvl = ti_spi_gcd(sc->sc_len, TI_SPI_FIFOSZ); 483 if (sc->sc_fifolvl < 2 || sc->sc_len > 0xffff) 484 sc->sc_fifolvl = 1; /* FIFO disabled. */ 485 /* Disable FIFO for now. */ 486 sc->sc_fifolvl = 1; 487 488 /* Use a safe clock - 500kHz. */ 489 ti_spi_set_clock(sc, sc->sc_cs, 500000); 490 491 /* Disable the FIFO. */ 492 TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0); 493 494 /* 8 bits word, d0 miso, d1 mosi, mode 0 and CS active low. */ 495 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); 496 reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW | MCSPI_CONF_SBPOL | 497 MCSPI_CONF_SBE | MCSPI_CONF_TURBO | MCSPI_CONF_IS | 498 MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR | 499 MCSPI_CONF_DMAW | MCSPI_CONF_EPOL); 500 reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS; 501 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); 502 503#if 0 504 /* Enable channel interrupts. */ 505 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); 506 reg |= 0xf; 507 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg); 508#endif 509 510 /* Start the transfer. */ 511 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); 512 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg | MCSPI_CTRL_ENABLE); 513 514 /* Force CS on. */ 515 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); 516 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg |= MCSPI_CONF_FORCE); 517 518 err = 0; 519 if (sc->sc_fifolvl == 1) 520 err = ti_spi_pio_transfer(sc); 521 522 /* Force CS off. */ 523 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); 524 reg &= ~MCSPI_CONF_FORCE; 525 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); 526 527 /* Disable IRQs. */ 528 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); 529 reg &= ~0xf; 530 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg); 531 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xf); 532 533 /* Disable the SPI channel. */ 534 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); 535 reg &= ~MCSPI_CTRL_ENABLE; 536 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg); 537 538 /* Disable FIFO. */ 539 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); 540 reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW); 541 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); 542 543 /* Release the controller and wakeup the next thread waiting for it. */ 544 sc->sc_flags = 0; 545 wakeup_one(dev); 546 TI_SPI_UNLOCK(sc); 547 548 return (err); 549} 550 551static phandle_t 552ti_spi_get_node(device_t bus, device_t dev) 553{ 554 555 /* Share controller node with spibus. */ 556 return (ofw_bus_get_node(bus)); 557} 558 559static device_method_t ti_spi_methods[] = { 560 /* Device interface */ 561 DEVMETHOD(device_probe, ti_spi_probe), 562 DEVMETHOD(device_attach, ti_spi_attach), 563 DEVMETHOD(device_detach, ti_spi_detach), 564 565 /* SPI interface */ 566 DEVMETHOD(spibus_transfer, ti_spi_transfer), 567 568 /* ofw_bus interface */ 569 DEVMETHOD(ofw_bus_get_node, ti_spi_get_node), 570 571 DEVMETHOD_END 572}; 573 574static devclass_t ti_spi_devclass; 575 576static driver_t ti_spi_driver = { 577 "spi", 578 ti_spi_methods, 579 sizeof(struct ti_spi_softc), 580}; 581 582DRIVER_MODULE(ti_spi, simplebus, ti_spi_driver, ti_spi_devclass, 0, 0); 583