1239281Sgonzo/*- 2239281Sgonzo * Copyright (c) 2011 3239281Sgonzo * Ben Gray <ben.r.gray@gmail.com>. 4239281Sgonzo * All rights reserved. 5239281Sgonzo * 6239281Sgonzo * Redistribution and use in source and binary forms, with or without 7239281Sgonzo * modification, are permitted provided that the following conditions 8239281Sgonzo * are met: 9239281Sgonzo * 1. Redistributions of source code must retain the above copyright 10239281Sgonzo * notice, this list of conditions and the following disclaimer. 11239281Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 12239281Sgonzo * notice, this list of conditions and the following disclaimer in the 13239281Sgonzo * documentation and/or other materials provided with the distribution. 14239281Sgonzo * 15239281Sgonzo * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16239281Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17239281Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18239281Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19239281Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20239281Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21239281Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22239281Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23239281Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24239281Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25239281Sgonzo * SUCH DAMAGE. 26239281Sgonzo * 27239281Sgonzo * $FreeBSD: releng/11.0/sys/arm/ti/omap4/omap4_reg.h 239281 2012-08-15 06:31:32Z gonzo $ 28239281Sgonzo */ 29239281Sgonzo 30239281Sgonzo/* 31239281Sgonzo * Texas Instruments - OMAP44xx series processors 32239281Sgonzo * 33239281Sgonzo * Reference: 34239281Sgonzo * OMAP44xx Applications Processor 35239281Sgonzo * Technical Reference Manual 36239281Sgonzo * (omap44xx_techref.pdf) 37239281Sgonzo * 38239281Sgonzo * 39239281Sgonzo * Note: 40239281Sgonzo * The devices are mapped into address above 0xD000_0000 as the kernel space 41239281Sgonzo * memory is at 0xC000_0000 and above. The first 256MB after this is reserved 42239281Sgonzo * for the size of the kernel, everything above that is reserved for SoC 43239281Sgonzo * devices. 44239281Sgonzo * 45239281Sgonzo */ 46239281Sgonzo#ifndef _OMAP44XX_REG_H_ 47239281Sgonzo#define _OMAP44XX_REG_H_ 48239281Sgonzo 49239281Sgonzo#ifndef _LOCORE 50239281Sgonzo#include <sys/types.h> /* for uint32_t */ 51239281Sgonzo#endif 52239281Sgonzo 53239281Sgonzo 54239281Sgonzo 55239281Sgonzo 56239281Sgonzo 57239281Sgonzo/* Physical/Virtual address for SDRAM controller */ 58239281Sgonzo 59239281Sgonzo#define OMAP44XX_SMS_VBASE 0x6C000000UL 60239281Sgonzo#define OMAP44XX_SMS_HWBASE 0x6C000000UL 61239281Sgonzo#define OMAP44XX_SMS_SIZE 0x01000000UL 62239281Sgonzo 63239281Sgonzo#define OMAP44XX_SDRC_VBASE 0x6D000000UL 64239281Sgonzo#define OMAP44XX_SDRC_HWBASE 0x6D000000UL 65239281Sgonzo#define OMAP44XX_SDRC_SIZE 0x01000000UL 66239281Sgonzo 67239281Sgonzo 68239281Sgonzo 69239281Sgonzo/* Physical/Virtual address for I/O space */ 70239281Sgonzo 71239281Sgonzo#define OMAP44XX_L3_EMU_VBASE 0xD4000000UL 72239281Sgonzo#define OMAP44XX_L3_EMU_HWBASE 0x54000000UL 73239281Sgonzo#define OMAP44XX_L3_EMU_SIZE 0x00200000UL 74239281Sgonzo 75239281Sgonzo#define OMAP44XX_L3_EMIF1_VBASE 0xEC000000UL 76239281Sgonzo#define OMAP44XX_L3_EMIF1_HWBASE 0x4C000000UL 77239281Sgonzo#define OMAP44XX_L3_EMIF1_SIZE 0x01000000UL 78239281Sgonzo 79239281Sgonzo#define OMAP44XX_L3_EMIF2_VBASE 0xED000000UL 80239281Sgonzo#define OMAP44XX_L3_EMIF2_HWBASE 0x4D000000UL 81239281Sgonzo#define OMAP44XX_L3_EMIF2_SIZE 0x01000000UL 82239281Sgonzo 83239281Sgonzo 84239281Sgonzo#define OMAP44XX_L4_CORE_VBASE 0xEA000000UL 85239281Sgonzo#define OMAP44XX_L4_CORE_HWBASE 0x4A000000UL 86239281Sgonzo#define OMAP44XX_L4_CORE_SIZE 0x01000000UL 87239281Sgonzo 88239281Sgonzo#define OMAP44XX_L4_WAKEUP_VBASE 0xEA300000UL 89239281Sgonzo#define OMAP44XX_L4_WAKEUP_HWBASE 0x4A300000UL 90239281Sgonzo#define OMAP44XX_L4_WAKEUP_SIZE 0x00040000UL 91239281Sgonzo 92239281Sgonzo#define OMAP44XX_L4_PERIPH_VBASE 0xE8000000UL 93239281Sgonzo#define OMAP44XX_L4_PERIPH_HWBASE 0x48000000UL 94239281Sgonzo#define OMAP44XX_L4_PERIPH_SIZE 0x01000000UL 95239281Sgonzo 96239281Sgonzo#define OMAP44XX_L4_ABE_VBASE 0xE9000000UL 97239281Sgonzo#define OMAP44XX_L4_ABE_HWBASE 0x49000000UL 98239281Sgonzo#define OMAP44XX_L4_ABE_SIZE 0x00100000UL 99239281Sgonzo 100239281Sgonzo 101239281Sgonzo/* Physical/Virtual address for MPU Subsystem space */ 102239281Sgonzo 103239281Sgonzo#define OMAP44XX_MPU_SUBSYS_VBASE (OMAP44XX_L4_PERIPH_VBASE + 0x00240000UL) 104239281Sgonzo#define OMAP44XX_MPU_SUBSYS_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + 0x00240000UL) 105239281Sgonzo#define OMAP44XX_MPU_SUBSYS_SIZE 0x00004000UL 106239281Sgonzo 107239281Sgonzo/* 108239281Sgonzo * MPU Subsystem addresss offsets 109239281Sgonzo */ 110239281Sgonzo#define OMAP44XX_SCU_OFFSET 0x00000000UL 111239281Sgonzo#define OMAP44XX_GIC_CPU_OFFSET 0x00000100UL 112239281Sgonzo#define OMAP44XX_GBL_TIMER_OFFSET 0x00000200UL 113239281Sgonzo#define OMAP44XX_PRV_TIMER_OFFSET 0x00000600UL 114239281Sgonzo#define OMAP44XX_GIC_DIST_OFFSET 0x00001000UL 115239281Sgonzo#define OMAP44XX_PL310_OFFSET 0x00002000UL 116239281Sgonzo#define OMAP44XX_CORTEXA9_SOCKET_PRCM_OFFSET 0x00003000UL 117239281Sgonzo#define OMAP44XX_CORTEXA9_PRM_OFFSET 0x00003200UL 118239281Sgonzo#define OMAP44XX_CORTEXA9_CPU0_OFFSET 0x00003400UL 119239281Sgonzo#define OMAP44XX_CORTEXA9_CPU1_OFFSET 0x00003800UL 120239281Sgonzo 121239281Sgonzo#define OMAP44XX_SCU_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_SCU_OFFSET) 122239281Sgonzo#define OMAP44XX_SCU_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_SCU_OFFSET) 123239281Sgonzo#define OMAP44XX_SCU_SIZE 0x00000080UL 124239281Sgonzo#define OMAP44XX_GIC_CPU_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_GIC_CPU_OFFSET) 125239281Sgonzo#define OMAP44XX_GIC_CPU_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_GIC_CPU_OFFSET) 126239281Sgonzo#define OMAP44XX_GIC_CPU_SIZE 0x00000100UL 127239281Sgonzo#define OMAP44XX_GBL_TIMER_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_GBL_TIMER_OFFSET) 128239281Sgonzo#define OMAP44XX_GBL_TIMER_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_GBL_TIMER_OFFSET) 129239281Sgonzo#define OMAP44XX_GBL_TIMER_SIZE 0x00000100UL 130239281Sgonzo#define OMAP44XX_PRV_TIMER_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_PRV_TIMER_OFFSET) 131239281Sgonzo#define OMAP44XX_PRV_TIMER_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_PRV_TIMER_OFFSET) 132239281Sgonzo#define OMAP44XX_PRV_TIMER_SIZE 0x00000100UL 133239281Sgonzo#define OMAP44XX_GIC_DIST_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_GIC_DIST_OFFSET) 134239281Sgonzo#define OMAP44XX_GIC_DIST_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_GIC_DIST_OFFSET) 135239281Sgonzo#define OMAP44XX_GIC_DIST_SIZE 0x00000100UL 136239281Sgonzo#define OMAP44XX_PL310_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_PL310_OFFSET) 137239281Sgonzo#define OMAP44XX_PL310_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_PL310_OFFSET) 138239281Sgonzo#define OMAP44XX_PL310_SIZE 0x00001000UL 139239281Sgonzo 140239281Sgonzo 141239281Sgonzo 142239281Sgonzo 143239281Sgonzo/* 144239281Sgonzo * L4-CORE Physical/Virtual addresss offsets 145239281Sgonzo */ 146239281Sgonzo#define OMAP44XX_SCM_OFFSET 0x00002000UL 147239281Sgonzo#define OMAP44XX_CM_OFFSET 0x00004000UL 148239281Sgonzo#define OMAP44XX_SDMA_OFFSET 0x00056000UL 149239281Sgonzo#define OMAP44XX_USB_TLL_OFFSET 0x00062000UL 150239281Sgonzo#define OMAP44XX_USB_UHH_OFFSET 0x00064000UL 151239281Sgonzo#define OMAP44XX_USB_OHCI_OFFSET 0x00064800UL 152239281Sgonzo#define OMAP44XX_USB_EHCI_OFFSET 0x00064C00UL 153239281Sgonzo#define OMAP44XX_MCBSP1_OFFSET 0x00074000UL 154239281Sgonzo#define OMAP44XX_MCBSP5_OFFSET 0x00096000UL 155239281Sgonzo#define OMAP44XX_SCM_PADCONF_OFFSET 0x00100000UL 156239281Sgonzo 157239281Sgonzo/* 158239281Sgonzo * L4-WAKEUP Physical/Virtual addresss offsets 159239281Sgonzo */ 160239281Sgonzo#define OMAP44XX_PRM_OFFSET 0x00006000UL 161239281Sgonzo#define OMAP44XX_SCRM_OFFSET 0x0000A000UL 162239281Sgonzo#define OMAP44XX_GPIO1_OFFSET 0x00010000UL 163239281Sgonzo#define OMAP44XX_GPTIMER1_OFFSET 0x00018000UL 164239281Sgonzo 165239281Sgonzo 166239281Sgonzo 167239281Sgonzo/* 168239281Sgonzo * L4-PERIPH Physical/Virtual addresss offsets 169239281Sgonzo */ 170239281Sgonzo#define OMAP44XX_UART3_OFFSET 0x00020000UL 171239281Sgonzo#define OMAP44XX_GPTIMER2_OFFSET 0x00032000UL 172239281Sgonzo#define OMAP44XX_GPTIMER3_OFFSET 0x00034000UL 173239281Sgonzo#define OMAP44XX_GPTIMER4_OFFSET 0x00036000UL 174239281Sgonzo#define OMAP44XX_GPTIMER9_OFFSET 0x0003E000UL 175239281Sgonzo#define OMAP44XX_GPIO2_OFFSET 0x00055000UL 176239281Sgonzo#define OMAP44XX_GPIO3_OFFSET 0x00057000UL 177239281Sgonzo#define OMAP44XX_GPIO4_OFFSET 0x00059000UL 178239281Sgonzo#define OMAP44XX_GPIO5_OFFSET 0x0005B000UL 179239281Sgonzo#define OMAP44XX_GPIO6_OFFSET 0x0005D000UL 180239281Sgonzo#define OMAP44XX_I2C3_OFFSET 0x00060000UL 181239281Sgonzo#define OMAP44XX_UART1_OFFSET 0x0006A000UL 182239281Sgonzo#define OMAP44XX_UART2_OFFSET 0x0006C000UL 183239281Sgonzo#define OMAP44XX_UART4_OFFSET 0x0006E000UL 184239281Sgonzo#define OMAP44XX_I2C1_OFFSET 0x00070000UL 185239281Sgonzo#define OMAP44XX_I2C2_OFFSET 0x00072000UL 186239281Sgonzo#define OMAP44XX_SLIMBUS2_OFFSET 0x00076000UL 187239281Sgonzo#define OMAP44XX_ELM_OFFSET 0x00078000UL 188239281Sgonzo#define OMAP44XX_GPTIMER10_OFFSET 0x00086000UL 189239281Sgonzo#define OMAP44XX_GPTIMER11_OFFSET 0x00088000UL 190239281Sgonzo#define OMAP44XX_MCBSP4_OFFSET 0x00096000UL 191239281Sgonzo#define OMAP44XX_MCSPI1_OFFSET 0x00098000UL 192239281Sgonzo#define OMAP44XX_MCSPI2_OFFSET 0x0009A000UL 193239281Sgonzo#define OMAP44XX_MMCHS1_OFFSET 0x0009C000UL 194239281Sgonzo#define OMAP44XX_MMCSD3_OFFSET 0x000AD000UL 195239281Sgonzo#define OMAP44XX_MMCHS2_OFFSET 0x000B4000UL 196239281Sgonzo#define OMAP44XX_MMCSD4_OFFSET 0x000D1000UL 197239281Sgonzo#define OMAP44XX_MMCSD5_OFFSET 0x000D5000UL 198239281Sgonzo#define OMAP44XX_I2C4_OFFSET 0x00350000UL 199239281Sgonzo 200239281Sgonzo/* The following are registers defined as part of the ARM MPCORE system, 201239281Sgonzo * they are not SoC components rather registers that control the MPCORE core. 202239281Sgonzo */ 203239281Sgonzo// #define OMAP44XX_SCU_OFFSET 0x48240000 /* Snoop control unit */ 204239281Sgonzo// #define OMAP44XX_GIC_PROC_OFFSET 0x48240100 /* Interrupt controller unit */ 205239281Sgonzo// #define OMAP44XX_MPU_TIMER_OFFSET 0x48240600 206239281Sgonzo// #define OMAP44XX_GIC_INTR_OFFSET 0x48241000 207239281Sgonzo// #define OMAP44XX_PL310_OFFSET 0x48242000 /* L2 Cache controller */ 208239281Sgonzo 209239281Sgonzo 210239281Sgonzo/* 211239281Sgonzo * L4-ABE Physical/Virtual addresss offsets 212239281Sgonzo */ 213239281Sgonzo#define OMAP44XX_GPTIMER5_OFFSET 0x00038000UL 214239281Sgonzo#define OMAP44XX_GPTIMER6_OFFSET 0x0003A000UL 215239281Sgonzo#define OMAP44XX_GPTIMER7_OFFSET 0x0003C000UL 216239281Sgonzo#define OMAP44XX_GPTIMER8_OFFSET 0x0003E000UL 217239281Sgonzo 218239281Sgonzo 219239281Sgonzo 220239281Sgonzo 221239281Sgonzo 222239281Sgonzo/* 223239281Sgonzo * System Control Module 224239281Sgonzo */ 225239281Sgonzo#define OMAP44XX_SCM_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_SCM_OFFSET) 226239281Sgonzo#define OMAP44XX_SCM_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_SCM_OFFSET) 227239281Sgonzo#define OMAP44XX_SCM_SIZE 0x00001000UL 228239281Sgonzo 229239281Sgonzo 230239281Sgonzo 231239281Sgonzo/* 232239281Sgonzo * 233239281Sgonzo */ 234239281Sgonzo#define OMAP44XX_CM_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_CM_OFFSET) 235239281Sgonzo#define OMAP44XX_CM_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_CM_OFFSET) 236239281Sgonzo#define OMAP44XX_CM_SIZE 0x00001500UL 237239281Sgonzo 238239281Sgonzo 239239281Sgonzo/* 240239281Sgonzo * 241239281Sgonzo */ 242239281Sgonzo#define OMAP44XX_PRM_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_PRM_OFFSET) 243239281Sgonzo#define OMAP44XX_PRM_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_PRM_OFFSET) 244239281Sgonzo#define OMAP44XX_PRM_SIZE 0x00001600UL 245239281Sgonzo 246239281Sgonzo/* 247239281Sgonzo * 248239281Sgonzo */ 249239281Sgonzo#define OMAP44XX_SCRM_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_SCRM_OFFSET) 250239281Sgonzo#define OMAP44XX_SCRM_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_SCRM_OFFSET) 251239281Sgonzo#define OMAP44XX_SCRM_SIZE 0x00000800UL 252239281Sgonzo 253239281Sgonzo 254239281Sgonzo 255239281Sgonzo/* 256239281Sgonzo * Uarts 257239281Sgonzo */ 258239281Sgonzo#define OMAP44XX_UART1_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_UART1_OFFSET) 259239281Sgonzo#define OMAP44XX_UART1_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_UART1_OFFSET) 260239281Sgonzo#define OMAP44XX_UART1_SIZE 0x00001000UL 261239281Sgonzo#define OMAP44XX_UART2_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_UART2_OFFSET) 262239281Sgonzo#define OMAP44XX_UART2_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_UART2_OFFSET) 263239281Sgonzo#define OMAP44XX_UART2_SIZE 0x00001000UL 264239281Sgonzo#define OMAP44XX_UART3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_UART3_OFFSET) 265239281Sgonzo#define OMAP44XX_UART3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_UART3_OFFSET) 266239281Sgonzo#define OMAP44XX_UART3_SIZE 0x00001000UL 267239281Sgonzo#define OMAP44XX_UART4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_UART4_OFFSET) 268239281Sgonzo#define OMAP44XX_UART4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_UART4_OFFSET) 269239281Sgonzo#define OMAP44XX_UART4_SIZE 0x00001000UL 270239281Sgonzo 271239281Sgonzo 272239281Sgonzo 273239281Sgonzo 274239281Sgonzo/* 275239281Sgonzo * I2C Modules 276239281Sgonzo */ 277239281Sgonzo#define OMAP44XX_I2C1_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_I2C1_OFFSET) 278239281Sgonzo#define OMAP44XX_I2C1_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_I2C1_OFFSET) 279239281Sgonzo#define OMAP44XX_I2C1_SIZE 0x00000080UL 280239281Sgonzo#define OMAP44XX_I2C2_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_I2C2_OFFSET) 281239281Sgonzo#define OMAP44XX_I2C2_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_I2C2_OFFSET) 282239281Sgonzo#define OMAP44XX_I2C2_SIZE 0x00000080UL 283239281Sgonzo#define OMAP44XX_I2C3_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_I2C3_OFFSET) 284239281Sgonzo#define OMAP44XX_I2C3_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_I2C3_OFFSET) 285239281Sgonzo#define OMAP44XX_I2C3_SIZE 0x00000080UL 286239281Sgonzo 287239281Sgonzo 288239281Sgonzo 289239281Sgonzo/* 290239281Sgonzo * McBSP Modules 291239281Sgonzo */ 292239281Sgonzo#define OMAP44XX_MCBSP1_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_MCBSP1_OFFSET) 293239281Sgonzo#define OMAP44XX_MCBSP1_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_MCBSP1_OFFSET) 294239281Sgonzo#define OMAP44XX_MCBSP1_SIZE 0x00001000UL 295239281Sgonzo#define OMAP44XX_MCBSP2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MCBSP2_OFFSET) 296239281Sgonzo#define OMAP44XX_MCBSP2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MCBSP2_OFFSET) 297239281Sgonzo#define OMAP44XX_MCBSP2_SIZE 0x00001000UL 298239281Sgonzo#define OMAP44XX_MCBSP3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MCBSP3_OFFSET) 299239281Sgonzo#define OMAP44XX_MCBSP3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MCBSP3_OFFSET) 300239281Sgonzo#define OMAP44XX_MCBSP3_SIZE 0x00001000UL 301239281Sgonzo#define OMAP44XX_MCBSP4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MCBSP4_OFFSET) 302239281Sgonzo#define OMAP44XX_MCBSP4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MCBSP4_OFFSET) 303239281Sgonzo#define OMAP44XX_MCBSP4_SIZE 0x00001000UL 304239281Sgonzo#define OMAP44XX_MCBSP5_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_MCBSP5_OFFSET) 305239281Sgonzo#define OMAP44XX_MCBSP5_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_MCBSP5_OFFSET) 306239281Sgonzo#define OMAP44XX_MCBSP5_SIZE 0x00001000UL 307239281Sgonzo 308239281Sgonzo 309239281Sgonzo 310239281Sgonzo/* 311239281Sgonzo * USB TTL Module 312239281Sgonzo */ 313239281Sgonzo#define OMAP44XX_USB_TLL_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_TLL_OFFSET) 314239281Sgonzo#define OMAP44XX_USB_TLL_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_TLL_OFFSET) 315239281Sgonzo#define OMAP44XX_USB_TLL_SIZE 0x00001000UL 316239281Sgonzo 317239281Sgonzo/* 318239281Sgonzo * USB Host Module 319239281Sgonzo */ 320239281Sgonzo#define OMAP44XX_USB_UHH_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_UHH_OFFSET) 321239281Sgonzo#define OMAP44XX_USB_UHH_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_UHH_OFFSET) 322239281Sgonzo#define OMAP44XX_USB_UHH_SIZE 0x00000700UL 323239281Sgonzo 324239281Sgonzo/* 325239281Sgonzo * USB OHCI Module 326239281Sgonzo */ 327239281Sgonzo#define OMAP44XX_USB_OHCI_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_OHCI_OFFSET) 328239281Sgonzo#define OMAP44XX_USB_OHCI_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_OHCI_OFFSET) 329239281Sgonzo#define OMAP44XX_USB_OHCI_SIZE 0x00000400UL 330239281Sgonzo 331239281Sgonzo/* 332239281Sgonzo * USB EHCI Module 333239281Sgonzo */ 334239281Sgonzo#define OMAP44XX_USB_EHCI_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_EHCI_OFFSET) 335239281Sgonzo#define OMAP44XX_USB_EHCI_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_EHCI_OFFSET) 336239281Sgonzo#define OMAP44XX_USB_EHCI_SIZE 0x0000400UL 337239281Sgonzo 338239281Sgonzo 339239281Sgonzo 340239281Sgonzo 341239281Sgonzo 342239281Sgonzo/* 343239281Sgonzo * SDMA Offset 344239281Sgonzo * PA 0x4805 6000 345239281Sgonzo */ 346239281Sgonzo 347239281Sgonzo#define OMAP44XX_SDMA_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_SDMA_OFFSET) 348239281Sgonzo#define OMAP44XX_SDMA_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_SDMA_OFFSET) 349239281Sgonzo#define OMAP44XX_SDMA_SIZE 0x00001000UL 350239281Sgonzo 351239281Sgonzo 352239281Sgonzo 353239281Sgonzo/* 354239281Sgonzo * Interrupt Controller Unit. 355239281Sgonzo * 356239281Sgonzo * Refer to the omap4_intr.c file for interrupt controller (GIC) 357239281Sgonzo * implementation. 358239281Sgonzo * 359239281Sgonzo * Note: 360239281Sgonzo * - 16 Interprocessor interrupts (IPI): ID[15:0] 361239281Sgonzo * - 2 private Timer/Watchdog interrupts: ID[30:29] 362239281Sgonzo * - 2 legacy nFIQ & nIRQ: one per CPU, bypasses the interrupt distributor 363239281Sgonzo * logic and directly drives interrupt requests into CPU if used in 364239281Sgonzo * legacy mode (else treated like other interrupts lines with ID28 365239281Sgonzo * and ID31 respectively) 366239281Sgonzo * - 128 hardware interrupts: ID[159:32] (rising-edge or high-level sensitive). 367239281Sgonzo */ 368239281Sgonzo#define OMAP44XX_HARDIRQ(x) (32 + (x)) 369239281Sgonzo 370239281Sgonzo#define OMAP44XX_IRQ_L2CACHE OMAP44XX_HARDIRQ(0) /* L2 cache controller interrupt */ 371239281Sgonzo#define OMAP44XX_IRQ_CTI_0 OMAP44XX_HARDIRQ(1) /* Cross-trigger module 0 (CTI0) interrupt */ 372239281Sgonzo#define OMAP44XX_IRQ_CTI_1 OMAP44XX_HARDIRQ(2) /* Cross-trigger module 1 (CTI1) interrupt */ 373239281Sgonzo#define OMAP44XX_IRQ_RESERVED3 OMAP44XX_HARDIRQ(3) /* RESERVED */ 374239281Sgonzo#define OMAP44XX_IRQ_ELM OMAP44XX_HARDIRQ(4) /* Error location process completion */ 375239281Sgonzo#define OMAP44XX_IRQ_RESERVED5 OMAP44XX_HARDIRQ(5) /* RESERVED */ 376239281Sgonzo#define OMAP44XX_IRQ_RESERVED6 OMAP44XX_HARDIRQ(6) /* RESERVED */ 377239281Sgonzo#define OMAP44XX_IRQ_SYS_NIRQ OMAP44XX_HARDIRQ(7) /* External source (active low) */ 378239281Sgonzo#define OMAP44XX_IRQ_RESERVED8 OMAP44XX_HARDIRQ(8) /* RESERVED */ 379239281Sgonzo#define OMAP44XX_IRQ_L3_DBG OMAP44XX_HARDIRQ(9) /* L3 interconnect debug error */ 380239281Sgonzo#define OMAP44XX_IRQ_L3_APP OMAP44XX_HARDIRQ(10) /* L3 interconnect application error */ 381239281Sgonzo#define OMAP44XX_IRQ_PRCM_MPU OMAP44XX_HARDIRQ(11) /* PRCM module IRQ */ 382239281Sgonzo#define OMAP44XX_IRQ_SDMA0 OMAP44XX_HARDIRQ(12) /* System DMA request 0(3) */ 383239281Sgonzo#define OMAP44XX_IRQ_SDMA1 OMAP44XX_HARDIRQ(13) /* System DMA request 1(3) */ 384239281Sgonzo#define OMAP44XX_IRQ_SDMA2 OMAP44XX_HARDIRQ(14) /* System DMA request 2 */ 385239281Sgonzo#define OMAP44XX_IRQ_SDMA3 OMAP44XX_HARDIRQ(15) /* System DMA request 3 */ 386239281Sgonzo#define OMAP44XX_IRQ_MCBSP4 OMAP44XX_HARDIRQ(16) /* McBSP module 4 IRQ */ 387239281Sgonzo#define OMAP44XX_IRQ_MCBSP1 OMAP44XX_HARDIRQ(17) /* McBSP module 1 IRQ */ 388239281Sgonzo#define OMAP44XX_IRQ_SR1 OMAP44XX_HARDIRQ(18) /* SmartReflex��� 1 */ 389239281Sgonzo#define OMAP44XX_IRQ_SR2 OMAP44XX_HARDIRQ(19) /* SmartReflex��� 2 */ 390239281Sgonzo#define OMAP44XX_IRQ_GPMC OMAP44XX_HARDIRQ(20) /* General-purpose memory controller module */ 391239281Sgonzo#define OMAP44XX_IRQ_SGX OMAP44XX_HARDIRQ(21) /* 2D/3D graphics module */ 392239281Sgonzo#define OMAP44XX_IRQ_MCBSP2 OMAP44XX_HARDIRQ(22) /* McBSP module 2 */ 393239281Sgonzo#define OMAP44XX_IRQ_MCBSP3 OMAP44XX_HARDIRQ(23) /* McBSP module 3 */ 394239281Sgonzo#define OMAP44XX_IRQ_ISS5 OMAP44XX_HARDIRQ(24) /* Imaging subsystem interrupt 5 */ 395239281Sgonzo#define OMAP44XX_IRQ_DSS OMAP44XX_HARDIRQ(25) /* Display subsystem module(3) */ 396239281Sgonzo#define OMAP44XX_IRQ_MAIL_U0 OMAP44XX_HARDIRQ(26) /* Mailbox user 0 request */ 397239281Sgonzo#define OMAP44XX_IRQ_C2C_SSCM OMAP44XX_HARDIRQ(27) /* C2C status interrupt */ 398239281Sgonzo#define OMAP44XX_IRQ_DSP_MMU OMAP44XX_HARDIRQ(28) /* DSP MMU */ 399239281Sgonzo#define OMAP44XX_IRQ_GPIO1_MPU OMAP44XX_HARDIRQ(29) /* GPIO module 1(3) */ 400239281Sgonzo#define OMAP44XX_IRQ_GPIO2_MPU OMAP44XX_HARDIRQ(30) /* GPIO module 2(3) */ 401239281Sgonzo#define OMAP44XX_IRQ_GPIO3_MPU OMAP44XX_HARDIRQ(31) /* GPIO module 3(3) */ 402239281Sgonzo#define OMAP44XX_IRQ_GPIO4_MPU OMAP44XX_HARDIRQ(32) /* GPIO module 4(3) */ 403239281Sgonzo#define OMAP44XX_IRQ_GPIO5_MPU OMAP44XX_HARDIRQ(33) /* GPIO module 5(3) */ 404239281Sgonzo#define OMAP44XX_IRQ_GPIO6_MPU OMAP44XX_HARDIRQ(34) /* GPIO module 6(3) */ 405239281Sgonzo#define OMAP44XX_IRQ_RESERVED35 OMAP44XX_HARDIRQ(35) /* RESERVED */ 406239281Sgonzo#define OMAP44XX_IRQ_WDT3 OMAP44XX_HARDIRQ(36) /* Watchdog timer module 3 overflow */ 407239281Sgonzo#define OMAP44XX_IRQ_GPT1 OMAP44XX_HARDIRQ(37) /* General-purpose timer module 1 */ 408239281Sgonzo#define OMAP44XX_IRQ_GPT2 OMAP44XX_HARDIRQ(38) /* General-purpose timer module 2 */ 409239281Sgonzo#define OMAP44XX_IRQ_GPT3 OMAP44XX_HARDIRQ(39) /* General-purpose timer module 3 */ 410239281Sgonzo#define OMAP44XX_IRQ_GPT4 OMAP44XX_HARDIRQ(40) /* General-purpose timer module 4 */ 411239281Sgonzo#define OMAP44XX_IRQ_GPT5 OMAP44XX_HARDIRQ(41) /* General-purpose timer module 5 */ 412239281Sgonzo#define OMAP44XX_IRQ_GPT6 OMAP44XX_HARDIRQ(42) /* General-purpose timer module 6 */ 413239281Sgonzo#define OMAP44XX_IRQ_GPT7 OMAP44XX_HARDIRQ(43) /* General-purpose timer module 7 */ 414239281Sgonzo#define OMAP44XX_IRQ_GPT8 OMAP44XX_HARDIRQ(44) /* General-purpose timer module 8 */ 415239281Sgonzo#define OMAP44XX_IRQ_GPT9 OMAP44XX_HARDIRQ(45) /* General-purpose timer module 9 */ 416239281Sgonzo#define OMAP44XX_IRQ_GPT10 OMAP44XX_HARDIRQ(46) /* General-purpose timer module 10 */ 417239281Sgonzo#define OMAP44XX_IRQ_GPT11 OMAP44XX_HARDIRQ(47) /* General-purpose timer module 11 */ 418239281Sgonzo#define OMAP44XX_IRQ_MCSPI4 OMAP44XX_HARDIRQ(48) /* McSPI module 4 */ 419239281Sgonzo#define OMAP44XX_IRQ_RESERVED49 OMAP44XX_HARDIRQ(49) /* RESERVED */ 420239281Sgonzo#define OMAP44XX_IRQ_RESERVED50 OMAP44XX_HARDIRQ(50) /* RESERVED */ 421239281Sgonzo#define OMAP44XX_IRQ_RESERVED51 OMAP44XX_HARDIRQ(51) /* RESERVED */ 422239281Sgonzo#define OMAP44XX_IRQ_RESERVED52 OMAP44XX_HARDIRQ(52) /* RESERVED */ 423239281Sgonzo#define OMAP44XX_IRQ_DSS_DSI1 OMAP44XX_HARDIRQ(53) /* Display Subsystem DSI1 interrupt */ 424239281Sgonzo#define OMAP44XX_IRQ_RESERVED54 OMAP44XX_HARDIRQ(54) /* RESERVED */ 425239281Sgonzo#define OMAP44XX_IRQ_RESERVED55 OMAP44XX_HARDIRQ(55) /* RESERVED */ 426239281Sgonzo#define OMAP44XX_IRQ_I2C1 OMAP44XX_HARDIRQ(56) /* I2C module 1 */ 427239281Sgonzo#define OMAP44XX_IRQ_I2C2 OMAP44XX_HARDIRQ(57) /* I2C module 2 */ 428239281Sgonzo#define OMAP44XX_IRQ_HDQ OMAP44XX_HARDIRQ(58) /* HDQ / One-wire */ 429239281Sgonzo#define OMAP44XX_IRQ_MMC5 OMAP44XX_HARDIRQ(59) /* MMC5 interrupt */ 430239281Sgonzo#define OMAP44XX_IRQ_RESERVED60 OMAP44XX_HARDIRQ(60) /* RESERVED */ 431239281Sgonzo#define OMAP44XX_IRQ_I2C3 OMAP44XX_HARDIRQ(61) /* I2C module 3 */ 432239281Sgonzo#define OMAP44XX_IRQ_I2C4 OMAP44XX_HARDIRQ(62) /* I2C module 4 */ 433239281Sgonzo#define OMAP44XX_IRQ_RESERVED63 OMAP44XX_HARDIRQ(63) /* RESERVED */ 434239281Sgonzo#define OMAP44XX_IRQ_RESERVED64 OMAP44XX_HARDIRQ(64) /* RESERVED */ 435239281Sgonzo#define OMAP44XX_IRQ_MCSPI1 OMAP44XX_HARDIRQ(65) /* McSPI module 1 */ 436239281Sgonzo#define OMAP44XX_IRQ_MCSPI2 OMAP44XX_HARDIRQ(66) /* McSPI module 2 */ 437239281Sgonzo#define OMAP44XX_IRQ_HSI_P1 OMAP44XX_HARDIRQ(67) /* HSI Port 1 interrupt */ 438239281Sgonzo#define OMAP44XX_IRQ_HSI_P2 OMAP44XX_HARDIRQ(68) /* HSI Port 2 interrupt */ 439239281Sgonzo#define OMAP44XX_IRQ_FDIF_3 OMAP44XX_HARDIRQ(69) /* Face detect interrupt 3 */ 440239281Sgonzo#define OMAP44XX_IRQ_UART4 OMAP44XX_HARDIRQ(70) /* UART module 4 interrupt */ 441239281Sgonzo#define OMAP44XX_IRQ_HSI_DMA OMAP44XX_HARDIRQ(71) /* HSI DMA engine MPU request */ 442239281Sgonzo#define OMAP44XX_IRQ_UART1 OMAP44XX_HARDIRQ(72) /* UART module 1 */ 443239281Sgonzo#define OMAP44XX_IRQ_UART2 OMAP44XX_HARDIRQ(73) /* UART module 2 */ 444239281Sgonzo#define OMAP44XX_IRQ_UART3 OMAP44XX_HARDIRQ(74) /* UART module 3 (also infrared)(3) */ 445239281Sgonzo#define OMAP44XX_IRQ_PBIAS OMAP44XX_HARDIRQ(75) /* Merged interrupt for PBIASlite1 and 2 */ 446239281Sgonzo#define OMAP44XX_IRQ_OHCI OMAP44XX_HARDIRQ(76) /* OHCI controller HSUSB MP Host Interrupt */ 447239281Sgonzo#define OMAP44XX_IRQ_EHCI OMAP44XX_HARDIRQ(77) /* EHCI controller HSUSB MP Host Interrupt */ 448239281Sgonzo#define OMAP44XX_IRQ_TLL OMAP44XX_HARDIRQ(78) /* HSUSB MP TLL Interrupt */ 449239281Sgonzo#define OMAP44XX_IRQ_RESERVED79 OMAP44XX_HARDIRQ(79) /* RESERVED */ 450239281Sgonzo#define OMAP44XX_IRQ_WDT2 OMAP44XX_HARDIRQ(80) /* WDTIMER2 interrupt */ 451239281Sgonzo#define OMAP44XX_IRQ_RESERVED81 OMAP44XX_HARDIRQ(81) /* RESERVED */ 452239281Sgonzo#define OMAP44XX_IRQ_RESERVED82 OMAP44XX_HARDIRQ(82) /* RESERVED */ 453239281Sgonzo#define OMAP44XX_IRQ_MMC1 OMAP44XX_HARDIRQ(83) /* MMC/SD module 1 */ 454239281Sgonzo#define OMAP44XX_IRQ_DSS_DSI2 OMAP44XX_HARDIRQ(84) /* Display subsystem DSI2 interrupt */ 455239281Sgonzo#define OMAP44XX_IRQ_RESERVED85 OMAP44XX_HARDIRQ(85) /* Reserved */ 456239281Sgonzo#define OMAP44XX_IRQ_MMC2 OMAP44XX_HARDIRQ(86) /* MMC/SD module 2 */ 457239281Sgonzo#define OMAP44XX_IRQ_MPU_ICR OMAP44XX_HARDIRQ(87) /* MPU ICR */ 458239281Sgonzo#define OMAP44XX_IRQ_C2C_GPI OMAP44XX_HARDIRQ(88) /* C2C GPI interrupt */ 459239281Sgonzo#define OMAP44XX_IRQ_FSUSB OMAP44XX_HARDIRQ(89) /* FS-USB - host controller Interrupt */ 460239281Sgonzo#define OMAP44XX_IRQ_FSUSB_SMI OMAP44XX_HARDIRQ(90) /* FS-USB - host controller SMI Interrupt */ 461239281Sgonzo#define OMAP44XX_IRQ_MCSPI3 OMAP44XX_HARDIRQ(91) /* McSPI module 3 */ 462239281Sgonzo#define OMAP44XX_IRQ_HSUSB_OTG OMAP44XX_HARDIRQ(92) /* High-Speed USB OTG controller */ 463239281Sgonzo#define OMAP44XX_IRQ_HSUSB_OTG_DMA OMAP44XX_HARDIRQ(93) /* High-Speed USB OTG DMA controller */ 464239281Sgonzo#define OMAP44XX_IRQ_MMC3 OMAP44XX_HARDIRQ(94) /* MMC/SD module 3 */ 465239281Sgonzo#define OMAP44XX_IRQ_RESERVED95 OMAP44XX_HARDIRQ(95) /* RESERVED */ 466239281Sgonzo#define OMAP44XX_IRQ_MMC4 OMAP44XX_HARDIRQ(96) /* MMC4 interrupt */ 467239281Sgonzo#define OMAP44XX_IRQ_SLIMBUS1 OMAP44XX_HARDIRQ(97) /* SLIMBUS1 interrupt */ 468239281Sgonzo#define OMAP44XX_IRQ_SLIMBUS2 OMAP44XX_HARDIRQ(98) /* SLIMBUS2 interrupt */ 469239281Sgonzo#define OMAP44XX_IRQ_ABE OMAP44XX_HARDIRQ(99) /* Audio back-end interrupt */ 470239281Sgonzo#define OMAP44XX_IRQ_CORTEXM3_MMU OMAP44XX_HARDIRQ(100) /* Cortex-M3 MMU interrupt */ 471239281Sgonzo#define OMAP44XX_IRQ_DSS_HDMI OMAP44XX_HARDIRQ(101) /* Display subsystem HDMI interrupt */ 472239281Sgonzo#define OMAP44XX_IRQ_SR_IVA OMAP44XX_HARDIRQ(102) /* SmartReflex IVA interrupt */ 473239281Sgonzo#define OMAP44XX_IRQ_IVAHD1 OMAP44XX_HARDIRQ(103) /* Sync interrupt from iCONT2 (vDMA) */ 474239281Sgonzo#define OMAP44XX_IRQ_IVAHD2 OMAP44XX_HARDIRQ(104) /* Sync interrupt from iCONT1 */ 475239281Sgonzo#define OMAP44XX_IRQ_RESERVED105 OMAP44XX_HARDIRQ(105) /* RESERVED */ 476239281Sgonzo#define OMAP44XX_IRQ_RESERVED106 OMAP44XX_HARDIRQ(106) /* RESERVED */ 477239281Sgonzo#define OMAP44XX_IRQ_IVAHD_MAILBOX0 OMAP44XX_HARDIRQ(107) /* IVAHD mailbox interrupt */ 478239281Sgonzo#define OMAP44XX_IRQ_RESERVED108 OMAP44XX_HARDIRQ(108) /* RESERVED */ 479239281Sgonzo#define OMAP44XX_IRQ_MCASP1 OMAP44XX_HARDIRQ(109) /* McASP1 transmit interrupt */ 480239281Sgonzo#define OMAP44XX_IRQ_EMIF1 OMAP44XX_HARDIRQ(110) /* EMIF1 interrupt */ 481239281Sgonzo#define OMAP44XX_IRQ_EMIF2 OMAP44XX_HARDIRQ(111) /* EMIF2 interrupt */ 482239281Sgonzo#define OMAP44XX_IRQ_MCPDM OMAP44XX_HARDIRQ(112) /* MCPDM interrupt */ 483239281Sgonzo#define OMAP44XX_IRQ_DMM OMAP44XX_HARDIRQ(113) /* DMM interrupt */ 484239281Sgonzo#define OMAP44XX_IRQ_DMIC OMAP44XX_HARDIRQ(114) /* DMIC interrupt */ 485239281Sgonzo#define OMAP44XX_IRQ_RESERVED115 OMAP44XX_HARDIRQ(115) /* RESERVED */ 486239281Sgonzo#define OMAP44XX_IRQ_RESERVED116 OMAP44XX_HARDIRQ(116) /* RESERVED */ 487239281Sgonzo#define OMAP44XX_IRQ_RESERVED117 OMAP44XX_HARDIRQ(117) /* RESERVED */ 488239281Sgonzo#define OMAP44XX_IRQ_RESERVED118 OMAP44XX_HARDIRQ(118) /* RESERVED */ 489239281Sgonzo#define OMAP44XX_IRQ_SYS_NIRQ2 OMAP44XX_HARDIRQ(119) /* External source 2 (active low) */ 490239281Sgonzo#define OMAP44XX_IRQ_KBD OMAP44XX_HARDIRQ(120) /* Keyboard controller interrupt */ 491239281Sgonzo#define OMAP44XX_IRQ_RESERVED121 OMAP44XX_HARDIRQ(121) /* RESERVED */ 492239281Sgonzo#define OMAP44XX_IRQ_RESERVED122 OMAP44XX_HARDIRQ(122) /* RESERVED */ 493239281Sgonzo#define OMAP44XX_IRQ_RESERVED123 OMAP44XX_HARDIRQ(123) /* RESERVED */ 494239281Sgonzo#define OMAP44XX_IRQ_RESERVED124 OMAP44XX_HARDIRQ(124) /* RESERVED */ 495239281Sgonzo#define OMAP44XX_IRQ_RESERVED125 OMAP44XX_HARDIRQ(125) /* RESERVED */ 496239281Sgonzo#define OMAP44XX_IRQ_RESERVED126 OMAP44XX_HARDIRQ(126) /* RESERVED */ 497239281Sgonzo#define OMAP44XX_IRQ_RESERVED127 OMAP44XX_HARDIRQ(127) /* RESERVED */ 498239281Sgonzo 499239281Sgonzo 500239281Sgonzo 501239281Sgonzo/* 502239281Sgonzo * General Purpose Timers 503239281Sgonzo */ 504239281Sgonzo#define OMAP44XX_GPTIMER1_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_GPTIMER1_OFFSET) 505239281Sgonzo#define OMAP44XX_GPTIMER1_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_GPTIMER1_OFFSET) 506239281Sgonzo#define OMAP44XX_GPTIMER2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER2_OFFSET) 507239281Sgonzo#define OMAP44XX_GPTIMER2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER2_OFFSET) 508239281Sgonzo#define OMAP44XX_GPTIMER3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER3_OFFSET) 509239281Sgonzo#define OMAP44XX_GPTIMER3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER3_OFFSET) 510239281Sgonzo#define OMAP44XX_GPTIMER4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER4_OFFSET) 511239281Sgonzo#define OMAP44XX_GPTIMER4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER4_OFFSET) 512239281Sgonzo#define OMAP44XX_GPTIMER5_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER5_OFFSET) 513239281Sgonzo#define OMAP44XX_GPTIMER5_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER5_OFFSET) 514239281Sgonzo#define OMAP44XX_GPTIMER6_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER6_OFFSET) 515239281Sgonzo#define OMAP44XX_GPTIMER6_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER6_OFFSET) 516239281Sgonzo#define OMAP44XX_GPTIMER7_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER7_OFFSET) 517239281Sgonzo#define OMAP44XX_GPTIMER7_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER7_OFFSET) 518239281Sgonzo#define OMAP44XX_GPTIMER8_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER8_OFFSET) 519239281Sgonzo#define OMAP44XX_GPTIMER8_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER8_OFFSET) 520239281Sgonzo#define OMAP44XX_GPTIMER9_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER9_OFFSET) 521239281Sgonzo#define OMAP44XX_GPTIMER9_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER9_OFFSET) 522239281Sgonzo#define OMAP44XX_GPTIMER10_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER10_OFFSET) 523239281Sgonzo#define OMAP44XX_GPTIMER10_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER10_OFFSET) 524239281Sgonzo#define OMAP44XX_GPTIMER11_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER11_OFFSET) 525239281Sgonzo#define OMAP44XX_GPTIMER11_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER11_OFFSET) 526239281Sgonzo#define OMAP44XX_GPTIMER_SIZE 0x00001000UL 527239281Sgonzo 528239281Sgonzo 529239281Sgonzo 530239281Sgonzo/* 531239281Sgonzo * GPIO - General Purpose IO 532239281Sgonzo */ 533239281Sgonzo 534239281Sgonzo/* Base addresses for the GPIO modules */ 535239281Sgonzo#define OMAP44XX_GPIO1_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_GPIO1_OFFSET) 536239281Sgonzo#define OMAP44XX_GPIO1_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_GPIO1_OFFSET) 537239281Sgonzo#define OMAP44XX_GPIO1_SIZE 0x00001000UL 538239281Sgonzo#define OMAP44XX_GPIO2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO2_OFFSET) 539239281Sgonzo#define OMAP44XX_GPIO2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO2_OFFSET) 540239281Sgonzo#define OMAP44XX_GPIO2_SIZE 0x00001000UL 541239281Sgonzo#define OMAP44XX_GPIO3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO3_OFFSET) 542239281Sgonzo#define OMAP44XX_GPIO3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO3_OFFSET) 543239281Sgonzo#define OMAP44XX_GPIO3_SIZE 0x00001000UL 544239281Sgonzo#define OMAP44XX_GPIO4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO4_OFFSET) 545239281Sgonzo#define OMAP44XX_GPIO4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO4_OFFSET) 546239281Sgonzo#define OMAP44XX_GPIO4_SIZE 0x00001000UL 547239281Sgonzo#define OMAP44XX_GPIO5_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO5_OFFSET) 548239281Sgonzo#define OMAP44XX_GPIO5_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO5_OFFSET) 549239281Sgonzo#define OMAP44XX_GPIO5_SIZE 0x00001000UL 550239281Sgonzo#define OMAP44XX_GPIO6_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO6_OFFSET) 551239281Sgonzo#define OMAP44XX_GPIO6_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO6_OFFSET) 552239281Sgonzo#define OMAP44XX_GPIO6_SIZE 0x00001000UL 553239281Sgonzo 554239281Sgonzo 555239281Sgonzo/* 556239281Sgonzo * MMC/SD/SDIO 557239281Sgonzo */ 558239281Sgonzo 559239281Sgonzo/* Base addresses for the MMC/SD/SDIO modules */ 560239281Sgonzo#define OMAP44XX_MMCHS1_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCHS1_OFFSET) 561239281Sgonzo#define OMAP44XX_MMCHS1_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCHS1_OFFSET) 562239281Sgonzo#define OMAP44XX_MMCHS2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCHS2_OFFSET) 563239281Sgonzo#define OMAP44XX_MMCHS2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCHS2_OFFSET) 564239281Sgonzo#define OMAP44XX_MMCHS3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCSD3_OFFSET) 565239281Sgonzo#define OMAP44XX_MMCHS3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCSD3_OFFSET) 566239281Sgonzo#define OMAP44XX_MMCHS4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCSD4_OFFSET) 567239281Sgonzo#define OMAP44XX_MMCHS4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCSD4_OFFSET) 568239281Sgonzo#define OMAP44XX_MMCHS5_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCSD5_OFFSET) 569239281Sgonzo#define OMAP44XX_MMCHS5_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCSD5_OFFSET) 570239281Sgonzo#define OMAP44XX_MMCHS_SIZE 0x00001000UL 571239281Sgonzo 572239281Sgonzo 573239281Sgonzo 574239281Sgonzo/* 575239281Sgonzo * SCM - System Control Module 576239281Sgonzo */ 577239281Sgonzo 578239281Sgonzo/* Base addresses for the SC modules */ 579239281Sgonzo#define OMAP44XX_SCM_PADCONF_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_SCM_PADCONF_OFFSET) 580239281Sgonzo#define OMAP44XX_SCM_PADCONF_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_SCM_PADCONF_OFFSET) 581239281Sgonzo#define OMAP44XX_SCM_PADCONF_SIZE 0x00001000UL 582239281Sgonzo 583239281Sgonzo 584239281Sgonzo 585239281Sgonzo 586239281Sgonzo#endif /* _OMAP44XX_REG_H_ */ 587