exynos_uart.h revision 252391
1162271Srwatson/* $NetBSD: s3c2xx0reg.h,v 1.4 2004/02/12 03:47:29 bsh Exp $ */ 2162271Srwatson 3172106Srwatson/*- 4162271Srwatson * Copyright (c) 2002, 2003 Fujitsu Component Limited 5162271Srwatson * Copyright (c) 2002, 2003 Genetec Corporation 6162271Srwatson * All rights reserved. 7162271Srwatson * 8162271Srwatson * Redistribution and use in source and binary forms, with or without 9162271Srwatson * modification, are permitted provided that the following conditions 10162271Srwatson * are met: 11162271Srwatson * 1. Redistributions of source code must retain the above copyright 12162271Srwatson * notice, this list of conditions and the following disclaimer. 13162271Srwatson * 2. Redistributions in binary form must reproduce the above copyright 14162271Srwatson * notice, this list of conditions and the following disclaimer in the 15162271Srwatson * documentation and/or other materials provided with the distribution. 16162271Srwatson * 3. Neither the name of The Fujitsu Component Limited nor the name of 17162271Srwatson * Genetec corporation may not be used to endorse or promote products 18162271Srwatson * derived from this software without specific prior written permission. 19162271Srwatson * 20162271Srwatson * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21162271Srwatson * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22162271Srwatson * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23162271Srwatson * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24162271Srwatson * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25162271Srwatson * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26162271Srwatson * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27162271Srwatson * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28162271Srwatson * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29162271Srwatson * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30162271Srwatson * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31162271Srwatson * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32162271Srwatson * SUCH DAMAGE. 33162271Srwatson * 34172106Srwatson * $FreeBSD: head/sys/arm/samsung/exynos/uart.h 252391 2013-06-29 23:39:05Z ray $ 35172106Srwatson */ 36172106Srwatson 37172106Srwatson/* s3c2410-specific registers */ 38172106Srwatson#define UMCON_AFC (1 << 4) /* auto flow control */ 39172106Srwatson#define UMSTAT_DCTS (1 << 2) /* CTS change */ 40162271Srwatson#define ULCON_IR (1 << 6) 41162271Srwatson#define ULCON_PARITY_SHIFT 3 42162271Srwatson 43162271Srwatson/* 44162271Srwatson * Exynos-specific 45162271Srwatson * 46162271Srwatson * UFSTAT_TXFULL register differs between Exynos and others. 47162271Srwatson * Others have UFSTAT_TXFULL (1 << 9) 48162271Srwatson */ 49162271Srwatson#define UFSTAT_TXFULL (1 << 24) 50162271Srwatson 51162271Srwatson#define SSCOM_UINTM 0x038 52162271Srwatson#define SSCOM_UINTP 0x030 53172106Srwatson 54162271Srwatson/* common for s3c2800 and s3c24x0 */ 55172106Srwatson#define SSCOM_ULCON 0x00 /* UART line control */ 56172106Srwatson#define ULCON_PARITY_NONE (0 << ULCON_PARITY_SHIFT) 57172106Srwatson#define ULCON_PARITY_ODD (4 << ULCON_PARITY_SHIFT) 58172106Srwatson#define ULCON_PARITY_EVEN (5 << ULCON_PARITY_SHIFT) 59172106Srwatson#define ULCON_PARITY_ONE (6 << ULCON_PARITY_SHIFT) 60162271Srwatson#define ULCON_PARITY_ZERO (7 << ULCON_PARITY_SHIFT) 61162271Srwatson#define ULCON_STOP (1 << 2) 62162271Srwatson#define ULCON_LENGTH_5 0 63162271Srwatson#define ULCON_LENGTH_6 1 64172106Srwatson#define ULCON_LENGTH_7 2 65172106Srwatson#define ULCON_LENGTH_8 3 66172106Srwatson#define SSCOM_UCON 0x04 /* UART control */ 67172106Srwatson#define UCON_TXINT_TYPE (1 << 9) /* Tx interrupt. 0=pulse,1=level */ 68172106Srwatson#define UCON_TXINT_TYPE_LEVEL UCON_TXINT_TYPE 69172106Srwatson#define UCON_TXINT_TYPE_PULSE 0 70172106Srwatson#define UCON_RXINT_TYPE (1 << 8) /* Rx interrupt */ 71172106Srwatson#define UCON_RXINT_TYPE_LEVEL UCON_RXINT_TYPE 72162271Srwatson#define UCON_RXINT_TYPE_PULSE 0 73172106Srwatson#define UCON_TOINT (1 << 7) /* Rx timeout interrupt */ 74172106Srwatson#define UCON_ERRINT (1 << 6) /* receive error interrupt */ 75172106Srwatson#define UCON_LOOP (1 << 5) /* loopback */ 76172106Srwatson#define UCON_SBREAK (1 << 4) /* send break */ 77172106Srwatson#define UCON_TXMODE_DISABLE (0 << 2) 78172106Srwatson#define UCON_TXMODE_INT (1 << 2) 79172106Srwatson#define UCON_TXMODE_DMA (2 << 2) 80172106Srwatson#define UCON_TXMODE_MASK (3 << 2) 81162271Srwatson#define UCON_RXMODE_DISABLE (0 << 0) 82172106Srwatson#define UCON_RXMODE_INT (1 << 0) 83172106Srwatson#define UCON_RXMODE_DMA (2 << 0) 84162271Srwatson#define UCON_RXMODE_MASK (3 << 0) 85172106Srwatson#define SSCOM_UFCON 0x08 /* FIFO control */ 86172106Srwatson#define UFCON_TXTRIGGER_0 (0 << 6) 87172106Srwatson#define UFCON_TXTRIGGER_4 (1 << 6) 88172106Srwatson#define UFCON_TXTRIGGER_8 (2 << 6) 89162271Srwatson#define UFCON_TXTRIGGER_16 (3 << 6) 90172106Srwatson#define UFCON_RXTRIGGER_4 (0 << 4) 91172106Srwatson#define UFCON_RXTRIGGER_8 (1 << 4) 92172106Srwatson#define UFCON_RXTRIGGER_12 (2 << 4) 93172106Srwatson#define UFCON_RXTRIGGER_16 (3 << 4) 94172106Srwatson#define UFCON_TXFIFO_RESET (1 << 2) 95172106Srwatson#define UFCON_RXFIFO_RESET (1 << 1) 96172106Srwatson#define UFCON_FIFO_ENABLE (1 << 0) 97172106Srwatson#define SSCOM_UMCON 0x0c /* MODEM control */ 98172106Srwatson#define UMCON_RTS (1 << 0) /* Request to send */ 99172106Srwatson#define SSCOM_UTRSTAT 0x10 /* Status register */ 100172106Srwatson#define UTRSTAT_TXSHIFTER_EMPTY ( 1<< 2) 101172106Srwatson#define UTRSTAT_TXEMPTY (1 << 1) /* TX fifo or buffer empty */ 102172106Srwatson#define UTRSTAT_RXREADY (1 << 0) /* RX fifo or buffer is not empty */ 103162271Srwatson#define SSCOM_UERSTAT 0x14 /* Error status register */ 104172106Srwatson#define UERSTAT_BREAK (1 << 3) /* Break signal, not 2410 */ 105172106Srwatson#define UERSTAT_FRAME (1 << 2) /* Frame error */ 106172106Srwatson#define UERSTAT_PARITY (1 << 1) /* Parity error, not 2410 */ 107172106Srwatson#define UERSTAT_OVERRUN (1 << 0) /* Overrun */ 108172106Srwatson#define UERSTAT_ALL_ERRORS \ 109172106Srwatson (UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY) 110172106Srwatson#define SSCOM_UFSTAT 0x18 /* Fifo status register */ 111172106Srwatson#define UFSTAT_RXFULL (1 <<8) /* Rx fifo full */ 112172106Srwatson#define UFSTAT_TXCOUNT_SHIFT 4 /* TX FIFO count */ 113172106Srwatson#define UFSTAT_TXCOUNT (0x0f << UFSTAT_TXCOUNT_SHIFT) 114172106Srwatson#define UFSTAT_RXCOUNT_SHIFT 0 /* RX FIFO count */ 115172106Srwatson#define UFSTAT_RXCOUNT (0x0f << UFSTAT_RXCOUNT_SHIFT) 116172106Srwatson#define SSCOM_UMSTAT 0x1c /* Modem status register */ 117172106Srwatson#define UMSTAT_CTS (1 << 0) /* Clear to send */ 118172106Srwatson#if _BYTE_ORDER == _LITTLE_ENDIAN 119172106Srwatson#define SSCOM_UTXH 0x20 /* Transmit data register */ 120172106Srwatson#define SSCOM_URXH 0x24 /* Receive data register */ 121172106Srwatson#else 122172106Srwatson#define SSCOM_UTXH 0x23 /* Transmit data register */ 123172106Srwatson#define SSCOM_URXH 0x27 /* Receive data register */ 124172106Srwatson#endif 125172106Srwatson#define SSCOM_UBRDIV 0x28 /* baud-reate divisor */ 126172106Srwatson#define SSCOM_SIZE 0x2c 127172106Srwatson