exynos5_combiner.c revision 269703 
1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/*
28 * Samsung Exynos 5 Interrupt Combiner
29 * Chapter 7, Exynos 5 Dual User's Manual Public Rev 1.00
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/arm/samsung/exynos/exynos5_combiner.c 269703 2014-08-08 06:30:17Z nwhitehorn $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/kernel.h>
39#include <sys/module.h>
40#include <sys/malloc.h>
41#include <sys/rman.h>
42#include <sys/timeet.h>
43#include <sys/timetc.h>
44#include <sys/watchdog.h>
45
46#include <dev/ofw/openfirm.h>
47#include <dev/ofw/ofw_bus.h>
48#include <dev/ofw/ofw_bus_subr.h>
49
50#include <machine/bus.h>
51#include <machine/cpu.h>
52#include <machine/intr.h>
53
54#include <arm/samsung/exynos/exynos5_common.h>
55#include <arm/samsung/exynos/exynos5_combiner.h>
56
57#define NGRP		32
58
59#define	IESR(n)	(0x10 * n + 0x0)	/* Interrupt enable set */
60#define	IECR(n)	(0x10 * n + 0x4)	/* Interrupt enable clear */
61#define	ISTR(n)	(0x10 * n + 0x8)	/* Interrupt status */
62#define	IMSR(n)	(0x10 * n + 0xC)	/* Interrupt masked status */
63#define	CIPSR	0x100			/* Combined interrupt pending */
64
65struct combiner_softc {
66	struct resource		*res[1 + NGRP];
67	bus_space_tag_t		bst;
68	bus_space_handle_t	bsh;
69	void			*ih[NGRP];
70	device_t		dev;
71};
72
73struct combiner_softc *combiner_sc;
74
75static struct resource_spec combiner_spec[] = {
76	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
77	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
78	{ SYS_RES_IRQ,		1,	RF_ACTIVE },
79	{ SYS_RES_IRQ,		2,	RF_ACTIVE },
80	{ SYS_RES_IRQ,		3,	RF_ACTIVE },
81	{ SYS_RES_IRQ,		4,	RF_ACTIVE },
82	{ SYS_RES_IRQ,		5,	RF_ACTIVE },
83	{ SYS_RES_IRQ,		6,	RF_ACTIVE },
84	{ SYS_RES_IRQ,		7,	RF_ACTIVE },
85	{ SYS_RES_IRQ,		8,	RF_ACTIVE },
86	{ SYS_RES_IRQ,		9,	RF_ACTIVE },
87	{ SYS_RES_IRQ,		10,	RF_ACTIVE },
88	{ SYS_RES_IRQ,		11,	RF_ACTIVE },
89	{ SYS_RES_IRQ,		12,	RF_ACTIVE },
90	{ SYS_RES_IRQ,		13,	RF_ACTIVE },
91	{ SYS_RES_IRQ,		14,	RF_ACTIVE },
92	{ SYS_RES_IRQ,		15,	RF_ACTIVE },
93	{ SYS_RES_IRQ,		16,	RF_ACTIVE },
94	{ SYS_RES_IRQ,		17,	RF_ACTIVE },
95	{ SYS_RES_IRQ,		18,	RF_ACTIVE },
96	{ SYS_RES_IRQ,		19,	RF_ACTIVE },
97	{ SYS_RES_IRQ,		20,	RF_ACTIVE },
98	{ SYS_RES_IRQ,		21,	RF_ACTIVE },
99	{ SYS_RES_IRQ,		22,	RF_ACTIVE },
100	{ SYS_RES_IRQ,		23,	RF_ACTIVE },
101	{ SYS_RES_IRQ,		24,	RF_ACTIVE },
102	{ SYS_RES_IRQ,		25,	RF_ACTIVE },
103	{ SYS_RES_IRQ,		26,	RF_ACTIVE },
104	{ SYS_RES_IRQ,		27,	RF_ACTIVE },
105	{ SYS_RES_IRQ,		28,	RF_ACTIVE },
106	{ SYS_RES_IRQ,		29,	RF_ACTIVE },
107	{ SYS_RES_IRQ,		30,	RF_ACTIVE },
108	{ SYS_RES_IRQ,		31,	RF_ACTIVE },
109	{ -1, 0 }
110};
111
112struct combiner_entry {
113	int combiner_id;
114	int bit;
115	char *source_name;
116};
117
118static struct combiner_entry interrupt_table[] = {
119	{ 63, 1, "EINT[15]" },
120	{ 63, 0, "EINT[14]" },
121	{ 62, 1, "EINT[13]" },
122	{ 62, 0, "EINT[12]" },
123	{ 61, 1, "EINT[11]" },
124	{ 61, 0, "EINT[10]" },
125	{ 60, 1, "EINT[9]" },
126	{ 60, 0, "EINT[8]" },
127	{ 59, 1, "EINT[7]" },
128	{ 59, 0, "EINT[6]" },
129	{ 58, 1, "EINT[5]" },
130	{ 58, 0, "EINT[4]" },
131	{ 57, 3, "MCT_G3" },
132	{ 57, 2, "MCT_G2" },
133	{ 57, 1, "EINT[3]" },
134	{ 57, 0, "EINT[2]" },
135	{ 56, 6, "SYSMMU_G2D[1]" },
136	{ 56, 5, "SYSMMU_G2D[0]" },
137	{ 56, 2, "SYSMMU_FIMC_LITE1[1]" },
138	{ 56, 1, "SYSMMU_FIMC_LITE1[0]" },
139	{ 56, 0, "EINT[1]" },
140	{ 55, 4, "MCT_G1" },
141	{ 55, 3, "MCT_G0" },
142	{ 55, 0, "EINT[0]" },
143	{ 54, 7, "CPU_nCNTVIRQ[1]" },
144	{ 54, 6, "CPU_nCTIIRQ[1]" },
145	{ 54, 5, "CPU_nCNTPSIRQ[1]" },
146	{ 54, 4, "CPU_nPMUIRQ[1]" },
147	{ 54, 3, "CPU_nCNTPNSIRQ[1]" },
148	{ 54, 2, "CPU_PARITYFAILSCU[1]" },
149	{ 54, 1, "CPU_nCNTHPIRQ[1]" },
150	{ 54, 0, "PARITYFAIL[1]" },
151	{ 53, 1, "CPU_nIRQ[1]" },
152	{ 52, 0, "CPU_nIRQ[0]" },
153	{ 51, 7, "CPU_nRAMERRIRQ" },
154	{ 51, 6, "CPU_nAXIERRIRQ" },
155	{ 51, 4, "INT_COMB_ISP_GIC" },
156	{ 51, 3, "INT_COMB_IOP_GIC" },
157	{ 51, 2, "CCI_nERRORIRQ" },
158	{ 51, 1, "INT_COMB_ARMISP_GIC" },
159	{ 51, 0, "INT_COMB_ARMIOP_GIC" },
160	{ 50, 7, "DISP1[3]" },
161	{ 50, 6, "DISP1[2]" },
162	{ 50, 5, "DISP1[1]" },
163	{ 50, 4, "DISP1[0]" },
164	{ 49, 3, "SSCM_PULSE_IRQ_C2CIF[1]" },
165	{ 49, 2, "SSCM_PULSE_IRQ_C2CIF[0]" },
166	{ 49, 1, "SSCM_IRQ_C2CIF[1]" },
167	{ 49, 0, "SSCM_IRQ_C2CIF[0]" },
168	{ 48, 3, "PEREV_M1_CDREX" },
169	{ 48, 2, "PEREV_M0_CDREX" },
170	{ 48, 1, "PEREV_A1_CDREX" },
171	{ 48, 0, "PEREV_A0_CDREX" },
172	{ 47, 3, "MDMA0_ABORT" },
173	/* 46 is fully reserved */
174	{ 45, 1, "MDMA1_ABORT" },
175	/* 44 is fully reserved */
176	{ 43, 7, "SYSMMU_DRCISP[1]" },
177	{ 43, 6, "SYSMMU_DRCISP[0]" },
178	{ 43, 1, "SYSMMU_ODC[1]" },
179	{ 43, 0, "SYSMMU_ODC[0]" },
180	{ 42, 7, "SYSMMU_ISP[1]" },
181	{ 42, 6, "SYSMMU_ISP[0]" },
182	{ 42, 5, "SYSMMU_DIS0[1]" },
183	{ 42, 4, "SYSMMU_DIS0[0]" },
184	{ 42, 3, "DP1" },
185	{ 41, 5, "SYSMMU_DIS1[1]" },
186	{ 41, 4, "SYSMMU_DIS1[0]" },
187	{ 40, 6, "SYSMMU_MFCL[1]" },
188	{ 40, 5, "SYSMMU_MFCL[0]" },
189	{ 39, 5, "SYSMMU_TV_M0[1]" },
190	{ 39, 4, "SYSMMU_TV_M0[0]" },
191	{ 39, 3, "SYSMMU_MDMA1[1]" },
192	{ 39, 2, "SYSMMU_MDMA1[0]" },
193	{ 39, 1, "SYSMMU_MDMA0[1]" },
194	{ 39, 0, "SYSMMU_MDMA0[0]" },
195	{ 38, 7, "SYSMMU_SSS[1]" },
196	{ 38, 6, "SYSMMU_SSS[0]" },
197	{ 38, 5, "SYSMMU_RTIC[1]" },
198	{ 38, 4, "SYSMMU_RTIC[0]" },
199	{ 38, 3, "SYSMMU_MFCR[1]" },
200	{ 38, 2, "SYSMMU_MFCR[0]" },
201	{ 38, 1, "SYSMMU_ARM[1]" },
202	{ 38, 0, "SYSMMU_ARM[0]" },
203	{ 37, 7, "SYSMMU_3DNR[1]" },
204	{ 37, 6, "SYSMMU_3DNR[0]" },
205	{ 37, 5, "SYSMMU_MCUISP[1]" },
206	{ 37, 4, "SYSMMU_MCUISP[0]" },
207	{ 37, 3, "SYSMMU_SCALERCISP[1]" },
208	{ 37, 2, "SYSMMU_SCALERCISP[0]" },
209	{ 37, 1, "SYSMMU_FDISP[1]" },
210	{ 37, 0, "SYSMMU_FDISP[0]" },
211	{ 36, 7, "MCUIOP_CTIIRQ" },
212	{ 36, 6, "MCUIOP_PMUIRQ" },
213	{ 36, 5, "MCUISP_CTIIRQ" },
214	{ 36, 4, "MCUISP_PMUIRQ" },
215	{ 36, 3, "SYSMMU_JPEGX[1]" },
216	{ 36, 2, "SYSMMU_JPEGX[0]" },
217	{ 36, 1, "SYSMMU_ROTATOR[1]" },
218	{ 36, 0, "SYSMMU_ROTATOR[0]" },
219	{ 35, 7, "SYSMMU_SCALERPISP[1]" },
220	{ 35, 6, "SYSMMU_SCALERPISP[0]" },
221	{ 35, 5, "SYSMMU_FIMC_LITE0[1]" },
222	{ 35, 4, "SYSMMU_FIMC_LITE0[0]" },
223	{ 35, 3, "SYSMMU_DISP1_M0[1]" },
224	{ 35, 2, "SYSMMU_DISP1_M0[0]" },
225	{ 35, 1, "SYSMMU_FIMC_LITE2[1]" },
226	{ 35, 0, "SYSMMU_FIMC_LITE2[0]" },
227	{ 34, 7, "SYSMMU_GSCL3[1]" },
228	{ 34, 6, "SYSMMU_GSCL3[0]" },
229	{ 34, 5, "SYSMMU_GSCL2[1]" },
230	{ 34, 4, "SYSMMU_GSCL2[0]" },
231	{ 34, 3, "SYSMMU_GSCL1[1]" },
232	{ 34, 2, "SYSMMU_GSCL1[0]" },
233	{ 34, 1, "SYSMMU_GSCL0[1]" },
234	{ 34, 0, "SYSMMU_GSCL0[0]" },
235	{ 33, 7, "CPU_nCNTVIRQ[0]" },
236	{ 33, 6, "CPU_nCNTPSIRQ[0]" },
237	{ 33, 5, "CPU_nCNTPSNIRQ[0]" },
238	{ 33, 4, "CPU_nCNTHPIRQ[0]" },
239	{ 33, 3, "CPU_nCTIIRQ[0]" },
240	{ 33, 2, "CPU_nPMUIRQ[0]" },
241	{ 33, 1, "CPU_PARITYFAILSCU[0]" },
242	{ 33, 0, "CPU_PARITYFAIL0" },
243	{ 32, 7, "TZASC_XR1BXW" },
244	{ 32, 6, "TZASC_XR1BXR" },
245	{ 32, 5, "TZASC_XLBXW" },
246	{ 32, 4, "TZASC_XLBXR" },
247	{ 32, 3, "TZASC_DRBXW" },
248	{ 32, 2, "TZASC_DRBXR" },
249	{ 32, 1, "TZASC_CBXW" },
250	{ 32, 0, "TZASC_CBXR" },
251
252	{ -1, -1, NULL },
253};
254
255struct combined_intr {
256	uint32_t	enabled;
257	void		(*ih) (void *);
258	void		*ih_user;
259};
260
261static struct combined_intr intr_map[32][8];
262
263static void
264combiner_intr(void *arg)
265{
266	struct combiner_softc *sc;
267	void (*ih) (void *);
268	void *ih_user;
269	int enabled;
270	int intrs;
271	int shift;
272	int cirq;
273	int grp;
274	int i,n;
275
276	sc = arg;
277
278	intrs = READ4(sc, CIPSR);
279	for (grp = 0; grp < 32; grp++) {
280		if (intrs & (1 << grp)) {
281			n = (grp / 4);
282			shift = (grp % 4) * 8;
283
284			cirq = READ4(sc, ISTR(n));
285			for (i = 0; i < 8; i++) {
286				if (cirq & (1 << (i + shift))) {
287					ih = intr_map[grp][i].ih;
288					ih_user = intr_map[grp][i].ih_user;
289					enabled = intr_map[grp][i].enabled;
290					if (enabled && (ih != NULL)) {
291						ih(ih_user);
292					}
293				}
294			}
295		}
296	}
297}
298
299void
300combiner_setup_intr(char *source_name, void (*ih)(void *), void *ih_user)
301{
302	struct combiner_entry *entry;
303	struct combined_intr *cirq;
304	struct combiner_softc *sc;
305	int shift;
306	int reg;
307	int grp;
308	int n;
309	int i;
310
311	sc = combiner_sc;
312
313	if (sc == NULL) {
314		device_printf(sc->dev, "Error: combiner is not attached\n");
315		return;
316	}
317
318	entry = NULL;
319
320	for (i = 0; i < NGRP && interrupt_table[i].bit != -1; i++) {
321		if (strcmp(interrupt_table[i].source_name, source_name) == 0) {
322			entry = &interrupt_table[i];
323		}
324	}
325
326	if (entry == NULL) {
327		device_printf(sc->dev, "Can't find interrupt name %s\n",
328		    source_name);
329		return;
330	}
331
332#if 0
333	device_printf(sc->dev, "Setting up interrupt %s\n", source_name);
334#endif
335
336	grp = entry->combiner_id - 32;
337
338	cirq = &intr_map[grp][entry->bit];
339	cirq->enabled = 1;
340	cirq->ih = ih;
341	cirq->ih_user = ih_user;
342
343	n = grp / 4;
344	shift = (grp % 4) * 8 + entry->bit;
345
346	reg = (1 << shift);
347	WRITE4(sc, IESR(n), reg);
348}
349
350static int
351combiner_probe(device_t dev)
352{
353
354	if (!ofw_bus_status_okay(dev))
355		return (ENXIO);
356
357	if (!ofw_bus_is_compatible(dev, "exynos,combiner"))
358		return (ENXIO);
359
360	device_set_desc(dev, "Samsung Exynos 5 Interrupt Combiner");
361	return (BUS_PROBE_DEFAULT);
362}
363
364static int
365combiner_attach(device_t dev)
366{
367	struct combiner_softc *sc;
368	int err;
369	int i;
370
371	sc = device_get_softc(dev);
372	sc->dev = dev;
373
374	if (bus_alloc_resources(dev, combiner_spec, sc->res)) {
375		device_printf(dev, "could not allocate resources\n");
376		return (ENXIO);
377	}
378
379	/* Memory interface */
380	sc->bst = rman_get_bustag(sc->res[0]);
381	sc->bsh = rman_get_bushandle(sc->res[0]);
382
383	combiner_sc = sc;
384
385        /* Setup interrupt handler */
386	for (i = 0; i < NGRP; i++) {
387		err = bus_setup_intr(dev, sc->res[1+i], INTR_TYPE_BIO | \
388		    INTR_MPSAFE, NULL, combiner_intr, sc, &sc->ih[i]);
389		if (err) {
390			device_printf(dev, "Unable to alloc int resource.\n");
391			return (ENXIO);
392		}
393	}
394
395	return (0);
396}
397
398static device_method_t combiner_methods[] = {
399	DEVMETHOD(device_probe,		combiner_probe),
400	DEVMETHOD(device_attach,	combiner_attach),
401	{ 0, 0 }
402};
403
404static driver_t combiner_driver = {
405	"combiner",
406	combiner_methods,
407	sizeof(struct combiner_softc),
408};
409
410static devclass_t combiner_devclass;
411
412DRIVER_MODULE(combiner, simplebus, combiner_driver, combiner_devclass, 0, 0);
413