exynos5_combiner.c revision 269369
1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Samsung Exynos 5 Interrupt Combiner 29 * Chapter 7, Exynos 5 Dual User's Manual Public Rev 1.00 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/arm/samsung/exynos/exynos5_combiner.c 269369 2014-08-01 06:20:25Z br $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39#include <sys/module.h> 40#include <sys/malloc.h> 41#include <sys/rman.h> 42#include <sys/timeet.h> 43#include <sys/timetc.h> 44#include <sys/watchdog.h> 45 46#include <dev/fdt/fdt_common.h> 47#include <dev/ofw/openfirm.h> 48#include <dev/ofw/ofw_bus.h> 49#include <dev/ofw/ofw_bus_subr.h> 50 51#include <machine/bus.h> 52#include <machine/fdt.h> 53#include <machine/cpu.h> 54#include <machine/intr.h> 55 56#include <arm/samsung/exynos/exynos5_common.h> 57#include <arm/samsung/exynos/exynos5_combiner.h> 58 59#define NGRP 32 60 61#define IESR(n) (0x10 * n + 0x0) /* Interrupt enable set */ 62#define IECR(n) (0x10 * n + 0x4) /* Interrupt enable clear */ 63#define ISTR(n) (0x10 * n + 0x8) /* Interrupt status */ 64#define IMSR(n) (0x10 * n + 0xC) /* Interrupt masked status */ 65#define CIPSR 0x100 /* Combined interrupt pending */ 66 67struct combiner_softc { 68 struct resource *res[1 + NGRP]; 69 bus_space_tag_t bst; 70 bus_space_handle_t bsh; 71 void *ih[NGRP]; 72 device_t dev; 73}; 74 75struct combiner_softc *combiner_sc; 76 77static struct resource_spec combiner_spec[] = { 78 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 79 { SYS_RES_IRQ, 0, RF_ACTIVE }, 80 { SYS_RES_IRQ, 1, RF_ACTIVE }, 81 { SYS_RES_IRQ, 2, RF_ACTIVE }, 82 { SYS_RES_IRQ, 3, RF_ACTIVE }, 83 { SYS_RES_IRQ, 4, RF_ACTIVE }, 84 { SYS_RES_IRQ, 5, RF_ACTIVE }, 85 { SYS_RES_IRQ, 6, RF_ACTIVE }, 86 { SYS_RES_IRQ, 7, RF_ACTIVE }, 87 { SYS_RES_IRQ, 8, RF_ACTIVE }, 88 { SYS_RES_IRQ, 9, RF_ACTIVE }, 89 { SYS_RES_IRQ, 10, RF_ACTIVE }, 90 { SYS_RES_IRQ, 11, RF_ACTIVE }, 91 { SYS_RES_IRQ, 12, RF_ACTIVE }, 92 { SYS_RES_IRQ, 13, RF_ACTIVE }, 93 { SYS_RES_IRQ, 14, RF_ACTIVE }, 94 { SYS_RES_IRQ, 15, RF_ACTIVE }, 95 { SYS_RES_IRQ, 16, RF_ACTIVE }, 96 { SYS_RES_IRQ, 17, RF_ACTIVE }, 97 { SYS_RES_IRQ, 18, RF_ACTIVE }, 98 { SYS_RES_IRQ, 19, RF_ACTIVE }, 99 { SYS_RES_IRQ, 20, RF_ACTIVE }, 100 { SYS_RES_IRQ, 21, RF_ACTIVE }, 101 { SYS_RES_IRQ, 22, RF_ACTIVE }, 102 { SYS_RES_IRQ, 23, RF_ACTIVE }, 103 { SYS_RES_IRQ, 24, RF_ACTIVE }, 104 { SYS_RES_IRQ, 25, RF_ACTIVE }, 105 { SYS_RES_IRQ, 26, RF_ACTIVE }, 106 { SYS_RES_IRQ, 27, RF_ACTIVE }, 107 { SYS_RES_IRQ, 28, RF_ACTIVE }, 108 { SYS_RES_IRQ, 29, RF_ACTIVE }, 109 { SYS_RES_IRQ, 30, RF_ACTIVE }, 110 { SYS_RES_IRQ, 31, RF_ACTIVE }, 111 { -1, 0 } 112}; 113 114struct combiner_entry { 115 int combiner_id; 116 int bit; 117 char *source_name; 118}; 119 120static struct combiner_entry interrupt_table[] = { 121 { 63, 1, "EINT[15]" }, 122 { 63, 0, "EINT[14]" }, 123 { 62, 1, "EINT[13]" }, 124 { 62, 0, "EINT[12]" }, 125 { 61, 1, "EINT[11]" }, 126 { 61, 0, "EINT[10]" }, 127 { 60, 1, "EINT[9]" }, 128 { 60, 0, "EINT[8]" }, 129 { 59, 1, "EINT[7]" }, 130 { 59, 0, "EINT[6]" }, 131 { 58, 1, "EINT[5]" }, 132 { 58, 0, "EINT[4]" }, 133 { 57, 3, "MCT_G3" }, 134 { 57, 2, "MCT_G2" }, 135 { 57, 1, "EINT[3]" }, 136 { 57, 0, "EINT[2]" }, 137 { 56, 6, "SYSMMU_G2D[1]" }, 138 { 56, 5, "SYSMMU_G2D[0]" }, 139 { 56, 2, "SYSMMU_FIMC_LITE1[1]" }, 140 { 56, 1, "SYSMMU_FIMC_LITE1[0]" }, 141 { 56, 0, "EINT[1]" }, 142 { 55, 4, "MCT_G1" }, 143 { 55, 3, "MCT_G0" }, 144 { 55, 0, "EINT[0]" }, 145 { 54, 7, "CPU_nCNTVIRQ[1]" }, 146 { 54, 6, "CPU_nCTIIRQ[1]" }, 147 { 54, 5, "CPU_nCNTPSIRQ[1]" }, 148 { 54, 4, "CPU_nPMUIRQ[1]" }, 149 { 54, 3, "CPU_nCNTPNSIRQ[1]" }, 150 { 54, 2, "CPU_PARITYFAILSCU[1]" }, 151 { 54, 1, "CPU_nCNTHPIRQ[1]" }, 152 { 54, 0, "PARITYFAIL[1]" }, 153 { 53, 1, "CPU_nIRQ[1]" }, 154 { 52, 0, "CPU_nIRQ[0]" }, 155 { 51, 7, "CPU_nRAMERRIRQ" }, 156 { 51, 6, "CPU_nAXIERRIRQ" }, 157 { 51, 4, "INT_COMB_ISP_GIC" }, 158 { 51, 3, "INT_COMB_IOP_GIC" }, 159 { 51, 2, "CCI_nERRORIRQ" }, 160 { 51, 1, "INT_COMB_ARMISP_GIC" }, 161 { 51, 0, "INT_COMB_ARMIOP_GIC" }, 162 { 50, 7, "DISP1[3]" }, 163 { 50, 6, "DISP1[2]" }, 164 { 50, 5, "DISP1[1]" }, 165 { 50, 4, "DISP1[0]" }, 166 { 49, 3, "SSCM_PULSE_IRQ_C2CIF[1]" }, 167 { 49, 2, "SSCM_PULSE_IRQ_C2CIF[0]" }, 168 { 49, 1, "SSCM_IRQ_C2CIF[1]" }, 169 { 49, 0, "SSCM_IRQ_C2CIF[0]" }, 170 { 48, 3, "PEREV_M1_CDREX" }, 171 { 48, 2, "PEREV_M0_CDREX" }, 172 { 48, 1, "PEREV_A1_CDREX" }, 173 { 48, 0, "PEREV_A0_CDREX" }, 174 { 47, 3, "MDMA0_ABORT" }, 175 /* 46 is fully reserved */ 176 { 45, 1, "MDMA1_ABORT" }, 177 /* 44 is fully reserved */ 178 { 43, 7, "SYSMMU_DRCISP[1]" }, 179 { 43, 6, "SYSMMU_DRCISP[0]" }, 180 { 43, 1, "SYSMMU_ODC[1]" }, 181 { 43, 0, "SYSMMU_ODC[0]" }, 182 { 42, 7, "SYSMMU_ISP[1]" }, 183 { 42, 6, "SYSMMU_ISP[0]" }, 184 { 42, 5, "SYSMMU_DIS0[1]" }, 185 { 42, 4, "SYSMMU_DIS0[0]" }, 186 { 42, 3, "DP1" }, 187 { 41, 5, "SYSMMU_DIS1[1]" }, 188 { 41, 4, "SYSMMU_DIS1[0]" }, 189 { 40, 6, "SYSMMU_MFCL[1]" }, 190 { 40, 5, "SYSMMU_MFCL[0]" }, 191 { 39, 5, "SYSMMU_TV_M0[1]" }, 192 { 39, 4, "SYSMMU_TV_M0[0]" }, 193 { 39, 3, "SYSMMU_MDMA1[1]" }, 194 { 39, 2, "SYSMMU_MDMA1[0]" }, 195 { 39, 1, "SYSMMU_MDMA0[1]" }, 196 { 39, 0, "SYSMMU_MDMA0[0]" }, 197 { 38, 7, "SYSMMU_SSS[1]" }, 198 { 38, 6, "SYSMMU_SSS[0]" }, 199 { 38, 5, "SYSMMU_RTIC[1]" }, 200 { 38, 4, "SYSMMU_RTIC[0]" }, 201 { 38, 3, "SYSMMU_MFCR[1]" }, 202 { 38, 2, "SYSMMU_MFCR[0]" }, 203 { 38, 1, "SYSMMU_ARM[1]" }, 204 { 38, 0, "SYSMMU_ARM[0]" }, 205 { 37, 7, "SYSMMU_3DNR[1]" }, 206 { 37, 6, "SYSMMU_3DNR[0]" }, 207 { 37, 5, "SYSMMU_MCUISP[1]" }, 208 { 37, 4, "SYSMMU_MCUISP[0]" }, 209 { 37, 3, "SYSMMU_SCALERCISP[1]" }, 210 { 37, 2, "SYSMMU_SCALERCISP[0]" }, 211 { 37, 1, "SYSMMU_FDISP[1]" }, 212 { 37, 0, "SYSMMU_FDISP[0]" }, 213 { 36, 7, "MCUIOP_CTIIRQ" }, 214 { 36, 6, "MCUIOP_PMUIRQ" }, 215 { 36, 5, "MCUISP_CTIIRQ" }, 216 { 36, 4, "MCUISP_PMUIRQ" }, 217 { 36, 3, "SYSMMU_JPEGX[1]" }, 218 { 36, 2, "SYSMMU_JPEGX[0]" }, 219 { 36, 1, "SYSMMU_ROTATOR[1]" }, 220 { 36, 0, "SYSMMU_ROTATOR[0]" }, 221 { 35, 7, "SYSMMU_SCALERPISP[1]" }, 222 { 35, 6, "SYSMMU_SCALERPISP[0]" }, 223 { 35, 5, "SYSMMU_FIMC_LITE0[1]" }, 224 { 35, 4, "SYSMMU_FIMC_LITE0[0]" }, 225 { 35, 3, "SYSMMU_DISP1_M0[1]" }, 226 { 35, 2, "SYSMMU_DISP1_M0[0]" }, 227 { 35, 1, "SYSMMU_FIMC_LITE2[1]" }, 228 { 35, 0, "SYSMMU_FIMC_LITE2[0]" }, 229 { 34, 7, "SYSMMU_GSCL3[1]" }, 230 { 34, 6, "SYSMMU_GSCL3[0]" }, 231 { 34, 5, "SYSMMU_GSCL2[1]" }, 232 { 34, 4, "SYSMMU_GSCL2[0]" }, 233 { 34, 3, "SYSMMU_GSCL1[1]" }, 234 { 34, 2, "SYSMMU_GSCL1[0]" }, 235 { 34, 1, "SYSMMU_GSCL0[1]" }, 236 { 34, 0, "SYSMMU_GSCL0[0]" }, 237 { 33, 7, "CPU_nCNTVIRQ[0]" }, 238 { 33, 6, "CPU_nCNTPSIRQ[0]" }, 239 { 33, 5, "CPU_nCNTPSNIRQ[0]" }, 240 { 33, 4, "CPU_nCNTHPIRQ[0]" }, 241 { 33, 3, "CPU_nCTIIRQ[0]" }, 242 { 33, 2, "CPU_nPMUIRQ[0]" }, 243 { 33, 1, "CPU_PARITYFAILSCU[0]" }, 244 { 33, 0, "CPU_PARITYFAIL0" }, 245 { 32, 7, "TZASC_XR1BXW" }, 246 { 32, 6, "TZASC_XR1BXR" }, 247 { 32, 5, "TZASC_XLBXW" }, 248 { 32, 4, "TZASC_XLBXR" }, 249 { 32, 3, "TZASC_DRBXW" }, 250 { 32, 2, "TZASC_DRBXR" }, 251 { 32, 1, "TZASC_CBXW" }, 252 { 32, 0, "TZASC_CBXR" }, 253 254 { -1, -1, NULL }, 255}; 256 257struct combined_intr { 258 uint32_t enabled; 259 void (*ih) (void *); 260 void *ih_user; 261}; 262 263static struct combined_intr intr_map[32][8]; 264 265static void 266combiner_intr(void *arg) 267{ 268 struct combiner_softc *sc; 269 void (*ih) (void *); 270 void *ih_user; 271 int enabled; 272 int intrs; 273 int shift; 274 int cirq; 275 int grp; 276 int i,n; 277 278 sc = arg; 279 280 intrs = READ4(sc, CIPSR); 281 for (grp = 0; grp < 32; grp++) { 282 if (intrs & (1 << grp)) { 283 n = (grp / 4); 284 shift = (grp % 4) * 8; 285 286 cirq = READ4(sc, ISTR(n)); 287 for (i = 0; i < 8; i++) { 288 if (cirq & (1 << (i + shift))) { 289 ih = intr_map[grp][i].ih; 290 ih_user = intr_map[grp][i].ih_user; 291 enabled = intr_map[grp][i].enabled; 292 if (enabled && (ih != NULL)) { 293 ih(ih_user); 294 } 295 } 296 } 297 } 298 } 299} 300 301void 302combiner_setup_intr(char *source_name, void (*ih)(void *), void *ih_user) 303{ 304 struct combiner_entry *entry; 305 struct combined_intr *cirq; 306 struct combiner_softc *sc; 307 int shift; 308 int reg; 309 int grp; 310 int n; 311 int i; 312 313 sc = combiner_sc; 314 315 if (sc == NULL) { 316 device_printf(sc->dev, "Error: combiner is not attached\n"); 317 return; 318 } 319 320 entry = NULL; 321 322 for (i = 0; i < NGRP && interrupt_table[i].bit != -1; i++) { 323 if (strcmp(interrupt_table[i].source_name, source_name) == 0) { 324 entry = &interrupt_table[i]; 325 } 326 } 327 328 if (entry == NULL) { 329 device_printf(sc->dev, "Can't find interrupt name %s\n", 330 source_name); 331 return; 332 } 333 334#if 0 335 device_printf(sc->dev, "Setting up interrupt %s\n", source_name); 336#endif 337 338 grp = entry->combiner_id - 32; 339 340 cirq = &intr_map[grp][entry->bit]; 341 cirq->enabled = 1; 342 cirq->ih = ih; 343 cirq->ih_user = ih_user; 344 345 n = grp / 4; 346 shift = (grp % 4) * 8 + entry->bit; 347 348 reg = (1 << shift); 349 WRITE4(sc, IESR(n), reg); 350} 351 352static int 353combiner_probe(device_t dev) 354{ 355 356 if (!ofw_bus_status_okay(dev)) 357 return (ENXIO); 358 359 if (!ofw_bus_is_compatible(dev, "exynos,combiner")) 360 return (ENXIO); 361 362 device_set_desc(dev, "Samsung Exynos 5 Interrupt Combiner"); 363 return (BUS_PROBE_DEFAULT); 364} 365 366static int 367combiner_attach(device_t dev) 368{ 369 struct combiner_softc *sc; 370 int err; 371 int i; 372 373 sc = device_get_softc(dev); 374 sc->dev = dev; 375 376 if (bus_alloc_resources(dev, combiner_spec, sc->res)) { 377 device_printf(dev, "could not allocate resources\n"); 378 return (ENXIO); 379 } 380 381 /* Memory interface */ 382 sc->bst = rman_get_bustag(sc->res[0]); 383 sc->bsh = rman_get_bushandle(sc->res[0]); 384 385 combiner_sc = sc; 386 387 /* Setup interrupt handler */ 388 for (i = 0; i < NGRP; i++) { 389 err = bus_setup_intr(dev, sc->res[1+i], INTR_TYPE_BIO | \ 390 INTR_MPSAFE, NULL, combiner_intr, sc, &sc->ih[i]); 391 if (err) { 392 device_printf(dev, "Unable to alloc int resource.\n"); 393 return (ENXIO); 394 } 395 } 396 397 return (0); 398} 399 400static device_method_t combiner_methods[] = { 401 DEVMETHOD(device_probe, combiner_probe), 402 DEVMETHOD(device_attach, combiner_attach), 403 { 0, 0 } 404}; 405 406static driver_t combiner_driver = { 407 "combiner", 408 combiner_methods, 409 sizeof(struct combiner_softc), 410}; 411 412static devclass_t combiner_devclass; 413 414DRIVER_MODULE(combiner, simplebus, combiner_driver, combiner_devclass, 0, 0); 415