1296936Smmel/*- 2296936Smmel * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3296936Smmel * All rights reserved. 4296936Smmel * 5296936Smmel * Redistribution and use in source and binary forms, with or without 6296936Smmel * modification, are permitted provided that the following conditions 7296936Smmel * are met: 8296936Smmel * 1. Redistributions of source code must retain the above copyright 9296936Smmel * notice, this list of conditions and the following disclaimer. 10296936Smmel * 2. Redistributions in binary form must reproduce the above copyright 11296936Smmel * notice, this list of conditions and the following disclaimer in the 12296936Smmel * documentation and/or other materials provided with the distribution. 13296936Smmel * 14296936Smmel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15296936Smmel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16296936Smmel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17296936Smmel * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18296936Smmel * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19296936Smmel * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20296936Smmel * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21296936Smmel * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22296936Smmel * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23296936Smmel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24296936Smmel * SUCH DAMAGE. 25296936Smmel * 26296936Smmel * $FreeBSD: releng/11.0/sys/arm/nvidia/tegra_efuse.h 296936 2016-03-16 13:01:48Z mmel $ 27296936Smmel */ 28296936Smmel 29296936Smmel#ifndef _TEGRA_EFUSE_H_ 30296936Smmel 31296936Smmelenum tegra_revision { 32296936Smmel TEGRA_REVISION_UNKNOWN = 0, 33296936Smmel TEGRA_REVISION_A01, 34296936Smmel TEGRA_REVISION_A02, 35296936Smmel TEGRA_REVISION_A03, 36296936Smmel TEGRA_REVISION_A03p, 37296936Smmel TEGRA_REVISION_A04, 38296936Smmel}; 39296936Smmel 40296936Smmelstruct tegra_sku_info { 41296936Smmel u_int chip_id; 42296936Smmel u_int sku_id; 43296936Smmel u_int cpu_process_id; 44296936Smmel u_int cpu_speedo_id; 45296936Smmel u_int cpu_speedo_value; 46296936Smmel u_int cpu_iddq_value; 47296936Smmel u_int soc_process_id; 48296936Smmel u_int soc_speedo_id; 49296936Smmel u_int soc_speedo_value; 50296936Smmel u_int soc_iddq_value; 51296936Smmel u_int gpu_process_id; 52296936Smmel u_int gpu_speedo_id; 53296936Smmel u_int gpu_speedo_value; 54296936Smmel u_int gpu_iddq_value; 55296936Smmel enum tegra_revision revision; 56296936Smmel}; 57296936Smmel 58296936Smmelextern struct tegra_sku_info tegra_sku_info; 59296936Smmeluint32_t tegra_fuse_read_4(int addr); 60296936Smmel 61296936Smmel#endif /* _TEGRA_EFUSE_H_ */ 62