1183840Sraj/*-
2183840Sraj * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3183840Sraj * All rights reserved.
4183840Sraj *
5183840Sraj * Developed by Semihalf.
6183840Sraj *
7183840Sraj * Redistribution and use in source and binary forms, with or without
8183840Sraj * modification, are permitted provided that the following conditions
9183840Sraj * are met:
10183840Sraj * 1. Redistributions of source code must retain the above copyright
11183840Sraj *    notice, this list of conditions and the following disclaimer.
12183840Sraj * 2. Redistributions in binary form must reproduce the above copyright
13183840Sraj *    notice, this list of conditions and the following disclaimer in the
14183840Sraj *    documentation and/or other materials provided with the distribution.
15183840Sraj * 3. Neither the name of MARVELL nor the names of contributors
16183840Sraj *    may be used to endorse or promote products derived from this software
17183840Sraj *    without specific prior written permission.
18183840Sraj *
19183840Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20183840Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21183840Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22183840Sraj * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23183840Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24183840Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25183840Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29183840Sraj * SUCH DAMAGE.
30183840Sraj */
31183840Sraj
32183840Sraj#include <sys/cdefs.h>
33183840Sraj__FBSDID("$FreeBSD: releng/11.0/sys/arm/mv/orion/db88f5xxx.c 298627 2016-04-26 11:53:37Z br $");
34183840Sraj
35183840Sraj#include <sys/param.h>
36183840Sraj#include <sys/systm.h>
37183840Sraj#include <sys/bus.h>
38183840Sraj#include <sys/kernel.h>
39183840Sraj
40183840Sraj#include <vm/vm.h>
41183840Sraj#include <vm/pmap.h>
42183840Sraj
43186909Sraj#include <machine/bus.h>
44194072Smarcel#include <machine/intr.h>
45183840Sraj#include <machine/vmparam.h>
46183840Sraj
47183840Sraj#include <arm/mv/mvreg.h>
48183840Sraj#include <arm/mv/mvvar.h>
49194072Smarcel#include <arm/mv/mvwin.h>
50183840Sraj
51183840Sraj/*
52183840Sraj * Virtual address space layout:
53183840Sraj * -----------------------------
54183840Sraj * 0x0000_0000 - 0xbfff_ffff	: user process
55183840Sraj *
56183840Sraj * 0xc040_0000 - virtual_avail	: kernel reserved (text, data, page tables
57183840Sraj *				: structures, ARM stacks etc.)
58183840Sraj * virtual_avail - 0xefff_ffff	: KVA (virtual_avail is typically < 0xc0a0_0000)
59183840Sraj * 0xf000_0000 - 0xf0ff_ffff	: no-cache allocation area (16MB)
60183840Sraj * 0xf100_0000 - 0xf10f_ffff	: SoC integrated devices registers range (1MB)
61185089Sraj * 0xf110_0000 - 0xf11f_ffff	: PCI-Express I/O space (1MB)
62185089Sraj * 0xf120_0000 - 0xf12f_ffff	: PCI I/O space (1MB)
63185089Sraj * 0xf130_0000 - 0xf52f_ffff	: PCI-Express memory space (64MB)
64185089Sraj * 0xf530_0000 - 0xf92f_ffff	: PCI memory space (64MB)
65185089Sraj * 0xf930_0000 - 0xfffe_ffff	: unused (~108MB)
66183840Sraj * 0xffff_0000 - 0xffff_0fff	: 'high' vectors page (4KB)
67183840Sraj * 0xffff_1000 - 0xffff_1fff	: ARM_TP_ADDRESS/RAS page (4KB)
68183840Sraj * 0xffff_2000 - 0xffff_ffff	: unused (~55KB)
69183840Sraj */
70183840Sraj
71209131Sraj
72209131Sraj#if 0
73185089Srajint platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin);
74183840Sraj
75183840Sraj/* Static device mappings. */
76298627Sbrconst struct devmap_entry db88f5xxx_devmap[] = {
77183840Sraj	/*
78183840Sraj	 * Map the on-board devices VA == PA so that we can access them
79183840Sraj	 * with the MMU on or off.
80183840Sraj	 */
81183840Sraj	{ /* SoC integrated peripherals registers range */
82183840Sraj		MV_BASE,
83183840Sraj		MV_PHYS_BASE,
84183840Sraj		MV_SIZE,
85183840Sraj	},
86183840Sraj	{ /* PCIE I/O */
87183840Sraj		MV_PCIE_IO_BASE,
88183840Sraj		MV_PCIE_IO_PHYS_BASE,
89183840Sraj		MV_PCIE_IO_SIZE,
90183840Sraj	},
91183840Sraj	{ /* PCIE Memory */
92183840Sraj		MV_PCIE_MEM_BASE,
93183840Sraj		MV_PCIE_MEM_PHYS_BASE,
94183840Sraj		MV_PCIE_MEM_SIZE,
95183840Sraj	},
96183840Sraj	{ /* PCI I/O */
97183840Sraj		MV_PCI_IO_BASE,
98183840Sraj		MV_PCI_IO_PHYS_BASE,
99183840Sraj		MV_PCI_IO_SIZE,
100183840Sraj	},
101183840Sraj	{ /* PCI Memory */
102183840Sraj		MV_PCI_MEM_BASE,
103183840Sraj		MV_PCI_MEM_PHYS_BASE,
104183840Sraj		MV_PCI_MEM_SIZE,
105183840Sraj	},
106183840Sraj	{ /* 7-seg LED */
107183840Sraj		MV_DEV_CS0_BASE,
108183840Sraj		MV_DEV_CS0_PHYS_BASE,
109183840Sraj		MV_DEV_CS0_SIZE,
110183840Sraj	},
111295694Sskra	{ 0, 0, 0, }
112183840Sraj};
113183840Sraj
114186932Sraj/*
115186932Sraj * The pci_irq_map table consists of 3 columns:
116186932Sraj * - PCI slot number (less than zero means ANY).
117186932Sraj * - PCI IRQ pin (less than zero means ANY).
118186932Sraj * - PCI IRQ (less than zero marks end of table).
119186932Sraj *
120186932Sraj * IRQ number from the first matching entry is used to configure PCI device
121186932Sraj */
122183840Sraj
123186932Sraj/* PCI IRQ Map for DB-88F5281 */
124186932Srajconst struct obio_pci_irq_map pci_irq_map[] = {
125186932Sraj	{ 7, -1, GPIO2IRQ(12) },
126186932Sraj	{ 8, -1, GPIO2IRQ(13) },
127186932Sraj	{ 9, -1, GPIO2IRQ(13) },
128186932Sraj	{ -1, -1, -1 }
129186932Sraj};
130183840Sraj
131186932Sraj/* PCI IRQ Map for DB-88F5182 */
132186932Srajconst struct obio_pci_irq_map pci_irq_map[] = {
133186932Sraj	{ 7, -1, GPIO2IRQ(0) },
134186932Sraj	{ 8, -1, GPIO2IRQ(1) },
135186932Sraj	{ 9, -1, GPIO2IRQ(1) },
136186932Sraj	{ -1, -1, -1 }
137186932Sraj};
138186932Sraj#endif
139183840Sraj
140209131Sraj#if 0
141186909Sraj/*
142186909Sraj * mv_gpio_config row structure:
143186909Sraj *	<GPIO number>, <GPIO flags>, <GPIO mode>
144186909Sraj *
145186909Sraj * - GPIO pin number (less than zero marks end of table)
146186909Sraj * - GPIO flags:
147186909Sraj *	MV_GPIO_BLINK
148186909Sraj *	MV_GPIO_POLAR_LOW
149186909Sraj *	MV_GPIO_EDGE
150186909Sraj *	MV_GPIO_LEVEL
151186909Sraj * - GPIO mode:
152186909Sraj *	1	- Output, set to HIGH.
153186909Sraj *	0	- Output, set to LOW.
154186909Sraj *	-1	- Input.
155186909Sraj */
156186909Sraj
157186909Sraj/* GPIO Configuration for DB-88F5281 */
158186909Srajconst struct gpio_config mv_gpio_config[] = {
159186909Sraj	{ 12, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
160186909Sraj	{ 13, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
161186909Sraj	{ -1, -1, -1 }
162186909Sraj};
163186909Sraj
164186909Sraj#if 0
165186909Sraj/* GPIO Configuration for DB-88F5182 */
166186909Srajconst struct gpio_config mv_gpio_config[] = {
167186909Sraj	{ 0, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
168186909Sraj	{ 1, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
169186909Sraj	{ -1, -1, -1 }
170186909Sraj};
171186909Sraj#endif
172186909Sraj
173186909Sraj#endif
174